udb 0.1.15 → 0.1.17

data/.data/spec/std/isa/csr/H/hie.yaml

@@ -0,0 +1,74 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hie
+long_name: Hypervisor Interrupt Enable Register
+description: |
+  The `hie` register is a read/write register in HS-mode that enables interrupts.
+  It corresponds to the enable bits for VS-level and hypervisor-specific interrupts, and supplements
+  the HS-level `sie` register.
+address: 0x604
+writable: true
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  # TODO: For each writable bit in sie, the corresponding bit shall be read-only zero in both hip and hie.
+
+  SGEIE:
+    location: 12
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Hypervisor guest external interrupt enable bit. When set, allows external interrupts to be delivered
+      to VS-mode based on the `hgeie` setting.
+    sw_write(csr_value): |
+      if (CSR[mideleg].SGEI == 0) {
+        return 0;
+      }
+      return csr_value.SGEIE;
+
+  VSEIE:
+    location: 10
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level external interrupt enable bit. When set, allows external interrupts directed to VS-level
+      to be processed based on the configuration in `hvip` and other platform-specific sources.
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSEI == 0) {
+        return 0;
+      }
+      return csr_value.VSEIE;
+
+  VSTIE:
+    location: 6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level timer interrupt enable bit. When set, allows VS-level timer interrupts to be processed
+      based on the `hvip` configuration and any platform-specific timer interrupts.
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSTI == 0) {
+        return 0;
+      }
+      return csr_value.VSTIE;
+
+  VSSIE:
+    location: 2
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level software interrupt enable bit. When set, allows software interrupts directed to VS-level
+      to be processed, based on the configuration in `hvip`.
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSSI == 0) {
+        return 0;
+      }
+      return csr_value.VSSIE;

data/.data/spec/std/isa/csr/H/hip.yaml

@@ -0,0 +1,88 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hip
+long_name: Hypervisor Interrupt Pending Register
+writable: true
+description: |
+  The `hip` register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level.
+  It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts.
+address: 0x608
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+sw_read(): |
+  XReg res = 0;
+
+  # SGEIP: 1 iff bitwise AND of hgeip and hgeie is nonzero
+  if (($bits(CSR[hgeie]) & $bits(CSR[hgeip])) != 0) {
+    res[12] = 1'b1;
+  }
+
+  # VSEIP: logical OR of hvip.VSEIP and platform-specific sources
+  if (CSR[hvip].VSEIP == 1'b1) {
+    res[10] = 1'b1;
+  }
+
+  # VSTIP: logical OR of hvip.VSTIP and vstimecmp comparison (if Sstc)
+  if (implemented?(ExtensionName::Sstc)) {
+    if ((CSR[hvip].VSTIP == 1'b1) || ((read_mtime() + CSR[htimedelta].DELTA) >= CSR[vstimecmp].TIME)) {
+      res[6] = 1'b1;
+    }
+  } else {
+    if (CSR[hvip].VSTIP == 1'b1) {
+      res[6] = 1'b1;
+    }
+  }
+
+  # VSSIP: alias of hvip.VSSIP
+  if (CSR[hvip].VSSIP == 1'b1) {
+    res[2] = 1'b1;
+  }
+
+  return res;
+length: SXLEN
+fields:
+  # TODO: For each writable bit in sie, the corresponding bit shall be read-only zero in both hip and hie.
+
+  SGEIP:
+    location: 12
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for supervisor guest external interrupts (SGEI).
+      This bit is 1 if and only if the logical AND of `hgeip` and `hgeie` is nonzero.
+
+  VSEIP:
+    location: 10
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level external interrupts (VSEI).
+      This bit is the logical OR of `vseip` from `hvip`, the interrupt from `hgeip` selected by `hstatus.VGEIN`,
+      and any other external interrupt signal directed to VS-level.
+
+  VSTIP:
+    location: 6
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level timer interrupts (VSTI).
+      This bit is the logical OR of `vstip` from `hvip` and any other timer interrupt directed to VS-level.
+
+  VSSIP:
+    location: 2
+    type: RO-H
+    reset_value: 0
+    sw_write(csr_value): |
+      # VSSIP in hip is an alias of VSSIP in hvip
+      CSR[hvip].VSSIP = csr_value.VSSIP;
+      return csr_value.VSSIP;
+    description: |
+      Pending interrupt bit for VS-level software interrupts (VSSI).
+      This bit is an alias of the `vssip` bit in `hvip`.

data/.data/spec/std/isa/csr/H/htimedeltah.yaml

@@ -29,4 +29,4 @@ fields:
       CSR[htimedelta].DELTA = {csr_value.DELTA, CSR[htimedelta].DELTA[31:0]};
       return csr_value.DELTA;
 sw_read(): |
-  return CSR[htimedelta].DELTA[31:0];
+  return CSR[htimedelta].DELTA[63:32];

data/.data/spec/std/isa/csr/H/hvip.yaml

@@ -0,0 +1,46 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hvip
+long_name: Hypervisor Virtual Interrupt Pending Register
+description: |
+  The `hvip` register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.
+  It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts.
+address: 0x645
+writable: true
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  VSEIP:
+    location: 10
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending interrupt bit for VS-level external interrupts. This bit is writable and
+      is set to 1 to assert a VS-level external interrupt.
+      TODO: assert the interrupt
+
+  VSTIP:
+    location: 6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending interrupt bit for VS-level timer interrupts. This bit is writable and
+      is set to 1 to assert a VS-level timer interrupt.
+      TODO: assert the interrupt
+
+  VSSIP:
+    location: 2
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending interrupt bit for VS-level software interrupts. This bit is writable and
+      is set to 1 to assert a VS-level software interrupt.
+      TODO: assert the interrupt

data/.data/spec/std/isa/csr/H/vsie.yaml

@@ -0,0 +1,86 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vsie
+long_name: Virtual Supervisor Interrupt Enable
+description: |
+  The vsie register is a VSXLEN-bit read/write register that is VS-mode’s version of
+  supervisor CSR sie. When V=1, vsie substitutes for the usual sie, so instructions that
+  normally read or modify sie actually access vsie instead. However, interrupts directed to
+  HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1.
+
+  When bit 13 of hideleg is zero, vsie.LCOFIE is read-only zero. Else, vsie.LCOFIE is an alias of sie.LCOFIE.
+  When bit 10 of hideleg is zero, vsie.SEIE is read-only zero. Else, vsie.SEIE is an alias of hie.VSEIE.
+  When bit 6 of hideleg is zero, vsie.STIE is read-only zero. Else, vsie.STIE is an alias of hie.VSTIE.
+  When bit 2 of hideleg is zero, vsie.SSIE is read-only zero. Else, vsie.SSIE is an alias of hie.VSSIE.
+address: 0x204
+virtual_address: 0x104
+writable: true
+priv_mode: VS
+definedBy:
+  extension:
+    name: H
+sw_read(): |
+  XReg result = 0;
+  if (CSR[hideleg].VSSI == 1) {
+    result[1] = CSR[hie].VSSIE;
+  }
+  if (CSR[hideleg].VSTI == 1) {
+    result[5] = CSR[hie].VSTIE;
+  }
+  if (CSR[hideleg].VSEI == 1) {
+    result[9] = CSR[hie].VSEIE;
+  }
+  if (CSR[hideleg].LCOFI == 1) {
+    result[13] = CSR[sie].LCOFIE;
+  }
+  return result;
+length: VSXLEN
+fields:
+  SSIE:
+    location: 1
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].VSSI == 1) {
+        CSR[hie].VSSIE = csr_value.SSIE;
+      }
+    description: |
+      SSIE. Read-only zero when hideleg.VSSI is 0. Else, alias of hie.VSSIE.
+
+  STIE:
+    location: 5
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].VSTI == 1) {
+        CSR[hie].VSTIE = csr_value.STIE;
+      }
+    description: |
+      STIE. Read-only zero when hideleg.VSTI is 0. Else, alias of hie.VSTIE.
+
+  SEIE:
+    location: 9
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].VSEI == 1) {
+        CSR[hie].VSEIE = csr_value.SEIE;
+      }
+    description: |
+      SEIE. Read-only zero when hideleg.VSEI is 0. Else, alias of hie.VSEIE.
+
+  LCOFIE:
+    location: 13
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].LCOFI == 1) {
+        CSR[sie].LCOFIE = csr_value.LCOFIE;
+      }
+    description: |
+      LCOFIE. Read-only zero when hideleg.LCOFI is 0. Else, alias of sie.LCOFIE.

data/.data/spec/std/isa/csr/H/vsip.yaml

@@ -0,0 +1,98 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vsip
+long_name: Virtual Supervisor Interrupt Pending
+description: |
+  The `vsip` register is a VSXLEN-bit read/write register that is VS-mode’s version of the `sip` CSR.
+  When V=1, instructions that normally access `sip` instead access `vsip`. It holds the pending
+  interrupt status for supervisor-level traps in a virtualized environment.
+
+  However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register,
+  not in `vsip`, when V=1.
+
+  The standard portion (bits 15:0) includes individual interrupt-pending bits.
+address: 0x244
+virtual_address: 0x144
+writable: true
+priv_mode: VS
+definedBy:
+  extension:
+    name: H
+sw_read(): |
+  XReg result = 0;
+  if (CSR[hideleg].VSSI == 1) {
+    result[1] = CSR[hip].VSSIP;
+  }
+  if (CSR[hideleg].VSTI == 1) {
+    result[5] = CSR[hip].VSTIP;
+  }
+  if (CSR[hideleg].VSEI == 1) {
+    result[9] = CSR[hip].VSEIP;
+  }
+  if (implemented?(ExtensionName::Sscofpmf)) {
+    if (CSR[hideleg].LCOFI == 1) {
+      result[13] = CSR[sip].LCOFIP;
+    }
+  }
+  return result;
+length: VSXLEN
+fields:
+  SSIP:
+    location: 1
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].VSSI == 1) {
+        CSR[hip].VSSIP = csr_value.SSIP;
+      }
+    description: |
+      *Supervisor Software Interrupt Pending*
+      Indicates a pending software interrupt at the supervisor level.
+      Read-only zero when `hideleg.VSSI == 0`, else aliased to `hip.VSSIP`.
+
+  STIP:
+    location: 5
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].VSTI == 1) {
+        CSR[hip].VSTIP = csr_value.STIP;
+      }
+    description: |
+      *Supervisor Timer Interrupt Pending*
+      Indicates a pending timer interrupt at the supervisor level.
+      Read-only zero when `hideleg.VSTI == 0`, else aliased to `hip.VSTIP`.
+
+  SEIP:
+    location: 9
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].VSEI == 1) {
+        CSR[hip].VSEIP = csr_value.SEIP;
+      }
+    description: |
+      *Supervisor External Interrupt Pending*
+      Indicates a pending external interrupt at the supervisor level.
+      Read-only zero when `hideleg.VSEI == 0`, else aliased to `hip.VSEIP`.
+
+  LCOFIP:
+    definedBy:
+      extension:
+        name: Sscofpmf
+    location: 13
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[hideleg].LCOFI == 1) {
+        CSR[sip].LCOFIP = csr_value.LCOFIP;
+      }
+    description: |
+      *Local Counter Overflow Interrupt Pending*
+      Indicates an overflow of a local counter.
+      Read-only zero when `hideleg.LCOFI == 0`, else aliased to `sip.LCOFIP`.

data/.data/spec/std/isa/csr/H/vsscratch.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vsscratch
+address: 0x240
+virtual_address: 0x140
+long_name: Virtual Supervisor Scratch Register
+writable: true
+description: |
+  The vsscratch register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sscratch.
+  When V=1, vsscratch substitutes for the usual sscratch, so instructions that normally read or modify sscratch actually access vsscratch instead.
+  The contents of vsscratch never directly affect the behavior of the machine.
+priv_mode: VS
+length: VSXLEN
+definedBy:
+  extension:
+    name: H
+fields:
+  SCRATCH:
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    location_rv32: 31-0
+    location_rv64: 63-0
+    description: |
+      Virtual supervisor scratch register.

data/.data/spec/std/isa/csr/I/pmpaddr0.yaml

@@ -48,16 +48,16 @@ fields:
         return csr_value.ADDR;
       }
 sw_read(): |
-  # when the mode is NAPOT and PMP_GRANULARITY >= 16,
+  # when the mode is NAPOT and PMP_GRANULARITY >= 4,
   # bits (PMP_GRANULARITY-4):0 must read as ones
   if (MXLEN == 32) {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg0].pmp0cfg[4] == 1)) {
       return CSR[pmpaddr0].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg0].pmp0cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr0].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
       return CSR[pmpaddr0].ADDR;
     }
   } else {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg0].pmp0cfg[4] == 1)) {
       return CSR[pmpaddr0].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg0].pmp0cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr0].ADDR & ~mask;

data/.data/spec/std/isa/csr/I/pmpaddr1.yaml

@@ -48,16 +48,16 @@ fields:
         return csr_value.ADDR;
       }
 sw_read(): |
-  # when the mode is NAPOT and PMP_GRANULARITY >= 16,
+  # when the mode is NAPOT and PMP_GRANULARITY >= 4,
   # bits (PMP_GRANULARITY-4):0 must read as ones
   if (MXLEN == 32) {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg0].pmp1cfg[4] == 1)) {
       return CSR[pmpaddr1].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg0].pmp1cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr1].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
       return CSR[pmpaddr1].ADDR;
     }
   } else {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg0].pmp1cfg[4] == 1)) {
       return CSR[pmpaddr1].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg0].pmp1cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr1].ADDR & ~mask;

data/.data/spec/std/isa/csr/I/pmpaddr10.yaml

@@ -48,16 +48,16 @@ fields:
         return csr_value.ADDR;
       }
 sw_read(): |
-  # when the mode is NAPOT and PMP_GRANULARITY >= 16,
+  # when the mode is NAPOT and PMP_GRANULARITY >= 4,
   # bits (PMP_GRANULARITY-4):0 must read as ones
   if (MXLEN == 32) {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg2].pmp10cfg[4] == 1)) {
       return CSR[pmpaddr10].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg2].pmp10cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr10].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
       return CSR[pmpaddr10].ADDR;
     }
   } else {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg2].pmp10cfg[4] == 1)) {
       return CSR[pmpaddr10].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg2].pmp10cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr10].ADDR & ~mask;

data/.data/spec/std/isa/csr/I/pmpaddr11.yaml

@@ -48,16 +48,16 @@ fields:
         return csr_value.ADDR;
       }
 sw_read(): |
-  # when the mode is NAPOT and PMP_GRANULARITY >= 16,
+  # when the mode is NAPOT and PMP_GRANULARITY >= 4,
   # bits (PMP_GRANULARITY-4):0 must read as ones
   if (MXLEN == 32) {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg2].pmp11cfg[4] == 1)) {
       return CSR[pmpaddr11].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg2].pmp11cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr11].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
       return CSR[pmpaddr11].ADDR;
     }
   } else {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg2].pmp11cfg[4] == 1)) {
       return CSR[pmpaddr11].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg2].pmp11cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr11].ADDR & ~mask;

data/.data/spec/std/isa/csr/I/pmpaddr12.yaml

@@ -48,16 +48,16 @@ fields:
         return csr_value.ADDR;
       }
 sw_read(): |
-  # when the mode is NAPOT and PMP_GRANULARITY >= 16,
+  # when the mode is NAPOT and PMP_GRANULARITY >= 4,
   # bits (PMP_GRANULARITY-4):0 must read as ones
   if (MXLEN == 32) {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg3].pmp12cfg[4] == 1)) {
       return CSR[pmpaddr12].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg3].pmp12cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr12].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
       return CSR[pmpaddr12].ADDR;
     }
   } else {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg2].pmp12cfg[4] == 1)) {
       return CSR[pmpaddr12].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg2].pmp12cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr12].ADDR & ~mask;

data/.data/spec/std/isa/csr/I/pmpaddr13.yaml

@@ -48,16 +48,16 @@ fields:
         return csr_value.ADDR;
       }
 sw_read(): |
-  # when the mode is NAPOT and PMP_GRANULARITY >= 16,
+  # when the mode is NAPOT and PMP_GRANULARITY >= 4,
   # bits (PMP_GRANULARITY-4):0 must read as ones
   if (MXLEN == 32) {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg3].pmp13cfg[4] == 1)) {
       return CSR[pmpaddr13].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg3].pmp13cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr13].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
       return CSR[pmpaddr13].ADDR;
     }
   } else {
-    if ((PMP_GRANULARITY >= 16) &&
+    if ((PMP_GRANULARITY >= 4) &&
         (CSR[pmpcfg2].pmp13cfg[4] == 1)) {
       return CSR[pmpaddr13].ADDR | {PMP_GRANULARITY-3{1'b1}};
 
-    # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
+    # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
     # bits (PMP_GRANULARITY-3):0 must read as zeros
-    } else if ((PMP_GRANULARITY >= 8) &&
+    } else if ((PMP_GRANULARITY >= 3) &&
                 (CSR[pmpcfg2].pmp13cfg[4] == 0)) {
       Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
       return CSR[pmpaddr13].ADDR & ~mask;