udb 0.1.15 → 0.1.17

data/.data/spec/std/isa/csr/tcontrol.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: "csr_schema.json#"
+kind: csr
+name: tcontrol
+long_name: Trigger Control
+address: 0x7A5
+priv_mode: M
+length: XLEN
+writable: true
+description: |
+  This optional register is only accessible in M-mode and Debug Mode and provides
+  various control bits related to triggers.
+definedBy:
+  extension:
+    name: Sdtrig
+fields:
+  MPTE:
+    location: 7
+    description: |
+      M-mode previous trigger enable field.
+      MPTE and MTE provide one solution to a problem regarding triggers with action=0
+      firing in M-mode trap handlers.
+      When any trap into M-mode is taken, MPTE is set to the value of MTE.
+    type: RW-H
+    reset_value: 0
+  MTE:
+    location: 3
+    description: |
+      M-mode trigger enable field.
+      0 (disabled):: Triggers with action=0 do not match/fire while the hart is in M-mode.
+      1 (enabled):: Triggers do match/fire while the hart is in M-mode.
+      When any trap into M-mode is taken, MTE is set to 0. When `mret` is executed, MTE is
+      set to the value of MPTE.
+    type: RW-H
+    reset_value: 0

data/.data/spec/std/isa/csr/time.yaml

@@ -79,7 +79,7 @@ sw_read(): |
     }
   } else if (mode() == PrivilegeMode::VU) {
     # access in VU mode
-    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].IR == 1'b1)) {
+    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].TM == 1'b1)) {
       raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
     } else if (CSR[mcounteren].TM == 1'b0) {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/csr/timeh.yaml

@@ -80,7 +80,7 @@ sw_read(): |
     }
   } else if (mode() == PrivilegeMode::VU) {
     # access in VU mode
-    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].IR == 1'b1)) {
+    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].TM == 1'b1)) {
       raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
     } else if (CSR[mcounteren].TM == 1'b0) {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/csr/tinfo.yaml

@@ -0,0 +1,44 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: "csr_schema.json#"
+kind: csr
+name: tinfo
+long_name: Trigger Info
+address: 0x7A4
+priv_mode: M
+length: XLEN
+writable: true
+description: |
+  This register provides access to the trigger selected by `tselect`.
+  The reset values listed here apply to every underlying trigger.
+
+  This register is optional if no triggers are implemented, or if `type` is not writable
+  and `version` would be 0. In this case the debugger can read the only supported type
+  from `tdata1`.
+
+  Writing this read/write CSR has no effect.
+definedBy:
+  extension:
+    name: Sdtrig
+fields:
+  VERSION:
+    location: 31-24
+    description: |
+      Contains the version of the Sdtrig extension implemented.
+
+      0 (0):: Supports triggers as described in this spec at commit 5a5c078, made on
+      February 2, 2023.
+
+      1 (1):: Supports triggers as described in the ratified version 1.0 of this document.
+    type: RO
+    reset_value: UNDEFINED_LEGAL
+  TYPES:
+    location: 15-0
+    description: |
+      One bit for each possible `type` enumerated in `tdata1`. Bit N corresponds to type N.
+      If the bit is set, then that type is supported by the currently selected trigger.
+
+      If the currently selected trigger doesn't exist, this field contains 1.
+    type: RO
+    reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/vsepc.yaml

@@ -11,7 +11,7 @@ address: 0x241
 writable: true
 virtual_address: 0x141
 priv_mode: VS
-length: 64
+length: VSXLEN
 description: |
   Written with the PC of an instruction on an exception or interrupt taken in VS-mode.
 
@@ -21,7 +21,8 @@ definedBy:
     name: H
 fields:
   PC:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       When a trap is taken into VS-mode, `vsepc.PC` is written with the virtual address of the
       instruction that was interrupted or that encountered the exception.
@@ -39,14 +40,14 @@ fields:
       When `misa.C` is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
       may be visible on the next read with `misa.C` is set.
 
-      Holds bits 63:<%= ext?(:C) ? 2 : 1 %> of the virtual address associated with an exception.
+      Holds bits [VSXLEN-1:<%= ext?(:C) ? 2 : 1 %>] of the virtual address associated with an exception.
     type: RW-RH
     sw_write(csr_value): |
       return csr_value.PC & ~64'b1;
     reset_value: UNDEFINED_LEGAL
 sw_read(): |
   if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
-    return CSR[sepc].PC & ~64'b1;
+    return CSR[vsepc].PC & ~64'b1;
   } else {
-    return CSR[sepc].PC;
+    return CSR[vsepc].PC;
   }

data/.data/spec/std/isa/csr/vstvec.yaml

@@ -11,19 +11,20 @@ address: 0x205
 writable: true
 virtual_address: 0x105
 priv_mode: VS
-length: 64
+length: VSXLEN
 description: Controls where traps jump.
 definedBy:
   extension:
     name: H
 fields:
   BASE:
-    location: 63-2
+    location_rv32: 31-2
+    location_rv64: 63-2
     description: |
       <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 48 : 39) -%>
-      Bits 63:2 of the virtual address of the exception vector for any trap taken into VS-mode.
+      Bits [VSXLEN-1:2] of the virtual address of the exception vector for any trap taken into VS-mode.
 
-      If the base address is written with a non-canonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
+      If the base address is written with a non-canonical address (_i.e._, bits [VSXLEN-1:<%= va_size %>] do not match bit <%= va_size-1 %>),
       the write should be ignored.
 
     type: RW-R

data/.data/spec/std/isa/ext/M.yaml

@@ -12,6 +12,10 @@ versions:
   - version: "2.0.0"
     state: ratified
     ratification_date: 2019-12
+    requirements:
+      extension:
+        name: Zmmul
+        version: "~> 1.0.0"
 description: |
   This chapter describes the standard integer multiplication and division
   instruction extension, which is named `M` and contains instructions

data/.data/spec/std/isa/ext/Shgatpa.yaml

@@ -26,6 +26,7 @@ requirements:
     implemented?(ExtensionName::Sv39) -> SV39X4_TRANSLATION;
     implemented?(ExtensionName::Sv48) -> SV48X4_TRANSLATION;
     implemented?(ExtensionName::Sv57) -> SV57X4_TRANSLATION;
+    -> GSTAGE_MODE_BARE;
   reason: |
     Shgatpa mandates that or each supported virtual memory scheme SvNN supported in
     `satp`, the corresponding hgatp SvNNx4 mode must be supported.

data/.data/spec/std/isa/ext/Smctr.yaml

@@ -51,7 +51,7 @@ requirements:
   extension:
     allOf:
       - name: S
-        version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified
+        version: ~> 1.13 # The latest ratified version of S when Ssctr was ratified
       - name: Smcsrind
         version: ~> 1.0
       - name: Ssctr

data/.data/spec/std/isa/ext/Ssctr.yaml

@@ -18,6 +18,6 @@ requirements:
   extension:
     allOf:
       - name: S
-        version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified
+        version: ~> 1.13 # The latest ratified version of S when Ssctr was ratified
       - name: Sscsrind
         version: ~> 1.0

data/.data/spec/std/isa/ext/Ssstrict.yaml

@@ -43,9 +43,9 @@ versions:
 requirements:
   allOf:
     - param:
-        name: TRAP_ON_UNIMPLEMENTED_INSTRUCTION
+        name: TRAP_ON_RESERVED_INSTRUCTION
         equal: true
-        reason: Ssstrict requires unimplemented opcodes to trap
+        reason: Ssstrict requires unimplemented opcodes in the standard or reserved encoding spaces to trap
     - param:
         name: TRAP_ON_UNIMPLEMENTED_CSR
         equal: true

data/.data/spec/std/isa/ext/Sv32.yaml

@@ -6,8 +6,8 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sv32
-long_name: 32-bit virtual address translation (3 level)
-description: 32-bit virtual address translation (3 level)
+long_name: 32-bit virtual address translation (2 level)
+description: 32-bit virtual address translation (2 level)
 type: privileged
 versions:
   - version: "1.0"

data/.data/spec/std/isa/ext/Svpbmt.yaml

@@ -8,8 +8,8 @@ kind: extension
 name: Svpbmt
 long_name: Page-based memory types
 description: |
-  This extension mandates that the `satp` mode Bare must
-  be supported.
+  This extension specifies page-based memory types, adding the PBMT field
+  to page-table entries to control memory type, cacheability, and ordering attributes.
 type: privileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Zaamo.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zaamo
-long_name: Load-acquire/Store-release atomic instructions
+long_name: Atomic Memory Operations
 type: unprivileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Zbc.yaml

@@ -17,6 +17,10 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2021-06
+    requirements:
+      extension:
+        name: Zbkc
+        version: "~> 1.0.0"
     repositories:
       - url: https://github.com/riscv/riscv-bitmanip
         branch: main

data/.data/spec/std/isa/ext/Zibi.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zibi
+long_name: Branch with Immediate
+description: |
+  The Zibi extension adds conditional branch instructions that compare an
+  integer register with a small immediate constant.
+
+  Existing conditional branch instructions, such as `beq` and `bne`, compare two
+  integer registers. When a branch compares against a constant, software must
+  otherwise materialize that constant in an integer register before branching,
+  which can increase register pressure and potentially cause register spills and
+  reloads.
+
+  The `beqi` and `bnei` instructions use the B-type instruction format. The
+  instruction bits that would otherwise carry _rs2_ in a B-type branch carry a
+  5-bit _cimm_ field. All _cimm_ encodings are valid: the _cimm_ field is not
+  sign-extended; it decodes to an XLEN-bit comparison constant where `cimm=0`
+  encodes the value -1, and `cimm` values 1 through 31 encode the corresponding
+  positive integer values 1 through 31.
+type: unprivileged
+versions:
+  - version: "0.7.0"
+    state: frozen

data/.data/spec/std/isa/ext/Zvfbfa.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfbfa
+long_name: Vector Extension for Additional BF16 Computation
+type: unprivileged
+description: |
+ The Zvfbfa extension adds more complete BF16 vector compute support.
+ Zvfbfa is compatible with, but does not require, Zvfbfwma and Zvfbfmin.
+versions:
+ - version: "0.8.0"
+   # date: 2026-06-08
+   # commit: f15df74e95e56ad5fabdc9edcf0f1c907d29040a
+   state: development
+   repositories:
+     - url: https://github.com/riscv/riscv-isa-manual
+       branch: zvfbfa
+requirements:
+ extension:
+   allOf:
+     - name: Zve32f
+     - name: Zfbfmin

data/.data/spec/std/isa/ext/Zvfofp4min.yaml

@@ -0,0 +1,21 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfofp4min
+long_name: Vector OFP4 Conversion Extension
+type: unprivileged
+description: |
+ The Zvfofp4min extension provides basic vector conversion support for
+ the OFP4 E2M1 format.
+versions:
+ - version: "0.1.0"
+   state: development
+   # commit: e1e20a75c9a9fa797519fcc11ee997c7a7be4503
+   repositories:
+     - url: https://github.com/aswaterman/riscv-misc
+       branch: main
+requirements:
+ extension:
+   name: Zve32f

data/.data/spec/std/isa/ext/Zvfofp8min.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfofp8min
+long_name: Vector OFP8 Conversion Extension
+description: |
+ The Zvfofp8min extension provides basic vector conversion support for the
+ 8-bit floating-point formats OFP8 E4M3 and OFP8 E5M2.
+type: unprivileged
+versions:
+ - version: "0.9.0"
+   state: development
+   repositories:
+     - url: https://github.com/riscv/riscv-isa-manual
+       branch: zvfofp8min
+requirements:
+ extension:
+   name: Zve32f

data/.data/spec/std/isa/inst/B/andn.yaml

@@ -32,8 +32,4 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs1] & ~X[xs2];

data/.data/spec/std/isa/inst/B/orn.yaml

@@ -31,8 +31,4 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs1] | ~X[xs2];

data/.data/spec/std/isa/inst/B/rev8.yaml

@@ -45,10 +45,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg input = X[xs1];
   XReg output = 0;
 

data/.data/spec/std/isa/inst/B/rol.yaml

@@ -31,10 +31,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0];
 
   X[xd] = (X[xs1] << shamt) | (X[xs1] >> (xlen() - shamt));

data/.data/spec/std/isa/inst/B/rolw.yaml

@@ -34,10 +34,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_word = X[xs1][31:0];
   XReg shamt = X[xs2][4:0];
 

data/.data/spec/std/isa/inst/B/ror.yaml

@@ -31,10 +31,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0];
 
   X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt));

data/.data/spec/std/isa/inst/B/rori.yaml

@@ -42,10 +42,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg shamt = (xlen() == 32) ? shamt[4:0] : shamt[5:0];
 
   X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt));

data/.data/spec/std/isa/inst/B/roriw.yaml

@@ -35,11 +35,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_word = X[xs1][31:0];
 
-  XReg unextended_result = (X[xs1] >> shamt) | (X[xs1] << (32 - shamt));
+  XReg unextended_result = (xs1_word >> shamt) | (xs1_word << (32 - shamt));
   X[xd] = {{32{unextended_result[31]}}, unextended_result};

data/.data/spec/std/isa/inst/B/rorw.yaml

@@ -35,12 +35,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_word = X[xs1][31:0];
   XReg shamt = X[xs2][4:0];
 
-  XReg unextended_result = (X[xs1] >> shamt) | (X[xs1] << (32 - shamt));
+  XReg unextended_result = (xs1_word >> shamt) | (xs1_word << (32 - shamt));
   X[xd] = {{32{unextended_result[31]}}, unextended_result};

data/.data/spec/std/isa/inst/B/xnor.yaml

@@ -31,8 +31,4 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = ~(X[xs1] ^ X[xs2]);

data/.data/spec/std/isa/inst/C/c.addi.yaml

@@ -33,8 +33,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = X[xd] + $signed(imm);

data/.data/spec/std/isa/inst/C/c.addi16sp.yaml

@@ -30,8 +30,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[2] = X[2] + $signed(imm);

data/.data/spec/std/isa/inst/C/c.addi4spn.yaml

@@ -31,8 +31,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[creg2reg(xd)] = X[2] + imm;

data/.data/spec/std/isa/inst/C/c.addiw.yaml

@@ -34,8 +34,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = sext((X[xd] + sext(imm, 6)), 32);

data/.data/spec/std/isa/inst/C/c.beqz.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   if (X[creg2reg(xs1)] == 0) {
     jump($pc + $signed(imm));

data/.data/spec/std/isa/inst/C/c.bnez.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   if (X[creg2reg(xs1)] != 0) {
     jump($pc + $signed(imm));

data/.data/spec/std/isa/inst/C/c.ebreak.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   if (TRAP_ON_EBREAK) {
     raise_precise(ExceptionCode::Breakpoint, mode(), $pc);

data/.data/spec/std/isa/inst/C/c.j.yaml

@@ -27,8 +27,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   jump($pc + $signed(imm));

data/.data/spec/std/isa/inst/C/c.jal.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg return_addr = $pc + 2;

data/.data/spec/std/isa/inst/C/c.jalr.yaml

@@ -26,8 +26,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   XReg addr = X[xs1];
   XReg returnaddr;

data/.data/spec/std/isa/inst/C/c.jr.yaml

@@ -26,8 +26,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   jump(X[xs1]);

data/.data/spec/std/isa/inst/C/c.ld.yaml

@@ -50,8 +50,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   if (xlen() == 32) {

data/.data/spec/std/isa/inst/C/c.ldsp.yaml

@@ -49,8 +49,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;