udb 0.1.15 → 0.1.17

data/.data/spec/std/isa/inst/Zabha/amoor.h.aqrl.yaml

@@ -37,13 +37,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b1, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b1, $encoding), 16);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoor.h.rl.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b1, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b1, $encoding), 16);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoor.h.yaml

@@ -37,9 +37,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b0, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b0, $encoding), 16);

data/.data/spec/std/isa/inst/Zabha/amoswap.b.aq.yaml

@@ -36,11 +36,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding), 8);

data/.data/spec/std/isa/inst/Zabha/amoswap.b.aqrl.yaml

@@ -36,13 +36,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding), 8);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoswap.b.rl.yaml

@@ -36,11 +36,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding), 8);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoswap.b.yaml

@@ -36,9 +36,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding), 8);

data/.data/spec/std/isa/inst/Zabha/amoswap.h.aq.yaml

@@ -36,11 +36,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding), 16);

data/.data/spec/std/isa/inst/Zabha/amoswap.h.aqrl.yaml

@@ -36,13 +36,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding), 16);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoswap.h.rl.yaml

@@ -36,11 +36,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding), 16);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoswap.h.yaml

@@ -36,9 +36,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding), 16);

data/.data/spec/std/isa/inst/Zabha/amoxor.b.aq.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding), 8);

data/.data/spec/std/isa/inst/Zabha/amoxor.b.aqrl.yaml

@@ -37,13 +37,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding), 8);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoxor.b.rl.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding), 8);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoxor.b.yaml

@@ -37,9 +37,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding);
+  X[xd] = sext(amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding), 8);

data/.data/spec/std/isa/inst/Zabha/amoxor.h.aq.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding), 16);

data/.data/spec/std/isa/inst/Zabha/amoxor.h.aqrl.yaml

@@ -37,13 +37,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding), 16);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoxor.h.rl.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding), 16);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zabha/amoxor.h.yaml

@@ -37,9 +37,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding);
+  X[xd] = sext(amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding), 16);

data/.data/spec/std/isa/inst/Zalrsc/lr.SIZE.AQRL.layout

@@ -119,12 +119,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(<%= current_size[:align_bits] %>, virtual_address)) {
@@ -147,11 +141,7 @@ operation(): |
 
   XReg load_value = load_reserved(<%= current_size[:load_reserved_bits] %>, virtual_address, aq, rl, $encoding);
 <%- if size == "w" -%>
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);
 <%- else -%>
   X[xd] = load_value;
 <%- end -%>

data/.data/spec/std/isa/inst/Zalrsc/lr.d.aq.yaml

@@ -73,12 +73,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(64, virtual_address)) {

data/.data/spec/std/isa/inst/Zalrsc/lr.d.aqrl.yaml

@@ -73,12 +73,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(64, virtual_address)) {

data/.data/spec/std/isa/inst/Zalrsc/lr.d.rl.yaml

@@ -73,12 +73,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(64, virtual_address)) {

data/.data/spec/std/isa/inst/Zalrsc/lr.d.yaml

@@ -73,12 +73,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(64, virtual_address)) {

data/.data/spec/std/isa/inst/Zalrsc/lr.w.aq.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/lr.w.aqrl.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/lr.w.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/sc.SIZE.AQRL.layout

@@ -175,17 +175,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(<%= current_size[:align_bits] %>, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -194,11 +188,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aq.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.rl.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.w.aq.yaml

@@ -134,17 +134,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(32, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -153,11 +147,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }