udb 0.1.15 → 0.1.17

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (692) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +21 -0
  3. data/.data/cfgs/mc100-32-full-example.yaml +7 -0
  4. data/.data/cfgs/profile/RVA20S64.yaml +2 -0
  5. data/.data/cfgs/profile/RVA20U64.yaml +2 -0
  6. data/.data/cfgs/profile/RVA22S64.yaml +2 -0
  7. data/.data/cfgs/profile/RVA22U64.yaml +2 -0
  8. data/.data/cfgs/profile/RVA23S64.yaml +2 -0
  9. data/.data/cfgs/profile/RVA23U64.yaml +2 -0
  10. data/.data/cfgs/profile/RVB23S64.yaml +2 -0
  11. data/.data/cfgs/profile/RVB23U64.yaml +2 -0
  12. data/.data/cfgs/qc_iu.yaml +15 -0
  13. data/.data/cfgs/rv32-riscv-tests.yaml +10 -0
  14. data/.data/cfgs/rv32-vector.yaml +11 -1
  15. data/.data/cfgs/rv64-riscv-tests.yaml +10 -0
  16. data/.data/cfgs/rv64-vector.yaml +12 -2
  17. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml +2 -2
  18. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml +2 -2
  19. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml +2 -2
  20. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml +2 -2
  21. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml +2 -2
  22. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml +2 -2
  23. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml +2 -2
  24. data/.data/spec/schemas/README.adoc +4 -1
  25. data/.data/spec/schemas/csr_schema.json +2 -2
  26. data/.data/spec/std/isa/csr/H/henvcfg.yaml +1 -1
  27. data/.data/spec/std/isa/csr/H/hgeie.yaml +38 -0
  28. data/.data/spec/std/isa/csr/H/hgeip.yaml +33 -0
  29. data/.data/spec/std/isa/csr/H/hideleg.yaml +120 -0
  30. data/.data/spec/std/isa/csr/H/hie.yaml +74 -0
  31. data/.data/spec/std/isa/csr/H/hip.yaml +88 -0
  32. data/.data/spec/std/isa/csr/H/htimedeltah.yaml +1 -1
  33. data/.data/spec/std/isa/csr/H/hvip.yaml +46 -0
  34. data/.data/spec/std/isa/csr/H/vsie.yaml +86 -0
  35. data/.data/spec/std/isa/csr/H/vsip.yaml +98 -0
  36. data/.data/spec/std/isa/csr/H/vsscratch.yaml +29 -0
  37. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +7 -7
  38. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +7 -7
  39. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +7 -7
  40. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +7 -7
  41. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +7 -7
  42. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +7 -7
  43. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +7 -7
  44. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +7 -7
  45. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +7 -7
  46. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +7 -7
  47. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +7 -7
  48. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +7 -7
  49. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +7 -7
  50. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +7 -7
  51. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +7 -7
  52. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +7 -7
  53. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +7 -7
  54. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +7 -7
  55. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +7 -7
  56. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +7 -7
  57. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +7 -7
  58. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +7 -7
  59. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +7 -7
  60. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +7 -7
  61. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +7 -7
  62. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +7 -7
  63. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +7 -7
  64. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +7 -7
  65. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +7 -7
  66. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +7 -7
  67. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +7 -7
  68. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +7 -7
  69. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +7 -7
  70. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +7 -7
  71. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +7 -7
  72. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +7 -7
  73. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +7 -7
  74. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +7 -7
  75. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +7 -7
  76. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +7 -7
  77. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +7 -7
  78. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +7 -7
  79. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +7 -7
  80. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +7 -7
  81. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +7 -7
  82. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +7 -7
  83. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +7 -7
  84. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +7 -7
  85. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +7 -7
  86. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +7 -7
  87. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +7 -7
  88. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +7 -7
  89. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +7 -7
  90. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +7 -7
  91. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +7 -7
  92. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +7 -7
  93. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +7 -7
  94. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +7 -7
  95. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +7 -7
  96. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +7 -7
  97. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +7 -7
  98. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +7 -7
  99. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +7 -7
  100. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +7 -7
  101. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +7 -7
  102. data/.data/spec/std/isa/csr/Smcsrind/mireg.yaml +2 -2
  103. data/.data/spec/std/isa/csr/Smcsrind/mireg2.yaml +2 -2
  104. data/.data/spec/std/isa/csr/Smcsrind/mireg3.yaml +2 -2
  105. data/.data/spec/std/isa/csr/Smcsrind/mireg4.yaml +2 -2
  106. data/.data/spec/std/isa/csr/Smcsrind/mireg5.yaml +2 -2
  107. data/.data/spec/std/isa/csr/Smcsrind/mireg6.yaml +2 -2
  108. data/.data/spec/std/isa/csr/Smcsrind/sireg.yaml +2 -2
  109. data/.data/spec/std/isa/csr/Smcsrind/sireg2.yaml +2 -2
  110. data/.data/spec/std/isa/csr/Smcsrind/sireg3.yaml +2 -2
  111. data/.data/spec/std/isa/csr/Smcsrind/sireg4.yaml +2 -2
  112. data/.data/spec/std/isa/csr/Smcsrind/sireg5.yaml +2 -2
  113. data/.data/spec/std/isa/csr/Smcsrind/sireg6.yaml +2 -2
  114. data/.data/spec/std/isa/csr/Smcsrind/vsireg.yaml +2 -2
  115. data/.data/spec/std/isa/csr/Smcsrind/vsireg2.yaml +2 -2
  116. data/.data/spec/std/isa/csr/Smcsrind/vsireg3.yaml +2 -2
  117. data/.data/spec/std/isa/csr/Smcsrind/vsireg4.yaml +2 -2
  118. data/.data/spec/std/isa/csr/Smcsrind/vsireg5.yaml +2 -2
  119. data/.data/spec/std/isa/csr/Smcsrind/vsireg6.yaml +2 -2
  120. data/.data/spec/std/isa/csr/Smctr/sctrctl.yaml +1 -1
  121. data/.data/spec/std/isa/csr/Smctr/sctrdepth.yaml +43 -0
  122. data/.data/spec/std/isa/csr/Smctr/sctrstatus.yaml +37 -0
  123. data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +4 -2
  124. data/.data/spec/std/isa/csr/Sstc/stimecmp.yaml +42 -0
  125. data/.data/spec/std/isa/csr/Sstc/stimecmph.yaml +43 -0
  126. data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml +45 -0
  127. data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml +46 -0
  128. data/.data/spec/std/isa/csr/V/vcsr.yaml +1 -1
  129. data/.data/spec/std/isa/csr/V/vl.yaml +1 -1
  130. data/.data/spec/std/isa/csr/V/vlenb.yaml +1 -1
  131. data/.data/spec/std/isa/csr/V/vstart.yaml +1 -1
  132. data/.data/spec/std/isa/csr/V/vtype.yaml +20 -1
  133. data/.data/spec/std/isa/csr/V/vxrm.yaml +1 -1
  134. data/.data/spec/std/isa/csr/V/vxsat.yaml +1 -1
  135. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +1 -15
  136. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +29 -267
  137. data/.data/spec/std/isa/csr/hstateen0h.yaml +1 -1
  138. data/.data/spec/std/isa/csr/hstateen1h.yaml +1 -1
  139. data/.data/spec/std/isa/csr/hstateen2h.yaml +1 -1
  140. data/.data/spec/std/isa/csr/hstateen3h.yaml +1 -1
  141. data/.data/spec/std/isa/csr/instreth.yaml +1 -3
  142. data/.data/spec/std/isa/csr/mideleg.yaml +57 -9
  143. data/.data/spec/std/isa/csr/mie.yaml +18 -9
  144. data/.data/spec/std/isa/csr/minstreth.yaml +1 -1
  145. data/.data/spec/std/isa/csr/mip.yaml +21 -10
  146. data/.data/spec/std/isa/csr/misa.yaml +11 -7
  147. data/.data/spec/std/isa/csr/mstatus.yaml +3 -3
  148. data/.data/spec/std/isa/csr/mstatush.yaml +1 -1
  149. data/.data/spec/std/isa/csr/schema.adoc +10 -4
  150. data/.data/spec/std/isa/csr/senvcfg.yaml +7 -13
  151. data/.data/spec/std/isa/csr/sepc.yaml +4 -3
  152. data/.data/spec/std/isa/csr/sip.yaml +1 -1
  153. data/.data/spec/std/isa/csr/sscratch.yaml +3 -2
  154. data/.data/spec/std/isa/csr/sstateen0.yaml +1 -1
  155. data/.data/spec/std/isa/csr/sstateen1.yaml +2 -3
  156. data/.data/spec/std/isa/csr/sstateen2.yaml +2 -3
  157. data/.data/spec/std/isa/csr/sstateen3.yaml +2 -3
  158. data/.data/spec/std/isa/csr/stval.yaml +3 -2
  159. data/.data/spec/std/isa/csr/stvec.yaml +5 -4
  160. data/.data/spec/std/isa/csr/tcontrol.yaml +37 -0
  161. data/.data/spec/std/isa/csr/time.yaml +1 -1
  162. data/.data/spec/std/isa/csr/timeh.yaml +1 -1
  163. data/.data/spec/std/isa/csr/tinfo.yaml +44 -0
  164. data/.data/spec/std/isa/csr/vsepc.yaml +6 -5
  165. data/.data/spec/std/isa/csr/vstvec.yaml +5 -4
  166. data/.data/spec/std/isa/ext/M.yaml +4 -0
  167. data/.data/spec/std/isa/ext/Shgatpa.yaml +1 -0
  168. data/.data/spec/std/isa/ext/Smctr.yaml +1 -1
  169. data/.data/spec/std/isa/ext/Ssctr.yaml +1 -1
  170. data/.data/spec/std/isa/ext/Ssstrict.yaml +2 -2
  171. data/.data/spec/std/isa/ext/Sv32.yaml +2 -2
  172. data/.data/spec/std/isa/ext/Svpbmt.yaml +2 -2
  173. data/.data/spec/std/isa/ext/Zaamo.yaml +1 -1
  174. data/.data/spec/std/isa/ext/Zbc.yaml +4 -0
  175. data/.data/spec/std/isa/ext/Zibi.yaml +29 -0
  176. data/.data/spec/std/isa/ext/Zvfbfa.yaml +24 -0
  177. data/.data/spec/std/isa/ext/Zvfofp4min.yaml +21 -0
  178. data/.data/spec/std/isa/ext/Zvfofp8min.yaml +20 -0
  179. data/.data/spec/std/isa/inst/B/andn.yaml +0 -4
  180. data/.data/spec/std/isa/inst/B/orn.yaml +0 -4
  181. data/.data/spec/std/isa/inst/B/rev8.yaml +0 -4
  182. data/.data/spec/std/isa/inst/B/rol.yaml +0 -4
  183. data/.data/spec/std/isa/inst/B/rolw.yaml +0 -4
  184. data/.data/spec/std/isa/inst/B/ror.yaml +0 -4
  185. data/.data/spec/std/isa/inst/B/rori.yaml +0 -4
  186. data/.data/spec/std/isa/inst/B/roriw.yaml +1 -5
  187. data/.data/spec/std/isa/inst/B/rorw.yaml +1 -5
  188. data/.data/spec/std/isa/inst/B/xnor.yaml +0 -4
  189. data/.data/spec/std/isa/inst/C/c.addi.yaml +2 -2
  190. data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +2 -2
  191. data/.data/spec/std/isa/inst/C/c.addi4spn.yaml +2 -2
  192. data/.data/spec/std/isa/inst/C/c.addiw.yaml +2 -2
  193. data/.data/spec/std/isa/inst/C/c.beqz.yaml +2 -2
  194. data/.data/spec/std/isa/inst/C/c.bnez.yaml +2 -2
  195. data/.data/spec/std/isa/inst/C/c.ebreak.yaml +2 -2
  196. data/.data/spec/std/isa/inst/C/c.j.yaml +2 -2
  197. data/.data/spec/std/isa/inst/C/c.jal.yaml +2 -2
  198. data/.data/spec/std/isa/inst/C/c.jalr.yaml +2 -2
  199. data/.data/spec/std/isa/inst/C/c.jr.yaml +2 -2
  200. data/.data/spec/std/isa/inst/C/c.ld.yaml +2 -2
  201. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +2 -2
  202. data/.data/spec/std/isa/inst/C/c.li.yaml +2 -2
  203. data/.data/spec/std/isa/inst/C/c.lui.yaml +2 -2
  204. data/.data/spec/std/isa/inst/C/c.lw.yaml +2 -2
  205. data/.data/spec/std/isa/inst/C/c.lwsp.yaml +2 -2
  206. data/.data/spec/std/isa/inst/C/c.mv.yaml +2 -2
  207. data/.data/spec/std/isa/inst/C/c.nop.yaml +2 -2
  208. data/.data/spec/std/isa/inst/C/c.sd.yaml +2 -2
  209. data/.data/spec/std/isa/inst/C/c.sdsp.yaml +5 -5
  210. data/.data/spec/std/isa/inst/C/c.sw.yaml +2 -2
  211. data/.data/spec/std/isa/inst/C/c.swsp.yaml +2 -2
  212. data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +3 -0
  213. data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +3 -0
  214. data/.data/spec/std/isa/inst/I/ld.yaml +9 -4
  215. data/.data/spec/std/isa/inst/I/sd.yaml +9 -4
  216. data/.data/spec/std/isa/inst/I/wfi.yaml +1 -1
  217. data/.data/spec/std/isa/inst/M/div.yaml +2 -2
  218. data/.data/spec/std/isa/inst/M/divu.yaml +2 -2
  219. data/.data/spec/std/isa/inst/M/divuw.yaml +2 -2
  220. data/.data/spec/std/isa/inst/M/divw.yaml +2 -2
  221. data/.data/spec/std/isa/inst/M/mul.yaml +1 -7
  222. data/.data/spec/std/isa/inst/M/mulh.yaml +1 -7
  223. data/.data/spec/std/isa/inst/M/mulhsu.yaml +1 -7
  224. data/.data/spec/std/isa/inst/M/mulhu.yaml +1 -7
  225. data/.data/spec/std/isa/inst/M/mulw.yaml +1 -7
  226. data/.data/spec/std/isa/inst/M/rem.yaml +2 -2
  227. data/.data/spec/std/isa/inst/M/remu.yaml +2 -2
  228. data/.data/spec/std/isa/inst/M/remuw.yaml +2 -2
  229. data/.data/spec/std/isa/inst/M/remw.yaml +2 -2
  230. data/.data/spec/std/isa/inst/V/vfadd.vf.yaml +3 -1
  231. data/.data/spec/std/isa/inst/V/vfadd.vv.yaml +3 -1
  232. data/.data/spec/std/isa/inst/V/vfclass.v.yaml +3 -1
  233. data/.data/spec/std/isa/inst/V/vfmacc.vf.yaml +3 -1
  234. data/.data/spec/std/isa/inst/V/vfmacc.vv.yaml +3 -1
  235. data/.data/spec/std/isa/inst/V/vfmadd.vf.yaml +3 -1
  236. data/.data/spec/std/isa/inst/V/vfmadd.vv.yaml +3 -1
  237. data/.data/spec/std/isa/inst/V/vfmax.vf.yaml +3 -1
  238. data/.data/spec/std/isa/inst/V/vfmax.vv.yaml +3 -1
  239. data/.data/spec/std/isa/inst/V/vfmerge.vfm.yaml +3 -1
  240. data/.data/spec/std/isa/inst/V/vfmin.vf.yaml +3 -1
  241. data/.data/spec/std/isa/inst/V/vfmin.vv.yaml +3 -1
  242. data/.data/spec/std/isa/inst/V/vfmsac.vf.yaml +3 -1
  243. data/.data/spec/std/isa/inst/V/vfmsac.vv.yaml +3 -1
  244. data/.data/spec/std/isa/inst/V/vfmsub.vf.yaml +3 -1
  245. data/.data/spec/std/isa/inst/V/vfmsub.vv.yaml +3 -1
  246. data/.data/spec/std/isa/inst/V/vfmul.vf.yaml +3 -1
  247. data/.data/spec/std/isa/inst/V/vfmul.vv.yaml +3 -1
  248. data/.data/spec/std/isa/inst/V/vfmv.f.s.yaml +3 -1
  249. data/.data/spec/std/isa/inst/V/vfmv.s.f.yaml +3 -1
  250. data/.data/spec/std/isa/inst/V/vfmv.v.f.yaml +3 -1
  251. data/.data/spec/std/isa/inst/V/vfncvt.f.f.w.yaml +3 -1
  252. data/.data/spec/std/isa/inst/V/vfncvt.rod.f.f.w.yaml +3 -1
  253. data/.data/spec/std/isa/inst/V/vfncvt.rtz.x.f.w.yaml +3 -1
  254. data/.data/spec/std/isa/inst/V/vfncvt.rtz.xu.f.w.yaml +3 -1
  255. data/.data/spec/std/isa/inst/V/vfncvt.x.f.w.yaml +3 -1
  256. data/.data/spec/std/isa/inst/V/vfncvt.xu.f.w.yaml +3 -1
  257. data/.data/spec/std/isa/inst/V/vfnmacc.vf.yaml +3 -1
  258. data/.data/spec/std/isa/inst/V/vfnmacc.vv.yaml +3 -1
  259. data/.data/spec/std/isa/inst/V/vfnmadd.vf.yaml +3 -1
  260. data/.data/spec/std/isa/inst/V/vfnmadd.vv.yaml +3 -1
  261. data/.data/spec/std/isa/inst/V/vfnmsac.vf.yaml +3 -1
  262. data/.data/spec/std/isa/inst/V/vfnmsac.vv.yaml +3 -1
  263. data/.data/spec/std/isa/inst/V/vfnmsub.vf.yaml +3 -1
  264. data/.data/spec/std/isa/inst/V/vfnmsub.vv.yaml +3 -1
  265. data/.data/spec/std/isa/inst/V/vfrec7.v.yaml +3 -1
  266. data/.data/spec/std/isa/inst/V/vfrsqrt7.v.yaml +3 -1
  267. data/.data/spec/std/isa/inst/V/vfrsub.vf.yaml +3 -1
  268. data/.data/spec/std/isa/inst/V/vfsgnj.vf.yaml +3 -1
  269. data/.data/spec/std/isa/inst/V/vfsgnj.vv.yaml +3 -1
  270. data/.data/spec/std/isa/inst/V/vfsgnjn.vf.yaml +3 -1
  271. data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -1
  272. data/.data/spec/std/isa/inst/V/vfsgnjx.vf.yaml +3 -1
  273. data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -1
  274. data/.data/spec/std/isa/inst/V/vfslide1down.vf.yaml +3 -1
  275. data/.data/spec/std/isa/inst/V/vfslide1up.vf.yaml +3 -1
  276. data/.data/spec/std/isa/inst/V/vfsub.vf.yaml +3 -1
  277. data/.data/spec/std/isa/inst/V/vfsub.vv.yaml +3 -1
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  529. data/.data/spec/std/isa/inst/Zcf/c.flw.yaml +3 -3
  530. data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +4 -4
  531. data/.data/spec/std/isa/inst/Zcf/c.fsw.yaml +3 -3
  532. data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +4 -4
  533. data/.data/spec/std/isa/inst/Zcmp/cm.mva01s.yaml +2 -2
  534. data/.data/spec/std/isa/inst/Zcmp/cm.mvsa01.yaml +2 -2
  535. data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +2 -2
  536. data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +2 -2
  537. data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +2 -2
  538. data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -2
  539. data/.data/spec/std/isa/inst/{Q → Zfa}/fltq.q.yaml +2 -2
  540. data/.data/spec/std/isa/inst/Zibi/beqi.yaml +45 -0
  541. data/.data/spec/std/isa/inst/Zibi/bnei.yaml +45 -0
  542. data/.data/spec/std/isa/inst/Zicbom/cbo.clean.yaml +2 -2
  543. data/.data/spec/std/isa/inst/Zicbom/cbo.flush.yaml +2 -2
  544. data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml +3 -3
  545. data/.data/spec/std/isa/inst/Zicboz/cbo.zero.yaml +2 -2
  546. data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.d.yaml +1 -1
  547. data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.w.yaml +1 -1
  548. data/.data/spec/std/isa/inst/Zicfiss/sspopchk.yaml +63 -0
  549. data/.data/spec/std/isa/inst/Zicfiss/sspush.yaml +63 -0
  550. data/.data/spec/std/isa/inst/Zimop/mop.r.28.yaml +1 -2
  551. data/.data/spec/std/isa/inst/Zimop/mop.r.N.layout +1 -2
  552. data/.data/spec/std/isa/inst/Zimop/mop.rr.7.yaml +1 -2
  553. data/.data/spec/std/isa/inst/Zimop/mop.rr.N.layout +1 -2
  554. data/.data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +3 -1
  555. data/.data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +3 -1
  556. data/.data/spec/std/isa/inst/Zvfofp4min/vfext.vf2.yaml +35 -0
  557. data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.f.f.q.yaml +31 -0
  558. data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.sat.f.f.q.yaml +32 -0
  559. data/.data/spec/std/isa/inst/Zvfofp8min/vfncvtbf16.sat.f.f.w.yaml +32 -0
  560. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vv.yaml +1 -1
  561. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vx.yaml +1 -1
  562. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vbrev8.v.yaml +1 -1
  563. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrev8.v.yaml +1 -1
  564. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vv.yaml +1 -1
  565. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vx.yaml +1 -1
  566. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vi.yaml +1 -1
  567. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vv.yaml +1 -1
  568. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vx.yaml +1 -1
  569. data/.data/spec/std/isa/isa/builtin_functions.idl +3 -1
  570. data/.data/spec/std/isa/isa/globals.isa +1 -1
  571. data/.data/spec/std/isa/isa/util.idl +4 -3
  572. data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +3 -2
  573. data/.data/spec/std/isa/param/HCONTEXT_AVAILABLE.yaml +1 -1
  574. data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +2 -5
  575. data/.data/spec/std/isa/param/HPM_COUNTER10_WIDTH.yaml +29 -0
  576. data/.data/spec/std/isa/param/HPM_COUNTER11_WIDTH.yaml +29 -0
  577. data/.data/spec/std/isa/param/HPM_COUNTER12_WIDTH.yaml +29 -0
  578. data/.data/spec/std/isa/param/HPM_COUNTER13_WIDTH.yaml +29 -0
  579. data/.data/spec/std/isa/param/HPM_COUNTER14_WIDTH.yaml +29 -0
  580. data/.data/spec/std/isa/param/HPM_COUNTER15_WIDTH.yaml +29 -0
  581. data/.data/spec/std/isa/param/HPM_COUNTER16_WIDTH.yaml +29 -0
  582. data/.data/spec/std/isa/param/HPM_COUNTER17_WIDTH.yaml +29 -0
  583. data/.data/spec/std/isa/param/HPM_COUNTER18_WIDTH.yaml +29 -0
  584. data/.data/spec/std/isa/param/HPM_COUNTER19_WIDTH.yaml +29 -0
  585. data/.data/spec/std/isa/param/HPM_COUNTER20_WIDTH.yaml +29 -0
  586. data/.data/spec/std/isa/param/HPM_COUNTER21_WIDTH.yaml +29 -0
  587. data/.data/spec/std/isa/param/HPM_COUNTER22_WIDTH.yaml +29 -0
  588. data/.data/spec/std/isa/param/HPM_COUNTER23_WIDTH.yaml +29 -0
  589. data/.data/spec/std/isa/param/HPM_COUNTER24_WIDTH.yaml +29 -0
  590. data/.data/spec/std/isa/param/HPM_COUNTER25_WIDTH.yaml +29 -0
  591. data/.data/spec/std/isa/param/HPM_COUNTER26_WIDTH.yaml +29 -0
  592. data/.data/spec/std/isa/param/HPM_COUNTER27_WIDTH.yaml +29 -0
  593. data/.data/spec/std/isa/param/HPM_COUNTER28_WIDTH.yaml +29 -0
  594. data/.data/spec/std/isa/param/HPM_COUNTER29_WIDTH.yaml +29 -0
  595. data/.data/spec/std/isa/param/HPM_COUNTER30_WIDTH.yaml +29 -0
  596. data/.data/spec/std/isa/param/HPM_COUNTER31_WIDTH.yaml +29 -0
  597. data/.data/spec/std/isa/param/HPM_COUNTER3_WIDTH.yaml +29 -0
  598. data/.data/spec/std/isa/param/HPM_COUNTER4_WIDTH.yaml +29 -0
  599. data/.data/spec/std/isa/param/HPM_COUNTER5_WIDTH.yaml +29 -0
  600. data/.data/spec/std/isa/param/HPM_COUNTER6_WIDTH.yaml +29 -0
  601. data/.data/spec/std/isa/param/HPM_COUNTER7_WIDTH.yaml +29 -0
  602. data/.data/spec/std/isa/param/HPM_COUNTER8_WIDTH.yaml +29 -0
  603. data/.data/spec/std/isa/param/HPM_COUNTER9_WIDTH.yaml +29 -0
  604. data/.data/spec/std/isa/param/HPM_COUNTERN_WIDTH.layout +27 -0
  605. data/.data/spec/std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml +2 -4
  606. data/.data/spec/std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml +2 -4
  607. data/.data/spec/std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml +1 -1
  608. data/.data/spec/std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml +1 -1
  609. data/.data/spec/std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml +4 -4
  610. data/.data/spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml +1 -1
  611. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +2 -5
  612. data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +28 -0
  613. data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +28 -0
  614. data/.data/spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml +8 -15
  615. data/.data/spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml +7 -15
  616. data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +28 -0
  617. data/.data/spec/std/isa/param/MTVAL_WIDTH.yaml +17 -5
  618. data/.data/spec/std/isa/param/MUTABLE_MISA_A.yaml +1 -1
  619. data/.data/spec/std/isa/param/MUTABLE_MISA_B.yaml +1 -1
  620. data/.data/spec/std/isa/param/MUTABLE_MISA_C.yaml +1 -1
  621. data/.data/spec/std/isa/param/MUTABLE_MISA_D.yaml +1 -1
  622. data/.data/spec/std/isa/param/MUTABLE_MISA_F.yaml +1 -1
  623. data/.data/spec/std/isa/param/MUTABLE_MISA_H.yaml +1 -1
  624. data/.data/spec/std/isa/param/MUTABLE_MISA_M.yaml +1 -1
  625. data/.data/spec/std/isa/param/MUTABLE_MISA_Q.yaml +1 -1
  626. data/.data/spec/std/isa/param/MUTABLE_MISA_S.yaml +1 -1
  627. data/.data/spec/std/isa/param/MUTABLE_MISA_U.yaml +1 -1
  628. data/.data/spec/std/isa/param/MUTABLE_MISA_V.yaml +1 -1
  629. data/.data/spec/std/isa/param/{PMLEN.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml} +6 -9
  630. data/.data/spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml +1 -1
  631. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +1 -1
  632. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  633. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  634. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  635. data/.data/spec/std/isa/param/SCOUNTENABLE_EN.yaml +2 -6
  636. data/.data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml +27 -0
  637. data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +28 -0
  638. data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +28 -0
  639. data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +33 -0
  640. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +81 -0
  641. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml +40 -0
  642. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml +42 -0
  643. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml +42 -0
  644. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml +1 -1
  645. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml +1 -1
  646. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml +1 -1
  647. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -1
  648. data/.data/spec/std/isa/param/VSEI_INTR_IMPL.yaml +28 -0
  649. data/.data/spec/std/isa/param/VSSI_INTR_IMPL.yaml +28 -0
  650. data/.data/spec/std/isa/param/VSTI_INTR_IMPL.yaml +33 -0
  651. data/.data/spec/std/isa/param/WFI_FINITE.yaml +20 -0
  652. data/.data/spec/std/isa/param/WFI_U_MODE.yaml +20 -0
  653. data/lib/udb/Z3_VERSION +1 -1
  654. data/lib/udb/config.rb +1 -1
  655. data/lib/udb/log.rb +16 -0
  656. data/lib/udb/obj/csr.rb +38 -45
  657. data/lib/udb/obj/database_obj.rb +1 -1
  658. data/lib/udb/obj/exception_code.rb +3 -3
  659. data/lib/udb/version.rb +1 -1
  660. metadata +122 -52
  661. data/.data/spec/std/isa/inst/Zicfiss/sspopchk.x1.yaml +0 -25
  662. data/.data/spec/std/isa/inst/Zicfiss/sspopchk.x5.yaml +0 -25
  663. data/.data/spec/std/isa/inst/Zicfiss/sspush.x1.yaml +0 -25
  664. data/.data/spec/std/isa/inst/Zicfiss/sspush.x5.yaml +0 -25
  665. /data/.data/spec/std/isa/inst/{Smdbltrp → Smctr}/sctrclr.yaml +0 -0
  666. /data/.data/spec/std/isa/inst/{D → Zfa}/fcvtmod.w.d.yaml +0 -0
  667. /data/.data/spec/std/isa/inst/{D → Zfa}/fleq.d.yaml +0 -0
  668. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fleq.h.yaml +0 -0
  669. /data/.data/spec/std/isa/inst/{Q → Zfa}/fleq.q.yaml +0 -0
  670. /data/.data/spec/std/isa/inst/{F → Zfa}/fleq.s.yaml +0 -0
  671. /data/.data/spec/std/isa/inst/{D → Zfa}/fli.d.yaml +0 -0
  672. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fli.h.yaml +0 -0
  673. /data/.data/spec/std/isa/inst/{Q → Zfa}/fli.q.yaml +0 -0
  674. /data/.data/spec/std/isa/inst/{D → Zfa}/fltq.d.yaml +0 -0
  675. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fltq.h.yaml +0 -0
  676. /data/.data/spec/std/isa/inst/{F → Zfa}/fltq.s.yaml +0 -0
  677. /data/.data/spec/std/isa/inst/{D → Zfa}/fmaxm.d.yaml +0 -0
  678. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fmaxm.h.yaml +0 -0
  679. /data/.data/spec/std/isa/inst/{Q → Zfa}/fmaxm.q.yaml +0 -0
  680. /data/.data/spec/std/isa/inst/{D → Zfa}/fminm.d.yaml +0 -0
  681. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fminm.h.yaml +0 -0
  682. /data/.data/spec/std/isa/inst/{Q → Zfa}/fminm.q.yaml +0 -0
  683. /data/.data/spec/std/isa/inst/{D → Zfa}/fmvh.x.d.yaml +0 -0
  684. /data/.data/spec/std/isa/inst/{Q → Zfa}/fmvh.x.q.yaml +0 -0
  685. /data/.data/spec/std/isa/inst/{D → Zfa}/fmvp.d.x.yaml +0 -0
  686. /data/.data/spec/std/isa/inst/{Q → Zfa}/fmvp.q.x.yaml +0 -0
  687. /data/.data/spec/std/isa/inst/{D → Zfa}/fround.d.yaml +0 -0
  688. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fround.h.yaml +0 -0
  689. /data/.data/spec/std/isa/inst/{Q → Zfa}/fround.q.yaml +0 -0
  690. /data/.data/spec/std/isa/inst/{D → Zfa}/froundnx.d.yaml +0 -0
  691. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/froundnx.h.yaml +0 -0
  692. /data/.data/spec/std/isa/inst/{Q → Zfa}/froundnx.q.yaml +0 -0
@@ -11,7 +11,9 @@ description: |
11
11
  Moves scalar floating-point value from register fs1 to all elements of vector register vd, using vector mask vm. This operation broadcasts a scalar to a vector.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1
16
18
  encoding:
17
19
  match: 010000100000-----101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Moves floating-point element from scalar register fs1 to vector register vd, using vector mask vm. This operation creates a vector with a single floating-point value.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1
16
18
  encoding:
17
19
  match: 010111100000-----101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------10100001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider floating-point format using round-to-odd mode and stores results in vector register vd, using vector mask vm.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------10101001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider integer format using round-toward-zero mode and stores results in vector register vd, using vector mask vm.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------10111001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider unsigned integer format using round-toward-zero mode and stores results in vector register vd, using vector mask vm.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------10110001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider integer format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 rounding rules.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------10001001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider unsigned integer format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 rounding rules.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------10000001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 101101-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 101101-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 101001-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 101001-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 101111-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 101111-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 101011-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 101011-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010011------00101001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010011------00100001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 100111-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 001000-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 001000-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 001001-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 001001-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 001010-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 001010-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 001111-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 001110-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Performs floating-point subtraction on elements from vs2 and scalar from rs1, according to mask vm, and stores results in vd. Element width is determined by SEW setting. Follows IEEE-754 floating-point standards. Supports vector masking and follows vector tail policy.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 000010-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Performs floating-point subtraction on elements from vs2 and vs1, according to mask vm, and stores results in vd. Element width is determined by SEW setting. Follows IEEE-754 floating-point standards. Supports vector masking and follows vector tail policy.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 000010-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Performs floating-point addition on elements from vector register vs2 and floating-point scalar register fs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 110000-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Performs floating-point addition on elements from vector registers vs2 and vs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 110000-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 110100-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 110100-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts floating-point elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------01100001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts signed integer elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------01011001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Converts unsigned integer elements from vector register vs2 to a wider floating-point format and stores results in vector register vd, using vector mask vm. The conversion follows IEEE 754 standards.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vm
16
18
  encoding:
17
19
  match: 010010------01010001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 111100-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 111100-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 111110-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 111110-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 111000-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 111000-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 111101-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 111101-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, fs1, vs2, vm
16
18
  encoding:
17
19
  match: 111111-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs1, vs2, vm
16
18
  encoding:
17
19
  match: 111111-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Performs floating-point subtraction on elements from vector register vs2 and floating-point scalar register fs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 110010-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  Performs floating-point subtraction on elements from vector registers vs2 and vs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 110010-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 110110-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 110110-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 011000-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, vs1, vm
16
18
  encoding:
17
19
  match: 011000-----------001-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 011111-----------101-----1010111
@@ -11,7 +11,9 @@ description: |
11
11
  No description available.
12
12
  definedBy:
13
13
  extension:
14
- name: Zvl32b
14
+ anyOf:
15
+ - name: Zvl32b
16
+ - name: Zvfbfa
15
17
  assembly: vd, vs2, fs1, vm
16
18
  encoding:
17
19
  match: 011101-----------101-----1010111