udb 0.1.15 → 0.1.17

data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml

@@ -31,12 +31,8 @@ access:
   vu: always
 operation(): |2
 
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[creg2reg(xd)] = X[creg2reg(xd)][31:0];

data/.data/spec/std/isa/inst/Zcd/c.fld.yaml

@@ -32,10 +32,10 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  F[fd] = sext(read_memory(64, virtual_address, $encoding), 64);
+  F[creg2reg(fd)] = sext(read_memory(64, virtual_address, $encoding), 64);

data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml

@@ -30,11 +30,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
-  if (implemented?(ExtensionName::D) && (CSR[misa].D == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::D) && MISA_CSR_IMPLEMENTED && (CSR[misa].D == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/Zcd/c.fsd.yaml

@@ -32,10 +32,10 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  write_memory(64, virtual_address, X[creg2reg(fs2)], $encoding);
+  write_memory(64, virtual_address, F[creg2reg(fs2)][63:0], $encoding);

data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml

@@ -30,11 +30,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
-  if (implemented?(ExtensionName::D) && (CSR[misa].D == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::D) && MISA_CSR_IMPLEMENTED && (CSR[misa].D == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/Zcf/c.flw.yaml

@@ -32,10 +32,10 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  X[creg2reg(fd)] = sext(read_memory(32, virtual_address, $encoding), 32);
+  F[creg2reg(fd)] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml

@@ -30,11 +30,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
-  if (implemented?(ExtensionName::F) && (CSR[misa].F == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::F) && MISA_CSR_IMPLEMENTED && (CSR[misa].F == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/Zcf/c.fsw.yaml

@@ -32,10 +32,10 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  write_memory(32, virtual_address, X[creg2reg(fs2)][31:0], $encoding);
+  write_memory(32, virtual_address, F[creg2reg(fs2)][31:0], $encoding);

data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml

@@ -30,11 +30,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
-  if (implemented?(ExtensionName::F) && (CSR[misa].F == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::F) && MISA_CSR_IMPLEMENTED && (CSR[misa].F == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/Zcmp/cm.mva01s.yaml

@@ -27,8 +27,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]};
   XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]};

data/.data/spec/std/isa/inst/Zcmp/cm.mvsa01.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]};
   XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]};

data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg size = xlen() / 8;

data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg size = xlen() / 8;

data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg size = xlen() / 8;

data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg size = xlen() / 8;

data/.data/spec/std/isa/inst/{Q → Zfa}/fltq.q.yaml

@@ -18,7 +18,7 @@ definedBy:
     allOf:
       - name: Q
       - name: Zfa
-assembly: fd, fs1, fs2
+assembly: xd, fs1, fs2
 encoding:
   match: 1010011----------101-----1010011
   variables:
@@ -26,7 +26,7 @@ encoding:
       location: 24-20
     - name: fs1
       location: 19-15
-    - name: fd
+    - name: xd
       location: 11-7
 access:
   s: always

data/.data/spec/std/isa/inst/Zibi/beqi.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: beqi
+long_name: Branch if equal immediate
+description: |
+  Branch to PC + offset if the value in register xs1 is equal to the XLEN-bit
+  comparison constant decoded from cimm.
+
+  The cimm field is not sign-extended: cimm == 0 encodes the value -1, and
+  cimm values 1 through 31 encode the corresponding positive integer values.
+
+  Raise a `MisalignedAddress` exception if the branch is taken and PC + offset is
+  misaligned.
+definedBy:
+  extension:
+    name: Zibi
+assembly: xs1, cimm, offset
+encoding:
+  match: "-----------------010-----1100011"
+  variables:
+    - name: offset
+      location: 31|7|30-25|11-8
+      left_shift: 1
+      sign_extend: true
+    - name: cimm
+      location: 24-20
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg lhs = X[xs1];
+  XReg rhs = (cimm == 0) ? {MXLEN{1'b1}} : cimm;
+
+  if (lhs == rhs) {
+    jump_halfword($pc + $signed(offset));
+  }

data/.data/spec/std/isa/inst/Zibi/bnei.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: bnei
+long_name: Branch if not equal immediate
+description: |
+  Branch to PC + offset if the value in register xs1 is not equal to the XLEN-bit
+  comparison constant decoded from cimm.
+
+  The cimm field is not sign-extended: cimm == 0 encodes the value -1, and
+  cimm values 1 through 31 encode the corresponding positive integer values.
+
+  Raise a `MisalignedAddress` exception if the branch is taken and PC + offset is
+  misaligned.
+definedBy:
+  extension:
+    name: Zibi
+assembly: xs1, cimm, offset
+encoding:
+  match: "-----------------011-----1100011"
+  variables:
+    - name: offset
+      location: 31|7|30-25|11-8
+      left_shift: 1
+      sign_extend: true
+    - name: cimm
+      location: 24-20
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg lhs = X[xs1];
+  XReg rhs = (cimm == 0) ? {MXLEN{1'b1}} : cimm;
+
+  if (lhs != rhs) {
+    jump_halfword($pc + $signed(offset));
+  }

data/.data/spec/std/isa/inst/Zicbom/cbo.clean.yaml

@@ -18,7 +18,7 @@ description: |
 
   `cbo.clean` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.clean` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -31,7 +31,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicbom/cbo.flush.yaml

@@ -12,7 +12,7 @@ description: |
 
   `cbo.flush` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.flush` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -25,7 +25,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml

@@ -51,8 +51,8 @@ description: |
 
   `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
-  Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.inval` has UNSPECIFIED behavior.
   <%- end -%>
 
   Invalidate operations are treated as stores for page and access permissions. If permission checks fail,
@@ -64,7 +64,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicboz/cbo.zero.yaml

@@ -14,7 +14,7 @@ description: |
 
   `cbo.zero` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -27,7 +27,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.d.yaml

@@ -12,7 +12,7 @@ description: |
 definedBy:
   extension:
     name: Zicfiss
-assembly: xd, xs2, xs1
+assembly: xd, xs2, (xs1)
 encoding:
   match: 01001------------011-----0101111
   variables:

data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.w.yaml

@@ -12,7 +12,7 @@ description: |
 definedBy:
   extension:
     name: Zicfiss
-assembly: xd, xs2, xs1
+assembly: xd, xs2, (xs1)
 encoding:
   match: 01001------------010-----0101111
   variables:

data/.data/spec/std/isa/inst/Zicfiss/sspopchk.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspopchk
+long_name: Shadow Stack Pop and Check
+description: |
+  SSPOPCHK pops a value from the shadow stack and checks it against link
+  register `xs1`. The encoding restricts `xs1` to `x1` or `x5`.
+
+  This instruction uses the `mop.r.28` codepoint provided by Zimop.
+definedBy:
+  extension:
+    name: Zicfiss
+assembly: xs1
+encoding:
+  match: "110011011100-----100000001110011"
+  variables:
+    - name: xs1
+      location: 19-15
+      not:
+        [
+          0,
+          2,
+          3,
+          4,
+          6,
+          7,
+          8,
+          9,
+          10,
+          11,
+          12,
+          13,
+          14,
+          15,
+          16,
+          17,
+          18,
+          19,
+          20,
+          21,
+          22,
+          23,
+          24,
+          25,
+          26,
+          27,
+          28,
+          29,
+          30,
+          31,
+        ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicfiss/sspush.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspush
+long_name: Shadow Stack Push
+description: |
+  SSPUSH pushes the value of link register `xs2` to the shadow stack.
+  The encoding restricts `xs2` to `x1` or `x5`.
+
+  This instruction uses the `mop.rr.7` codepoint provided by Zimop.
+definedBy:
+  extension:
+    name: Zicfiss
+assembly: xs2
+encoding:
+  match: "1100111-----00000100000001110011"
+  variables:
+    - name: xs2
+      location: 24-20
+      not:
+        [
+          0,
+          2,
+          3,
+          4,
+          6,
+          7,
+          8,
+          9,
+          10,
+          11,
+          12,
+          13,
+          14,
+          15,
+          16,
+          17,
+          18,
+          19,
+          20,
+          21,
+          22,
+          23,
+          24,
+          25,
+          26,
+          27,
+          28,
+          29,
+          30,
+          31,
+        ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zimop/mop.r.28.yaml

@@ -33,8 +33,7 @@ access:
   vu: always
 data_independent_timing: false
 hints:
-  - { $ref: inst/Zicfiss/sspopchk.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspopchk.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspopchk.yaml# }
   - { $ref: inst/Zicfiss/ssrdp.yaml# }
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zimop/mop.r.N.layout

@@ -50,8 +50,7 @@ access:
 data_independent_timing: false
 <% if n == 28 -%>
 hints:
-  - { $ref: inst/Zicfiss/sspopchk.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspopchk.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspopchk.yaml# }
   - { $ref: inst/Zicfiss/ssrdp.yaml# }
 <% end -%>
 operation(): |

data/.data/spec/std/isa/inst/Zimop/mop.rr.7.yaml

@@ -36,7 +36,6 @@ access:
   vu: always
 data_independent_timing: false
 hints:
-  - { $ref: inst/Zicfiss/sspush.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspush.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspush.yaml# }
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zimop/mop.rr.N.layout

@@ -51,8 +51,7 @@ access:
 data_independent_timing: false
 <% if n == 7 -%>
 hints:
-  - { $ref: inst/Zicfiss/sspush.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspush.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspush.yaml# }
 <% end -%>
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml

@@ -11,7 +11,9 @@ description: |
   Converts each single-precision floating-point element in vector register vs2 to BFloat16 format, storing results in vector register vd according to mask vm. This is a narrowing conversion that compresses 32-bit single-precision values to 16-bit BFloat16 values.
 definedBy:
   extension:
-    name: Zvfbfmin
+    anyOf:
+      - name: Zvfbfmin
+      - name: Zvfofp8min
 assembly: vd, vs2, vm
 encoding:
   match: 010010------11101001-----1010111

data/.data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml

@@ -11,7 +11,9 @@ description: |
   Converts each BFloat16 element in vector register vs2 to single-precision floating-point format, storing results in vector register vd according to mask vm. This is a widening conversion that expands 16-bit BFloat16 values to 32-bit single-precision values.
 definedBy:
   extension:
-    name: Zvfbfmin
+    anyOf:
+      - name: Zvfbfmin
+      - name: Zvfofp8min
 assembly: vd, vs2, vm
 encoding:
   match: 010010------01101001-----1010111

data/.data/spec/std/isa/inst/Zvfofp4min/vfext.vf2.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfext.vf2
+long_name: Vector OFP4 to OFP8 widening conversion
+description: |
+  Converts a vector of OFP4 E2M1 values in vector register vs2 (EEW=4,
+  EMUL=LMUL/2) to a vector of OFP8 E4M3 values in vector register vd
+  (EEW=8, EMUL=LMUL), according to mask vm. Defined only for SEW=8,
+  altfmt=0, and LMUL >= 1/4. No rounding occurs, and no floating-point
+  exception flags are set. This instruction does not access the fcsr
+  and is not considered a floating-point instruction for the purposes
+  of the floating-point context status (FS) setting.
+definedBy:
+  extension:
+    name: Zvfofp4min
+assembly: vd, vs2, vm
+encoding:
+  match: "010010------10110010-----1010111"
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |