udb 0.1.13 → 0.1.15

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (429) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +20 -24
  3. data/.data/cfgs/mc100-32-full-example.yaml +2 -2
  4. data/.data/cfgs/qc_iu.yaml +7 -3
  5. data/.data/cfgs/rv32-riscv-tests.yaml +8 -5
  6. data/.data/cfgs/rv32-vector.yaml +8 -5
  7. data/.data/cfgs/rv64-riscv-tests.yaml +8 -5
  8. data/.data/cfgs/rv64-vector.yaml +8 -5
  9. data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +107 -36
  10. data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +52 -69
  11. data/.data/spec/custom/isa/qc_iu/isa/globals.isa +27 -5
  12. data/.data/spec/schemas/README.adoc +3 -0
  13. data/.data/spec/schemas/config_schema.json +1 -1
  14. data/.data/spec/schemas/mmr_schema.json +3 -3
  15. data/.data/spec/schemas/schema_defs.json +8 -3
  16. data/.data/spec/std/isa/csr/H/hcounteren.layout +3 -3
  17. data/.data/spec/std/isa/csr/H/hcounteren.yaml +31 -31
  18. data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
  19. data/.data/spec/std/isa/csr/H/htinst.yaml +3 -3
  20. data/.data/spec/std/isa/csr/H/htval.yaml +3 -3
  21. data/.data/spec/std/isa/csr/H/mtinst.yaml +1 -1
  22. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
  23. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
  24. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
  25. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
  26. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
  27. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
  28. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
  29. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
  30. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
  31. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
  32. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
  33. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
  34. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
  35. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
  36. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
  37. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
  38. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
  39. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
  40. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
  41. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
  42. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
  43. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
  44. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
  45. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
  46. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
  47. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
  48. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
  49. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
  50. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
  51. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
  52. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
  53. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
  54. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
  55. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
  56. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
  57. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
  58. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
  59. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
  60. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
  61. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
  62. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
  63. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
  64. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
  65. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
  66. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
  67. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
  68. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
  69. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
  70. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
  71. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
  72. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
  73. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
  74. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
  75. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
  76. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
  77. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
  78. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
  79. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
  80. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
  81. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
  82. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
  83. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
  84. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
  85. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
  86. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
  87. data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +120 -144
  88. data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +60 -72
  89. data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +120 -144
  90. data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +60 -72
  91. data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +120 -144
  92. data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +60 -72
  93. data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +120 -144
  94. data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +60 -72
  95. data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +120 -144
  96. data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +60 -72
  97. data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +120 -144
  98. data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +60 -72
  99. data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +120 -144
  100. data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +60 -72
  101. data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +120 -144
  102. data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +60 -72
  103. data/.data/spec/std/isa/csr/I/pmpcfgN.layout +15 -18
  104. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +1 -1
  105. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +1 -1
  106. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +1 -1
  107. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +1 -1
  108. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +1 -1
  109. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +29 -29
  110. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -4
  111. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +1 -1
  112. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -4
  113. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +1 -1
  114. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -4
  115. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +1 -1
  116. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -4
  117. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +1 -1
  118. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -4
  119. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +1 -1
  120. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -4
  121. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +1 -1
  122. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -4
  123. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +1 -1
  124. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -4
  125. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +1 -1
  126. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -4
  127. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +1 -1
  128. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -4
  129. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +1 -1
  130. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -4
  131. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +1 -1
  132. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -4
  133. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +1 -1
  134. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -4
  135. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +1 -1
  136. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -4
  137. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +1 -1
  138. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -4
  139. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +1 -1
  140. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -4
  141. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +1 -1
  142. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -4
  143. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +1 -1
  144. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -4
  145. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +1 -1
  146. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -4
  147. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +1 -1
  148. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -4
  149. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +1 -1
  150. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -4
  151. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -4
  152. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +1 -1
  153. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -4
  154. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +1 -1
  155. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +1 -1
  156. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -4
  157. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +1 -1
  158. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -4
  159. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +1 -1
  160. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -4
  161. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +1 -1
  162. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -4
  163. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +1 -1
  164. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -4
  165. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +1 -1
  166. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -4
  167. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +1 -1
  168. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -4
  169. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +1 -1
  170. data/.data/spec/std/isa/csr/hstatus.yaml +1 -1
  171. data/.data/spec/std/isa/csr/jvt.yaml +1 -0
  172. data/.data/spec/std/isa/csr/mcycle.yaml +6 -6
  173. data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
  174. data/.data/spec/std/isa/csr/minstret.yaml +3 -3
  175. data/.data/spec/std/isa/csr/minstreth.yaml +1 -1
  176. data/.data/spec/std/isa/csr/mstatus.yaml +21 -25
  177. data/.data/spec/std/isa/csr/mtvec.yaml +16 -57
  178. data/.data/spec/std/isa/csr/senvcfg.yaml +26 -0
  179. data/.data/spec/std/isa/csr/sie.yaml +30 -4
  180. data/.data/spec/std/isa/csr/sip.yaml +16 -2
  181. data/.data/spec/std/isa/csr/stvec.yaml +11 -12
  182. data/.data/spec/std/isa/csr/vstval.yaml +1 -1
  183. data/.data/spec/std/isa/csr/vstvec.yaml +14 -15
  184. data/.data/spec/std/isa/ext/Q.yaml +1 -1
  185. data/.data/spec/std/isa/ext/Shlcofideleg.yaml +24 -0
  186. data/.data/spec/std/isa/ext/Shvstvecd.yaml +2 -2
  187. data/.data/spec/std/isa/ext/Sspm.yaml +5 -0
  188. data/.data/spec/std/isa/ext/Sstvecd.yaml +2 -2
  189. data/.data/spec/std/isa/ext/Sstvecv.yaml +2 -2
  190. data/.data/spec/std/isa/ext/Supm.yaml +17 -0
  191. data/.data/spec/std/isa/ext/Zcb.yaml +3 -0
  192. data/.data/spec/std/isa/ext/Zfbfmin.yaml +3 -5
  193. data/.data/spec/std/isa/ext/Ziccid.yaml +29 -0
  194. data/.data/spec/std/isa/ext/Zicfilp.yaml +5 -1
  195. data/.data/spec/std/isa/ext/Zicfiss.yaml +20 -1
  196. data/.data/spec/std/isa/ext/Zihpm.yaml +3 -0
  197. data/.data/spec/std/isa/ext/Zilx.yaml +58 -0
  198. data/.data/spec/std/isa/ext/Zkt.yaml +33 -1
  199. data/.data/spec/std/isa/ext/Zvabd.yaml +21 -0
  200. data/.data/spec/std/isa/ext/Zvbc.yaml +3 -0
  201. data/.data/spec/std/isa/ext/Zvkb.yaml +3 -0
  202. data/.data/spec/std/isa/ext/Zvkg.yaml +3 -0
  203. data/.data/spec/std/isa/ext/Zvkned.yaml +3 -0
  204. data/.data/spec/std/isa/ext/Zvknha.yaml +3 -0
  205. data/.data/spec/std/isa/ext/Zvknhb.yaml +4 -2
  206. data/.data/spec/std/isa/ext/Zvksed.yaml +3 -0
  207. data/.data/spec/std/isa/ext/Zvksh.yaml +3 -0
  208. data/.data/spec/std/isa/ext/Zvkt.yaml +3 -0
  209. data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
  210. data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
  211. data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
  212. data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
  213. data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
  214. data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
  215. data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
  216. data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
  217. data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
  218. data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
  219. data/.data/spec/std/isa/inst/C/c.add.yaml +1 -0
  220. data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
  221. data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
  222. data/.data/spec/std/isa/inst/C/c.addw.yaml +1 -0
  223. data/.data/spec/std/isa/inst/C/c.and.yaml +1 -0
  224. data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
  225. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +3 -3
  226. data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
  227. data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -0
  228. data/.data/spec/std/isa/inst/C/c.nop.yaml +13 -2
  229. data/.data/spec/std/isa/inst/C/c.or.yaml +1 -0
  230. data/.data/spec/std/isa/inst/C/c.slli.yaml +1 -0
  231. data/.data/spec/std/isa/inst/C/c.srai.yaml +1 -0
  232. data/.data/spec/std/isa/inst/C/c.srli.yaml +1 -0
  233. data/.data/spec/std/isa/inst/C/c.sub.yaml +1 -0
  234. data/.data/spec/std/isa/inst/C/c.subw.yaml +1 -0
  235. data/.data/spec/std/isa/inst/C/c.xor.yaml +1 -0
  236. data/.data/spec/std/isa/inst/D/fld.yaml +1 -0
  237. data/.data/spec/std/isa/inst/D/fsd.yaml +1 -0
  238. data/.data/spec/std/isa/inst/F/fadd.s.yaml +1 -1
  239. data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
  240. data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
  241. data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
  242. data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
  243. data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
  244. data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
  245. data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
  246. data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
  247. data/.data/spec/std/isa/inst/F/feq.s.yaml +1 -1
  248. data/.data/spec/std/isa/inst/F/fle.s.yaml +1 -1
  249. data/.data/spec/std/isa/inst/F/fleq.s.yaml +1 -1
  250. data/.data/spec/std/isa/inst/F/flt.s.yaml +1 -1
  251. data/.data/spec/std/isa/inst/F/fltq.s.yaml +1 -1
  252. data/.data/spec/std/isa/inst/F/flw.yaml +2 -1
  253. data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
  254. data/.data/spec/std/isa/inst/F/fmax.s.yaml +1 -1
  255. data/.data/spec/std/isa/inst/F/fmin.s.yaml +1 -1
  256. data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
  257. data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
  258. data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +1 -1
  259. data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
  260. data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +1 -1
  261. data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
  262. data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
  263. data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
  264. data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
  265. data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
  266. data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
  267. data/.data/spec/std/isa/inst/F/fsw.yaml +2 -1
  268. data/.data/spec/std/isa/inst/I/addi.yaml +1 -0
  269. data/.data/spec/std/isa/inst/I/addiw.yaml +1 -0
  270. data/.data/spec/std/isa/inst/I/andi.yaml +1 -0
  271. data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
  272. data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
  273. data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
  274. data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
  275. data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
  276. data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
  277. data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
  278. data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
  279. data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
  280. data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
  281. data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
  282. data/.data/spec/std/isa/inst/I/sd.yaml +2 -1
  283. data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
  284. data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
  285. data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -0
  286. data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
  287. data/.data/spec/std/isa/inst/I/xori.yaml +1 -0
  288. data/.data/spec/std/isa/inst/Q/fadd.q.yaml +2 -2
  289. data/.data/spec/std/isa/inst/Q/fclass.q.yaml +5 -5
  290. data/.data/spec/std/isa/inst/Q/fleq.q.yaml +0 -1
  291. data/.data/spec/std/isa/inst/Q/fli.q.yaml +1 -1
  292. data/.data/spec/std/isa/inst/Q/flq.yaml +1 -0
  293. data/.data/spec/std/isa/inst/Q/fltq.q.yaml +0 -1
  294. data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml +0 -1
  295. data/.data/spec/std/isa/inst/Q/fminm.q.yaml +0 -1
  296. data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml +1 -1
  297. data/.data/spec/std/isa/inst/Q/fsq.yaml +1 -0
  298. data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
  299. data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
  300. data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
  301. data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -0
  302. data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
  303. data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
  304. data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
  305. data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
  306. data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +1 -0
  307. data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +1 -0
  308. data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +1 -0
  309. data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +1 -0
  310. data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
  311. data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +1 -0
  312. data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
  313. data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
  314. data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
  315. data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
  316. data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -0
  317. data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
  318. data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
  319. data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
  320. data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
  321. data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
  322. data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
  323. data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
  324. data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
  325. data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +1 -0
  326. data/.data/spec/std/isa/inst/Zcb/c.not.yaml +1 -0
  327. data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml +2 -7
  328. data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +1 -1
  329. data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml +2 -0
  330. data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml +2 -0
  331. data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout +7 -0
  332. data/.data/spec/std/isa/inst/Zfa/fli.s.yaml +1 -1
  333. data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml +1 -1
  334. data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml +1 -1
  335. data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
  336. data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml +1 -1
  337. data/.data/spec/std/isa/inst/Zfh/flh.yaml +5 -2
  338. data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +3 -1
  339. data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +3 -1
  340. data/.data/spec/std/isa/inst/Zfh/fsh.yaml +4 -1
  341. data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
  342. data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
  343. data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
  344. data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml +30 -0
  345. data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml +29 -0
  346. data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml +1 -1
  347. data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml +1 -1
  348. data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +12 -0
  349. data/.data/spec/std/isa/inst/Zilx/lxd.yaml +38 -0
  350. data/.data/spec/std/isa/inst/Zilx/lxh.yaml +35 -0
  351. data/.data/spec/std/isa/inst/Zilx/lxhu.yaml +35 -0
  352. data/.data/spec/std/isa/inst/Zilx/lxsb.yaml +40 -0
  353. data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml +40 -0
  354. data/.data/spec/std/isa/inst/Zilx/lxsd.yaml +38 -0
  355. data/.data/spec/std/isa/inst/Zilx/lxsh.yaml +35 -0
  356. data/.data/spec/std/isa/inst/Zilx/lxshu.yaml +35 -0
  357. data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml +40 -0
  358. data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml +40 -0
  359. data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml +39 -0
  360. data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml +40 -0
  361. data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml +40 -0
  362. data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml +40 -0
  363. data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml +40 -0
  364. data/.data/spec/std/isa/inst/Zilx/lxsw.yaml +35 -0
  365. data/.data/spec/std/isa/inst/Zilx/lxswu.yaml +39 -0
  366. data/.data/spec/std/isa/inst/Zilx/lxw.yaml +35 -0
  367. data/.data/spec/std/isa/inst/Zilx/lxwu.yaml +39 -0
  368. data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
  369. data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
  370. data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
  371. data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
  372. data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +67 -0
  373. data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +67 -0
  374. data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml +61 -0
  375. data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +72 -0
  376. data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +72 -0
  377. data/.data/spec/std/isa/isa/builtin_functions.idl +1 -0
  378. data/.data/spec/std/isa/isa/fp.idl +42 -18
  379. data/.data/spec/std/isa/isa/globals.isa +27 -7
  380. data/.data/spec/std/isa/isa/interrupts.idl +1 -0
  381. data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml +70 -6
  382. data/.data/spec/std/isa/param/ELEN.yaml +27 -5
  383. data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +13 -0
  384. data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml +13 -3
  385. data/.data/spec/std/isa/param/HPM_EVENTS.yaml +0 -3
  386. data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
  387. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +8 -0
  388. data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
  389. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +71 -64
  390. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +71 -64
  391. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
  392. data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
  393. data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
  394. data/.data/spec/std/isa/param/{STVEC_MODE_VECTORED.yaml → PMP_NAPOT_SUPPORTED.yaml} +9 -9
  395. data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
  396. data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
  397. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +3 -2
  398. data/.data/spec/std/isa/param/STVEC_BASE_ALIGNMENT_VECTORED.yaml +100 -0
  399. data/.data/spec/std/isa/param/STVEC_MODES.yaml +31 -0
  400. data/.data/spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml +1 -1
  401. data/.data/spec/std/isa/param/SXLEN.yaml +2 -2
  402. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml +1 -1
  403. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml +1 -1
  404. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml +1 -1
  405. data/.data/spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml +1 -1
  406. data/.data/spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml +1 -1
  407. data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
  408. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
  409. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
  410. data/.data/spec/std/isa/param/UXLEN.yaml +1 -1
  411. data/.data/spec/std/isa/param/VLEN.yaml +16 -7
  412. data/.data/spec/std/isa/param/VSTVEC_MODES.yaml +31 -0
  413. data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
  414. data/lib/udb/ESPRESSO_VERSION +1 -1
  415. data/lib/udb/Z3_VERSION +1 -1
  416. data/lib/udb/config.rb +14 -2
  417. data/lib/udb/doc_link.rb +3 -4
  418. data/lib/udb/obj/csr.rb +1 -1
  419. data/lib/udb/obj/csr_field.rb +1 -1
  420. data/lib/udb/obj/extension.rb +1 -1
  421. data/lib/udb/obj/instruction.rb +1 -1
  422. data/lib/udb/obj/non_isa_specification.rb +22 -100
  423. data/lib/udb/version.rb +1 -1
  424. data/lib/udb/version_spec.rb +1 -1
  425. data/lib/udb/z3.rb +31 -9
  426. metadata +42 -9
  427. data/.data/spec/std/isa/param/STVEC_MODE_DIRECT.yaml +0 -21
  428. data/.data/spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml +0 -21
  429. data/.data/spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml +0 -21
@@ -28,9 +28,6 @@ definedBy:
28
28
  - name: HPM_COUNTER_EN
29
29
  index: 4
30
30
  equal: true
31
- - name: HPM_COUNTER_EN
32
- index: 4
33
- equal: true
34
31
  - name: HPM_COUNTER_EN
35
32
  index: 5
36
33
  equal: true
@@ -19,6 +19,7 @@ schema:
19
19
  - rw
20
20
  - read-only-0
21
21
  - read-only-1
22
+ default: rw
22
23
  requirements:
23
24
  idl(): |
24
25
  MSTATEEN_CONTEXT_TYPE == "read-only-0" -> HSTATEEN_CONTEXT_TYPE == "read-only-0";
@@ -27,6 +27,14 @@ definedBy:
27
27
  name: Sm
28
28
  requirements:
29
29
  idl(): |
30
+ for (U32 i = 0; i < 3; i++) {
31
+ !implemented?(ExtensionName::Zicntr) -> !MCOUNTENABLE_EN[i];
32
+ }
30
33
  for (U32 i=3; i < 32; i++) {
34
+ !implemented?(ExtensionName::Zihpm) -> !MCOUNTENABLE_EN[i];
31
35
  MCOUNTENABLE_EN[i] -> HPM_COUNTER_EN[i];
32
36
  }
37
+ reason: |
38
+ Counters 0-2 are defined by Zicntr
39
+ Counters 3..31 are defined by Zihpm
40
+ When mhpmcounter[i] is not implemented, it cannot be enabled.
@@ -19,6 +19,7 @@ schema:
19
19
  - rw
20
20
  - read-only-0
21
21
  - read-only-1
22
+ default: rw
22
23
  definedBy:
23
24
  extension:
24
25
  allOf:
@@ -25,72 +25,79 @@ description: |
25
25
  the base, the minimum alignment cannot be less than 4.
26
26
  schema:
27
27
  description: An unsigned power of 2 greater than or equal to 4 that fits in 64 bits
28
+ default: 0x4
28
29
  enum:
29
30
  [
30
- 4,
31
- 8,
32
- 16,
33
- 32,
34
- 64,
35
- 128,
36
- 256,
37
- 512,
38
- 1024,
39
- 2048,
40
- 4095,
41
- 8192,
42
- 16384,
43
- 32768,
44
- 65536,
45
- 131072,
46
- 262144,
47
- 524288,
48
- 1048576,
49
- 2097152,
50
- 4194304,
51
- 8388608,
52
- 16777216,
53
- 33554432,
54
- 67108864,
55
- 134217728,
56
- 268435456,
57
- 536870912,
58
- 1073741824,
59
- 2147483648,
60
- 4294967296,
61
- 8589934592,
62
- 17179869184,
63
- 34359738368,
64
- 68719476736,
65
- 137438953472,
66
- 274877906944,
67
- 549755813888,
68
- 1099511627776,
69
- 2199023255552,
70
- 4398046511104,
71
- 8796093022208,
72
- 17592186044416,
73
- 35184372088832,
74
- 70368744177664,
75
- 140737488355328,
76
- 281474976710656,
77
- 562949953421312,
78
- 1125899906842624,
79
- 2251799813685248,
80
- 4503599627370496,
81
- 9007199254740992,
82
- 18014398509481984,
83
- 36028797018963968,
84
- 72057594037927936,
85
- 144115188075855872,
86
- 288230376151711744,
87
- 576460752303423488,
88
- 1152921504606846976,
89
- 2305843009213693952,
90
- 4611686018427387904,
91
- 9223372036854775808,
31
+ 0x4,
32
+ 0x8,
33
+ 0x10,
34
+ 0x20,
35
+ 0x40,
36
+ 0x80,
37
+ 0x100,
38
+ 0x200,
39
+ 0x400,
40
+ 0x800,
41
+ 0x1000,
42
+ 0x2000,
43
+ 0x4000,
44
+ 0x8000,
45
+ 0x10000,
46
+ 0x20000,
47
+ 0x40000,
48
+ 0x80000,
49
+ 0x100000,
50
+ 0x200000,
51
+ 0x400000,
52
+ 0x800000,
53
+ 0x1000000,
54
+ 0x2000000,
55
+ 0x4000000,
56
+ 0x8000000,
57
+ 0x10000000,
58
+ 0x20000000,
59
+ 0x40000000,
60
+ 0x80000000,
61
+ 0x100000000,
62
+ 0x200000000,
63
+ 0x400000000,
64
+ 0x800000000,
65
+ 0x1000000000,
66
+ 0x2000000000,
67
+ 0x4000000000,
68
+ 0x8000000000,
69
+ 0x10000000000,
70
+ 0x20000000000,
71
+ 0x40000000000,
72
+ 0x80000000000,
73
+ 0x100000000000,
74
+ 0x200000000000,
75
+ 0x400000000000,
76
+ 0x800000000000,
77
+ 0x1000000000000,
78
+ 0x2000000000000,
79
+ 0x4000000000000,
80
+ 0x8000000000000,
81
+ 0x10000000000000,
82
+ 0x20000000000000,
83
+ 0x40000000000000,
84
+ 0x80000000000000,
85
+ 0x100000000000000,
86
+ 0x200000000000000,
87
+ 0x400000000000000,
88
+ 0x800000000000000,
89
+ 0x1000000000000000,
90
+ 0x2000000000000000,
91
+ 0x4000000000000000,
92
+ 0x8000000000000000,
92
93
  ]
93
94
 
94
95
  requirements:
95
- idl(): |
96
- (MXLEN == 32) -> MTVEC_BASE_ALIGNMENT_DIRECT <= 2147483648;
96
+ if:
97
+ param:
98
+ name: MXLEN
99
+ equal: 32
100
+ then:
101
+ param:
102
+ name: MTVEC_BASE_ALIGNMENT_DIRECT
103
+ lessThanOrEqual: 0x80000000
@@ -25,72 +25,79 @@ description: |
25
25
  the base, the minimum alignment cannot be less than 4.
26
26
  schema:
27
27
  description: An unsigned power of 2 greater than or equal to 4 that fits in 64 bits
28
+ default: 0x4
28
29
  enum:
29
30
  [
30
- 4,
31
- 8,
32
- 16,
33
- 32,
34
- 64,
35
- 128,
36
- 256,
37
- 512,
38
- 1024,
39
- 2048,
40
- 4095,
41
- 8192,
42
- 16384,
43
- 32768,
44
- 65536,
45
- 131072,
46
- 262144,
47
- 524288,
48
- 1048576,
49
- 2097152,
50
- 4194304,
51
- 8388608,
52
- 16777216,
53
- 33554432,
54
- 67108864,
55
- 134217728,
56
- 268435456,
57
- 536870912,
58
- 1073741824,
59
- 2147483648,
60
- 4294967296,
61
- 8589934592,
62
- 17179869184,
63
- 34359738368,
64
- 68719476736,
65
- 137438953472,
66
- 274877906944,
67
- 549755813888,
68
- 1099511627776,
69
- 2199023255552,
70
- 4398046511104,
71
- 8796093022208,
72
- 17592186044416,
73
- 35184372088832,
74
- 70368744177664,
75
- 140737488355328,
76
- 281474976710656,
77
- 562949953421312,
78
- 1125899906842624,
79
- 2251799813685248,
80
- 4503599627370496,
81
- 9007199254740992,
82
- 18014398509481984,
83
- 36028797018963968,
84
- 72057594037927936,
85
- 144115188075855872,
86
- 288230376151711744,
87
- 576460752303423488,
88
- 1152921504606846976,
89
- 2305843009213693952,
90
- 4611686018427387904,
91
- 9223372036854775808,
31
+ 0x4,
32
+ 0x8,
33
+ 0x10,
34
+ 0x20,
35
+ 0x40,
36
+ 0x80,
37
+ 0x100,
38
+ 0x200,
39
+ 0x400,
40
+ 0x800,
41
+ 0x1000,
42
+ 0x2000,
43
+ 0x4000,
44
+ 0x8000,
45
+ 0x10000,
46
+ 0x20000,
47
+ 0x40000,
48
+ 0x80000,
49
+ 0x100000,
50
+ 0x200000,
51
+ 0x400000,
52
+ 0x800000,
53
+ 0x1000000,
54
+ 0x2000000,
55
+ 0x4000000,
56
+ 0x8000000,
57
+ 0x10000000,
58
+ 0x20000000,
59
+ 0x40000000,
60
+ 0x80000000,
61
+ 0x100000000,
62
+ 0x200000000,
63
+ 0x400000000,
64
+ 0x800000000,
65
+ 0x1000000000,
66
+ 0x2000000000,
67
+ 0x4000000000,
68
+ 0x8000000000,
69
+ 0x10000000000,
70
+ 0x20000000000,
71
+ 0x40000000000,
72
+ 0x80000000000,
73
+ 0x100000000000,
74
+ 0x200000000000,
75
+ 0x400000000000,
76
+ 0x800000000000,
77
+ 0x1000000000000,
78
+ 0x2000000000000,
79
+ 0x4000000000000,
80
+ 0x8000000000000,
81
+ 0x10000000000000,
82
+ 0x20000000000000,
83
+ 0x40000000000000,
84
+ 0x80000000000000,
85
+ 0x100000000000000,
86
+ 0x200000000000000,
87
+ 0x400000000000000,
88
+ 0x800000000000000,
89
+ 0x1000000000000000,
90
+ 0x2000000000000000,
91
+ 0x4000000000000000,
92
+ 0x8000000000000000,
92
93
  ]
93
94
 
94
95
  requirements:
95
- idl(): |
96
- (MXLEN == 32) -> MTVEC_BASE_ALIGNMENT_VECTORED <= 2147483648;
96
+ if:
97
+ param:
98
+ name: MXLEN
99
+ equal: 32
100
+ then:
101
+ param:
102
+ name: MTVEC_BASE_ALIGNMENT_VECTORED
103
+ lessThanOrEqual: 0x80000000
@@ -7,36 +7,25 @@ $schema: param_schema.json#
7
7
  kind: parameter
8
8
  name: NUM_PMP_ENTRIES
9
9
  description: |
10
- Number of implemented PMP entries. Can be any value between 0-64, inclusive.
10
+ Number of implemented PMP entries.
11
11
 
12
12
  The architecture mandates that the number of implemented PMP registers
13
- must appear to be 0, 16, or 64.
14
-
15
- Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:
16
-
17
- [separator="!"]
18
- !===
19
- ! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15>
20
- ! 0 ! N ! N
21
- ! 1-16 ! Y ! N
22
- ! 17-64 ! Y ! Y
23
- !===
24
-
25
- ** N = Not implemented; access will cause `IllegalInstruction`
26
- if TRAP_ON_UNIMPLEMENTED_CSR is true
27
- ** Y = Implemented; access will not cause an exception (from M-mode), but register
28
- may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register
13
+ must appear to be 0, 16, or 64, so NUM_PMP_ENTRIES must be one of those values.
14
+ It directly determines which PMP registers exist: `pmpaddr0`-`pmpaddr<N-1>`
15
+ and their corresponding `pmpNcfg` fields are implemented, and the rest are
16
+ not. Accessing an unimplemented PMP register causes an `IllegalInstruction`
17
+ when TRAP_ON_UNIMPLEMENTED_CSR is true.
29
18
 
30
19
  [NOTE]
31
- `pmpcfgN` for an odd N never exists when XLEN == 64
20
+ `pmpcfgN` for an odd N never exists when XLEN == 64.
32
21
 
33
- When NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers,
34
- and associated pmpNcfg, will be read-only zero (but will never cause an exception).
22
+ An implemented entry may still be read-only zero (but will never cause an exception).
23
+ The number of entries that are actually usable is given by
24
+ NUM_USABLE_PMP_ENTRIES.
35
25
  long_name: TODO
36
26
  schema:
37
27
  type: integer
38
- minimum: 0
39
- maximum: 64
28
+ enum: [0, 16, 64]
40
29
  definedBy:
41
30
  extension:
42
31
  name: Sm
@@ -0,0 +1,35 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../schemas/param_schema.json
5
+
6
+ $schema: param_schema.json#
7
+ kind: parameter
8
+ name: NUM_USABLE_PMP_ENTRIES
9
+ description: |
10
+ Number of implemented PMP entries that are actually usable.
11
+
12
+ An implementation may implement PMP entries (NUM_PMP_ENTRIES) but hardwire
13
+ some of them to zero (read-only zero). Such entries exist -- their
14
+ `pmpaddrN`/`pmpNcfg` registers are accessible and will not cause an exception
15
+ from M-mode -- but they cannot be configured to guard a region.
16
+
17
+ NUM_USABLE_PMP_ENTRIES gives the number of low-numbered entries that are
18
+ writable/usable. Entries `0` through `NUM_USABLE_PMP_ENTRIES-1` are usable;
19
+ entries `NUM_USABLE_PMP_ENTRIES` through `NUM_PMP_ENTRIES-1` are read-only
20
+ zero.
21
+
22
+ Must be between 0 and NUM_PMP_ENTRIES, inclusive.
23
+ long_name: TODO
24
+ schema:
25
+ type: integer
26
+ minimum: 0
27
+ maximum: 64
28
+ definedBy:
29
+ param:
30
+ name: NUM_PMP_ENTRIES
31
+ greaterThan: 0
32
+ requirements:
33
+ idl(): |
34
+ NUM_PMP_ENTRIES == 16 -> NUM_USABLE_PMP_ENTRIES <= 16;
35
+ reason: Usable PMP entries cannot exceed the number of implemented PMP entries
@@ -0,0 +1,23 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../schemas/param_schema.json
5
+
6
+ $schema: param_schema.json#
7
+ kind: parameter
8
+ name: PMP_NA4_SUPPORTED
9
+ description: |
10
+ Whether or not the Naturally Aligned four-byte (NA4) PMP address matching
11
+ mode is supported.
12
+
13
+ long_name: PMP NA4 mode supported
14
+ schema:
15
+ type: boolean
16
+ definedBy:
17
+ param:
18
+ name: NUM_PMP_ENTRIES
19
+ greaterThan: 0
20
+ requirements:
21
+ idl(): |
22
+ PMP_NA4_SUPPORTED -> (PMP_GRANULARITY == 2);
23
+ reason: NA4 is not valid when the PMP granularity is larger than 4 bytes
@@ -5,15 +5,15 @@
5
5
 
6
6
  $schema: param_schema.json#
7
7
  kind: parameter
8
- name: STVEC_MODE_VECTORED
9
- description: Whether or not `stvec.MODE` supports Vectored (1).
10
- long_name: TODO
8
+ name: PMP_NAPOT_SUPPORTED
9
+ description: |
10
+ Whether or not the Naturally Aligned Power-Of-Two (NAPOT) PMP address
11
+ matching mode is supported.
12
+
13
+ long_name: PMP NAPOT mode supported
11
14
  schema:
12
15
  type: boolean
13
- requirements:
14
- idl(): |
15
- !STVEC_MODE_DIRECT -> STVEC_MODE_VECTORED;
16
- reason: stvec must support at least one mode
17
16
  definedBy:
18
- extension:
19
- name: S
17
+ param:
18
+ name: NUM_PMP_ENTRIES
19
+ greaterThan: 0
@@ -5,14 +5,14 @@
5
5
 
6
6
  $schema: param_schema.json#
7
7
  kind: parameter
8
- name: MSTATUS_TVM_IMPLEMENTED
8
+ name: PMP_TOR_SUPPORTED
9
9
  description: |
10
- Whether or not mstatus.TVM is implemented.
10
+ Whether or not the Top-of-Range (TOR) PMP address matching mode is supported.
11
11
 
12
- When not implemented mstatus.TVM will be read-only-zero.
13
- long_name: TODO
12
+ long_name: PMP TOR mode supported
14
13
  schema:
15
14
  type: boolean
16
15
  definedBy:
17
- extension:
18
- name: S
16
+ param:
17
+ name: NUM_PMP_ENTRIES
18
+ greaterThan: 0
@@ -15,3 +15,4 @@ description: |
15
15
  will cause execution to enter an unpredictable state.
16
16
  schema:
17
17
  type: boolean
18
+ default: true
@@ -10,10 +10,11 @@ description: |
10
10
  The number of implemented bits in `stval`.
11
11
 
12
12
  Must be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `VA_SIZE`)
13
- long_name: TODO
13
+ long_name: "`stval` implemented bits"
14
14
  schema:
15
15
  type: integer
16
- maximum: 18446744073709551615
16
+ minimum: 0
17
+ maximum: 64
17
18
  definedBy:
18
19
  extension:
19
20
  name: S
@@ -0,0 +1,100 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../schemas/param_schema.json
5
+
6
+ $schema: param_schema.json#
7
+ kind: parameter
8
+ name: STVEC_BASE_ALIGNMENT_VECTORED
9
+ long_name: |
10
+ Minimum alignment of `stvec.BASE` when `stvec.MODE` is 1 (Vectored)
11
+ definedBy:
12
+ allOf:
13
+ - extension:
14
+ name: S
15
+ - param:
16
+ name: STVEC_MODES
17
+ includes: 1
18
+ reason: Only relevant when vectored mode is supported
19
+ description: |
20
+ Minimum alignment of the base pointer when `stvec.MODE` is Vectored. Because
21
+ `stvec` excludes the two least-significant bits of the base, the minimum
22
+ alignment cannot be less than 4 bytes.
23
+ schema:
24
+ description: An unsigned power of 2 greater than or equal to 4 that fits in 64 bits
25
+ default: 0x4
26
+ enum:
27
+ [
28
+ 0x4,
29
+ 0x8,
30
+ 0x10,
31
+ 0x20,
32
+ 0x40,
33
+ 0x80,
34
+ 0x100,
35
+ 0x200,
36
+ 0x400,
37
+ 0x800,
38
+ 0x1000,
39
+ 0x2000,
40
+ 0x4000,
41
+ 0x8000,
42
+ 0x10000,
43
+ 0x20000,
44
+ 0x40000,
45
+ 0x80000,
46
+ 0x100000,
47
+ 0x200000,
48
+ 0x400000,
49
+ 0x800000,
50
+ 0x1000000,
51
+ 0x2000000,
52
+ 0x4000000,
53
+ 0x8000000,
54
+ 0x10000000,
55
+ 0x20000000,
56
+ 0x40000000,
57
+ 0x80000000,
58
+ 0x100000000,
59
+ 0x200000000,
60
+ 0x400000000,
61
+ 0x800000000,
62
+ 0x1000000000,
63
+ 0x2000000000,
64
+ 0x4000000000,
65
+ 0x8000000000,
66
+ 0x10000000000,
67
+ 0x20000000000,
68
+ 0x40000000000,
69
+ 0x80000000000,
70
+ 0x100000000000,
71
+ 0x200000000000,
72
+ 0x400000000000,
73
+ 0x800000000000,
74
+ 0x1000000000000,
75
+ 0x2000000000000,
76
+ 0x4000000000000,
77
+ 0x8000000000000,
78
+ 0x10000000000000,
79
+ 0x20000000000000,
80
+ 0x40000000000000,
81
+ 0x80000000000000,
82
+ 0x100000000000000,
83
+ 0x200000000000000,
84
+ 0x400000000000000,
85
+ 0x800000000000000,
86
+ 0x1000000000000000,
87
+ 0x2000000000000000,
88
+ 0x4000000000000000,
89
+ 0x8000000000000000,
90
+ ]
91
+
92
+ requirements:
93
+ if:
94
+ param:
95
+ name: SXLEN
96
+ includes: 32
97
+ then:
98
+ param:
99
+ name: STVEC_BASE_ALIGNMENT_VECTORED
100
+ lessThanOrEqual: 0x80000000
@@ -0,0 +1,31 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../schemas/param_schema.json
5
+
6
+ $schema: param_schema.json#
7
+ kind: parameter
8
+ name: STVEC_MODES
9
+ long_name: |
10
+ Modes supported by `stvec.MODE`
11
+ definedBy:
12
+ extension:
13
+ name: S
14
+ description: |
15
+ Options:
16
+
17
+ 0::
18
+ Direct; All traps set `pc` to `stvec.BASE`
19
+ 1::
20
+ Vectored; Asynchronous interrupts set `pc` to `stvec.BASE` + 4 x cause.
21
+
22
+ If only one mode is given, `stvec.MODE` is assumed to be read-only with that value.
23
+ Otherwise, `stvec.MODE` is read-write.
24
+ schema:
25
+ type: array
26
+ items:
27
+ type: integer
28
+ enum: [0, 1]
29
+ minItems: 1
30
+ maxItems: 2
31
+ uniqueItems: true
@@ -16,7 +16,7 @@ requirements:
16
16
  idl(): |
17
17
  # at least one of Bare, Sv32 must be supported
18
18
  !VSSTAGE_MODE_BARE
19
- -> SV39_VSMODE_TRANSLATION;
19
+ -> SV32_VSMODE_TRANSLATION;
20
20
  reason: at least one of Bare, Sv32 must be supported
21
21
  definedBy:
22
22
  allOf:
@@ -9,8 +9,8 @@ name: SXLEN
9
9
  description: |
10
10
  Set of XLENs supported in S-mode. Can be one of:
11
11
 
12
- * 32: SXLEN is always 32
13
- * 64: SXLEN is always 64
12
+ * [32]: SXLEN is always 32
13
+ * [64]: SXLEN is always 64
14
14
  * [32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64
15
15
  long_name: TODO
16
16
  schema:
@@ -7,7 +7,7 @@ $schema: param_schema.json#
7
7
  kind: parameter
8
8
  name: TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT
9
9
  description: |
10
- Value to write into htval/mtval2 when there is a guest page fault on a final translation.
10
+ Value written into htinst/mtinst when there is an instruction guest-page fault on a final translation.
11
11
 
12
12
  Possible values:
13
13
  * "always zero": Always write the value zero