udb 0.1.13 → 0.1.15

data/.data/spec/custom/isa/qc_iu/isa/globals.isa

@@ -103,14 +103,15 @@ function raise_ilut {
   }
 }
 
-function is_pc_relative_inst? {
+function is_pc_referencing_inst? {
   returns Boolean
   arguments Bits<32> inst
   description {
-    Returns true if +inst+ is a PC-relative instruction (auipc, branch, jump, or
-    compressed PC-relative jump (jal/c.j/c.jal), or compressed branch) that is
-    forbidden inside an ILUT entry. Register-indirect jumps (jalr, c.jr, c.jalr)
-    are NOT PC-relative and are permitted inside ILUT entries.
+    Returns true if +inst+ references PC as an input or output, making it
+    forbidden inside an ILUT entry. This covers three categories:
+    (1) PC-relative instructions: auipc, branches, jal, c.j, c.jal, c.beqz, c.bnez;
+    (2) register-indirect jumps that write PC: jalr, c.jr, c.jalr;
+    (3) return instructions that write PC: cm.popret, cm.popretz, qc.cm.popret, qc.cm.popretz.
     For 16-bit compressed instructions, only the lower 16 bits of +inst+ are examined.
     For 48-bit Xqci instructions, only the lower 32 bits are passed here (the upper
     16 bits are in a separate word and are not needed for this check).
@@ -135,6 +136,22 @@ function is_pc_relative_inst? {
       if (cinst[15:13] == 3'b111 && cinst[1:0] == 2'b01) {
         return true;
       }
+      # c.jr:   bits[15:12]=1000, bits[6:2]!=00000, bits[1:0]=10 (register jump, writes PC)
+      if (cinst[15:12] == 4'b1000 && cinst[6:2] != 5'b00000 && cinst[1:0] == 2'b10) {
+        return true;
+      }
+      # c.jalr: bits[15:12]=1001, bits[6:2]!=00000, bits[1:0]=10 (register jump-and-link, writes PC)
+      if (cinst[15:12] == 4'b1001 && cinst[6:2] != 5'b00000 && cinst[1:0] == 2'b10) {
+        return true;
+      }
+      # cm.popret / qc.cm.popret: bits[15:8]=10111110, bits[1:0]=10 (pops stack and returns, writes PC)
+      if (cinst[15:8] == 8'b10111110 && cinst[1:0] == 2'b10) {
+        return true;
+      }
+      # cm.popretz / qc.cm.popretz: bits[15:8]=10111100, bits[1:0]=10 (pops stack, zeroes a0, returns, writes PC)
+      if (cinst[15:8] == 8'b10111100 && cinst[1:0] == 2'b10) {
+        return true;
+      }
       return false;
     } else {
       # 32-bit (or 48-bit) instruction: check opcode field bits[6:0]
@@ -147,6 +164,11 @@ function is_pc_relative_inst? {
       if (opcode == 7'b1101111) {
         return true;
       }
+      # jalr: register-indirect jump, writes PC
+      # (grouped with PC-referencing instructions, not PC-relative)
+      if (opcode == 7'b1100111) {
+        return true;
+      }
       # branches
       if (opcode == 7'b1100011) {
         return true;

data/.data/spec/schemas/README.adoc

@@ -80,6 +80,9 @@ version should be released.  Follow these steps:
 . The CI `schema-release` workflow will automatically publish the new version
   as a GitHub release under the tag `schemas/<schema_name>/<version>` when the
   changes are merged to `main`.
+. Published schema version assets are immutable. If a release already exists
+  with different content, the publish workflow fails; bump the schema `$id`
+  instead of overwriting an existing version.
 . Previous schema versions remain available via their GitHub release tags and
   at `https://riscv.github.io/riscv-unified-db/schemas/<schema_name>/<old-version>/<schema_name>`.
 

data/.data/spec/schemas/config_schema.json

@@ -75,7 +75,7 @@
                 "description": "Extension name"
               },
               "version": {
-                "$ref": "schema_defs.json#/$defs/extension_version"
+                "$ref": "schema_defs.json#/$defs/implemented_extension_version"
               }
             }
           },

data/.data/spec/schemas/mmr_schema.json

@@ -35,11 +35,11 @@
       "description": "One line description for the MMR"
     },
     "description": {
-      "$ref": "schema_defs.json#/definitions/spec_text",
+      "$ref": "schema_defs.json#/$defs/spec_text",
       "description": "Function of the register"
     },
     "definedBy": {
-      "$ref": "schema_defs.json#/definitions/condition",
+      "$ref": "schema_defs.json#/$defs/condition",
       "description": "Extension(s) that define the MMR"
     },
     "physical_address": {
@@ -59,7 +59,7 @@
       "type": "object",
       "patternProperties": {
         "^[a-zA-Z].*$": {
-          "$ref": "csr_schema.json#/definitions/csr_field"
+          "$ref": "csr_schema.json#/$defs/csr_field"
         }
       },
       "description": "fields of this MMR",

data/.data/spec/schemas/schema_defs.json

@@ -1,6 +1,6 @@
 {
   "$schema": "http://json-schema.org/draft-07/schema#",
-  "$id": "v0.1",
+  "$id": "v0.2",
   "title": "Common patterns used by all schemas",
   "$defs": {
     "$source": {
@@ -231,6 +231,11 @@
       "$ref": "#/$defs/rvi_version",
       "description": "Exact version in `MAJOR[.MINOR[.PATCH]]` format (e.g., `2.1.0`, `2.1`, `2`)"
     },
+    "implemented_extension_version": {
+      "type": "string",
+      "description": "Exact implemented extension version, either bare or prefixed with `=` (e.g., `2.1.0`, `2.1`, `= 2.1`)",
+      "pattern": "^(=\\s*)?[0-9]+(\\.[0-9]+(\\.[0-9]+(-pre)?)?)?$"
+    },
     "requirement_string": {
       "type": "string",
       "description": "Version requirement string (e.g., `>= 2.0`, `~> 1.5`, `= 2.1`). The `~>` operator is a pessimistic version constraint: `~> X.Y` means `>= X.Y` and `< (X+1).0`; `~> X.Y.Z` means `>= X.Y.Z` and `< X.(Y+1).0`.",
@@ -858,7 +863,7 @@
       "description": "An unsigned power of 2 that fits in 32 bits",
       "type": "integer",
       "enum": [
-        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, 16384,
+        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,
         32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304,
         8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912,
         1073741824, 2147483648
@@ -868,7 +873,7 @@
       "description": "An unsigned power of 2 that fits in 64 bits",
       "type": "integer",
       "enum": [
-        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, 16384,
+        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,
         32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304,
         8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912,
         1073741824, 2147483648, 4294967296, 8589934592, 17179869184,

data/.data/spec/std/isa/csr/H/hcounteren.layout

@@ -76,7 +76,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `time` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -116,7 +116,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `instret` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -154,7 +154,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`mcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`scounteren.HPM<%= hpm_num %>`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`mcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`scounteren.HPM<%= hpm_num %>`# 2+^.>! `hpmcounter<%= hpm_num %>` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`

data/.data/spec/std/isa/csr/H/hcounteren.yaml

@@ -79,7 +79,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `time` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -119,7 +119,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `instret` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -156,7 +156,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM3`# .2+h! [.rotate]#`mcounteren.HPM3`# .2+h! [.rotate]#`scounteren.HPM3`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM3`# .2+h! [.rotate]#`mcounteren.HPM3`# .2+h! [.rotate]#`scounteren.HPM3`# 2+^.>! `hpmcounter3` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -193,7 +193,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM4`# .2+h! [.rotate]#`mcounteren.HPM4`# .2+h! [.rotate]#`scounteren.HPM4`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM4`# .2+h! [.rotate]#`mcounteren.HPM4`# .2+h! [.rotate]#`scounteren.HPM4`# 2+^.>! `hpmcounter4` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -230,7 +230,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM5`# .2+h! [.rotate]#`mcounteren.HPM5`# .2+h! [.rotate]#`scounteren.HPM5`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM5`# .2+h! [.rotate]#`mcounteren.HPM5`# .2+h! [.rotate]#`scounteren.HPM5`# 2+^.>! `hpmcounter5` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -267,7 +267,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM6`# .2+h! [.rotate]#`mcounteren.HPM6`# .2+h! [.rotate]#`scounteren.HPM6`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM6`# .2+h! [.rotate]#`mcounteren.HPM6`# .2+h! [.rotate]#`scounteren.HPM6`# 2+^.>! `hpmcounter6` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -304,7 +304,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM7`# .2+h! [.rotate]#`mcounteren.HPM7`# .2+h! [.rotate]#`scounteren.HPM7`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM7`# .2+h! [.rotate]#`mcounteren.HPM7`# .2+h! [.rotate]#`scounteren.HPM7`# 2+^.>! `hpmcounter7` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -341,7 +341,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM8`# .2+h! [.rotate]#`mcounteren.HPM8`# .2+h! [.rotate]#`scounteren.HPM8`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM8`# .2+h! [.rotate]#`mcounteren.HPM8`# .2+h! [.rotate]#`scounteren.HPM8`# 2+^.>! `hpmcounter8` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -378,7 +378,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM9`# .2+h! [.rotate]#`mcounteren.HPM9`# .2+h! [.rotate]#`scounteren.HPM9`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM9`# .2+h! [.rotate]#`mcounteren.HPM9`# .2+h! [.rotate]#`scounteren.HPM9`# 2+^.>! `hpmcounter9` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -415,7 +415,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM10`# .2+h! [.rotate]#`mcounteren.HPM10`# .2+h! [.rotate]#`scounteren.HPM10`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM10`# .2+h! [.rotate]#`mcounteren.HPM10`# .2+h! [.rotate]#`scounteren.HPM10`# 2+^.>! `hpmcounter10` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -452,7 +452,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM11`# .2+h! [.rotate]#`mcounteren.HPM11`# .2+h! [.rotate]#`scounteren.HPM11`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM11`# .2+h! [.rotate]#`mcounteren.HPM11`# .2+h! [.rotate]#`scounteren.HPM11`# 2+^.>! `hpmcounter11` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -489,7 +489,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM12`# .2+h! [.rotate]#`mcounteren.HPM12`# .2+h! [.rotate]#`scounteren.HPM12`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM12`# .2+h! [.rotate]#`mcounteren.HPM12`# .2+h! [.rotate]#`scounteren.HPM12`# 2+^.>! `hpmcounter12` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -526,7 +526,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM13`# .2+h! [.rotate]#`mcounteren.HPM13`# .2+h! [.rotate]#`scounteren.HPM13`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM13`# .2+h! [.rotate]#`mcounteren.HPM13`# .2+h! [.rotate]#`scounteren.HPM13`# 2+^.>! `hpmcounter13` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -563,7 +563,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM14`# .2+h! [.rotate]#`mcounteren.HPM14`# .2+h! [.rotate]#`scounteren.HPM14`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM14`# .2+h! [.rotate]#`mcounteren.HPM14`# .2+h! [.rotate]#`scounteren.HPM14`# 2+^.>! `hpmcounter14` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -600,7 +600,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM15`# .2+h! [.rotate]#`mcounteren.HPM15`# .2+h! [.rotate]#`scounteren.HPM15`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM15`# .2+h! [.rotate]#`mcounteren.HPM15`# .2+h! [.rotate]#`scounteren.HPM15`# 2+^.>! `hpmcounter15` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -637,7 +637,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM16`# .2+h! [.rotate]#`mcounteren.HPM16`# .2+h! [.rotate]#`scounteren.HPM16`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM16`# .2+h! [.rotate]#`mcounteren.HPM16`# .2+h! [.rotate]#`scounteren.HPM16`# 2+^.>! `hpmcounter16` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -674,7 +674,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM17`# .2+h! [.rotate]#`mcounteren.HPM17`# .2+h! [.rotate]#`scounteren.HPM17`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM17`# .2+h! [.rotate]#`mcounteren.HPM17`# .2+h! [.rotate]#`scounteren.HPM17`# 2+^.>! `hpmcounter17` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -711,7 +711,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM18`# .2+h! [.rotate]#`mcounteren.HPM18`# .2+h! [.rotate]#`scounteren.HPM18`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM18`# .2+h! [.rotate]#`mcounteren.HPM18`# .2+h! [.rotate]#`scounteren.HPM18`# 2+^.>! `hpmcounter18` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -748,7 +748,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM19`# .2+h! [.rotate]#`mcounteren.HPM19`# .2+h! [.rotate]#`scounteren.HPM19`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM19`# .2+h! [.rotate]#`mcounteren.HPM19`# .2+h! [.rotate]#`scounteren.HPM19`# 2+^.>! `hpmcounter19` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -785,7 +785,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM20`# .2+h! [.rotate]#`mcounteren.HPM20`# .2+h! [.rotate]#`scounteren.HPM20`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM20`# .2+h! [.rotate]#`mcounteren.HPM20`# .2+h! [.rotate]#`scounteren.HPM20`# 2+^.>! `hpmcounter20` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -822,7 +822,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM21`# .2+h! [.rotate]#`mcounteren.HPM21`# .2+h! [.rotate]#`scounteren.HPM21`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM21`# .2+h! [.rotate]#`mcounteren.HPM21`# .2+h! [.rotate]#`scounteren.HPM21`# 2+^.>! `hpmcounter21` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -859,7 +859,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM22`# .2+h! [.rotate]#`mcounteren.HPM22`# .2+h! [.rotate]#`scounteren.HPM22`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM22`# .2+h! [.rotate]#`mcounteren.HPM22`# .2+h! [.rotate]#`scounteren.HPM22`# 2+^.>! `hpmcounter22` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -896,7 +896,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM23`# .2+h! [.rotate]#`mcounteren.HPM23`# .2+h! [.rotate]#`scounteren.HPM23`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM23`# .2+h! [.rotate]#`mcounteren.HPM23`# .2+h! [.rotate]#`scounteren.HPM23`# 2+^.>! `hpmcounter23` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -933,7 +933,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM24`# .2+h! [.rotate]#`mcounteren.HPM24`# .2+h! [.rotate]#`scounteren.HPM24`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM24`# .2+h! [.rotate]#`mcounteren.HPM24`# .2+h! [.rotate]#`scounteren.HPM24`# 2+^.>! `hpmcounter24` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -970,7 +970,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM25`# .2+h! [.rotate]#`mcounteren.HPM25`# .2+h! [.rotate]#`scounteren.HPM25`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM25`# .2+h! [.rotate]#`mcounteren.HPM25`# .2+h! [.rotate]#`scounteren.HPM25`# 2+^.>! `hpmcounter25` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1007,7 +1007,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM26`# .2+h! [.rotate]#`mcounteren.HPM26`# .2+h! [.rotate]#`scounteren.HPM26`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM26`# .2+h! [.rotate]#`mcounteren.HPM26`# .2+h! [.rotate]#`scounteren.HPM26`# 2+^.>! `hpmcounter26` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1044,7 +1044,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM27`# .2+h! [.rotate]#`mcounteren.HPM27`# .2+h! [.rotate]#`scounteren.HPM27`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM27`# .2+h! [.rotate]#`mcounteren.HPM27`# .2+h! [.rotate]#`scounteren.HPM27`# 2+^.>! `hpmcounter27` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1081,7 +1081,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM28`# .2+h! [.rotate]#`mcounteren.HPM28`# .2+h! [.rotate]#`scounteren.HPM28`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM28`# .2+h! [.rotate]#`mcounteren.HPM28`# .2+h! [.rotate]#`scounteren.HPM28`# 2+^.>! `hpmcounter28` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1118,7 +1118,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM29`# .2+h! [.rotate]#`mcounteren.HPM29`# .2+h! [.rotate]#`scounteren.HPM29`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM29`# .2+h! [.rotate]#`mcounteren.HPM29`# .2+h! [.rotate]#`scounteren.HPM29`# 2+^.>! `hpmcounter29` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1155,7 +1155,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM30`# .2+h! [.rotate]#`mcounteren.HPM30`# .2+h! [.rotate]#`scounteren.HPM30`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM30`# .2+h! [.rotate]#`mcounteren.HPM30`# .2+h! [.rotate]#`scounteren.HPM30`# 2+^.>! `hpmcounter30` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1192,7 +1192,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM31`# .2+h! [.rotate]#`mcounteren.HPM31`# .2+h! [.rotate]#`scounteren.HPM31`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM31`# .2+h! [.rotate]#`mcounteren.HPM31`# .2+h! [.rotate]#`scounteren.HPM31`# 2+^.>! `hpmcounter31` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`

data/.data/spec/std/isa/csr/H/henvcfg.yaml

@@ -289,6 +289,27 @@ fields:
         return 0;
       }
       return csr_value.SSE;
+  LPE:
+    location: 2
+    description: |
+      *Landing Pad Enable*
+
+      When the LPE field is set to 1, the Zicfilp extension is enabled in
+      VS-mode. When the LPE field is 0, the Zicfilp extension is not enabled
+      in VS-mode and the following rules apply to VS-mode:
+
+        * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
+        * The `LPAD` instruction operates as a no-op.
+    definedBy:
+      extension:
+        name: Zicfilp
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[menvcfg].LPE == 0){
+        return 0;
+      }
+      return csr_value.LPE;
   FIOM:
     location: 0
     description: |
@@ -336,4 +357,8 @@ sw_read(): |
     # henvcfg.SSE must read-as-zero
     value = value & ~(1 `<< 3);
   }
+  if (implemented?(ExtensionName::Zicfilp) && CSR[menvcfg].LPE == 0) {
+    # henvcfg.LPE must read-as-zero
+    value = value & ~(1 `<< 2);
+  }
   return value;

data/.data/spec/std/isa/csr/H/htinst.yaml

@@ -10,9 +10,9 @@ address: 0x64a
 writable: true
 long_name: Hypervisor Trap Instruction Register
 description: |
-  When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,
+  When a trap is taken into HS-mode, htinst is written with a value that, if nonzero,
   provides information about the instruction that trapped, to assist software in handling the trap.
-  The values that may be written to mtinst on a trap are documented in TODO.
+  The values that may be written to htinst on a trap are documented in TODO.
 
   htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap.
 priv_mode: S
@@ -34,7 +34,7 @@ fields:
           || (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
           || (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
-          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
+          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_UCALL != "always zero")
           || (TINST_VALUE_ON_SCALL != "always zero")
           || (TINST_VALUE_ON_MCALL != "always zero")

data/.data/spec/std/isa/csr/H/htval.yaml

@@ -19,8 +19,8 @@ description: |
   Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in htval corresponds to the faulting portion of the access as indicated by the virtual address in stval. For instruction guest-page faults on systems with variable-length instructions, a nonzero htval corresponds to the faulting portion of the instruction as indicated by the virtual address in stval.
 
   htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.
-priv_mode: M
-length: MXLEN
+priv_mode: S
+length: SXLEN
 definedBy:
   extension:
     name: H
@@ -38,5 +38,5 @@ fields:
         return CsrFieldType::RO;
       }
     description: |
-      Exception-specific information for a trap into M-mode.
+      Exception-specific information for a trap into HS-mode.
     reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/H/mtinst.yaml

@@ -34,7 +34,7 @@ fields:
           || (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
           || (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
-          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
+          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_UCALL != "always zero")
           || (TINST_VALUE_ON_SCALL != "always zero")
           || (TINST_VALUE_ON_MCALL != "always zero")

data/.data/spec/std/isa/csr/I/pmpaddr0.yaml

@@ -30,17 +30,19 @@ fields:
       Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 0
       (or, if `pmp1cfg.A` == TOR, for PMP entry 1).
     type(): |
-      if (NUM_PMP_ENTRIES > 0) {
+      if (NUM_USABLE_PMP_ENTRIES > 0) {
         return CsrFieldType::RW;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (NUM_PMP_ENTRIES <= 0) {
+      if (NUM_USABLE_PMP_ENTRIES <= 0) {
+        # entry is not usable (not implemented or read-only zero)
+        return 0;
+      } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
         return UNDEFINED_LEGAL_DETERMINISTIC;
       } else {
         return csr_value.ADDR;

data/.data/spec/std/isa/csr/I/pmpaddr1.yaml

@@ -30,17 +30,19 @@ fields:
       Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 1
       (or, if `pmp2cfg.A` == TOR, for PMP entry 2).
     type(): |
-      if (NUM_PMP_ENTRIES > 1) {
+      if (NUM_USABLE_PMP_ENTRIES > 1) {
         return CsrFieldType::RW;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (NUM_PMP_ENTRIES <= 1) {
+      if (NUM_USABLE_PMP_ENTRIES <= 1) {
+        # entry is not usable (not implemented or read-only zero)
+        return 0;
+      } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
         return UNDEFINED_LEGAL_DETERMINISTIC;
       } else {
         return csr_value.ADDR;

data/.data/spec/std/isa/csr/I/pmpaddr10.yaml

@@ -30,17 +30,19 @@ fields:
       Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 10
       (or, if `pmp11cfg.A` == TOR, for PMP entry 11).
     type(): |
-      if (NUM_PMP_ENTRIES > 10) {
+      if (NUM_USABLE_PMP_ENTRIES > 10) {
         return CsrFieldType::RW;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (NUM_PMP_ENTRIES <= 10) {
+      if (NUM_USABLE_PMP_ENTRIES <= 10) {
+        # entry is not usable (not implemented or read-only zero)
+        return 0;
+      } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
         return UNDEFINED_LEGAL_DETERMINISTIC;
       } else {
         return csr_value.ADDR;

data/.data/spec/std/isa/csr/I/pmpaddr11.yaml

@@ -30,17 +30,19 @@ fields:
       Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 11
       (or, if `pmp12cfg.A` == TOR, for PMP entry 12).
     type(): |
-      if (NUM_PMP_ENTRIES > 11) {
+      if (NUM_USABLE_PMP_ENTRIES > 11) {
         return CsrFieldType::RW;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (NUM_PMP_ENTRIES <= 11) {
+      if (NUM_USABLE_PMP_ENTRIES <= 11) {
+        # entry is not usable (not implemented or read-only zero)
+        return 0;
+      } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
         return UNDEFINED_LEGAL_DETERMINISTIC;
       } else {
         return csr_value.ADDR;

data/.data/spec/std/isa/csr/I/pmpaddr12.yaml

@@ -30,17 +30,19 @@ fields:
       Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 12
       (or, if `pmp13cfg.A` == TOR, for PMP entry 13).
     type(): |
-      if (NUM_PMP_ENTRIES > 12) {
+      if (NUM_USABLE_PMP_ENTRIES > 12) {
         return CsrFieldType::RW;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (NUM_PMP_ENTRIES <= 12) {
+      if (NUM_USABLE_PMP_ENTRIES <= 12) {
+        # entry is not usable (not implemented or read-only zero)
+        return 0;
+      } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
         return UNDEFINED_LEGAL_DETERMINISTIC;
       } else {
         return csr_value.ADDR;