udb 0.1.13 → 0.1.15

data/.data/spec/std/isa/csr/sie.yaml

@@ -15,34 +15,60 @@ definedBy:
 length: SXLEN
 description: Supervisor interrupt-enable register.
 writable: true
+sw_read(): |
+  return $bits(CSR[mie]) & $bits(CSR[mideleg]);
 fields:
   SSIE:
     location: 1
     alias: mie.SSIE
     description: |
       Supervisor Software Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].SSI == 1'b1) {
+        CSR[mie].SSIE = csr_value.SSIE;
+        return csr_value.SSIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
   STIE:
     location: 5
     alias: mie.STIE
     description: |
       Supervisor Timer Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].STI == 1'b1) {
+        CSR[mie].STIE = csr_value.STIE;
+        return csr_value.STIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
   SEIE:
     location: 9
     alias: mie.SEIE
     description: |
       Supervisor External Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].SEI == 1'b1) {
+        CSR[mie].SEIE = csr_value.SEIE;
+        return csr_value.SEIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
   LCOFIE:
     location: 13
     alias: mie.LCOFIE
     description: |
       Local Counter Overflow Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].LCOFI == 1'b1) {
+        CSR[mie].LCOFIE = csr_value.LCOFIE;
+        return csr_value.LCOFIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
     definedBy:
       extension:

data/.data/spec/std/isa/csr/sip.yaml

@@ -19,6 +19,8 @@ length: 64
 definedBy:
   extension:
     name: S
+sw_read(): |
+  return $bits(CSR[mip]) & $bits(CSR[mideleg]);
 fields:
   SSIP:
     location: 1
@@ -59,7 +61,13 @@ fields:
       ! 0 ! read-only 0
       ! 1 ! writable alias of `mip.SSIP` <% if ext?(:Smaia) %>and `mvip.SSIP`<% end %>
       !===
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].SSI == 1'b1) {
+        CSR[mip].SSIP = csr_value.SSIP;
+        return csr_value.SSIP;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
     definedBy:
       extension:
@@ -153,7 +161,13 @@ fields:
       ! 1
       a! writable alias of `mip.LCOFIP` (and `vsip.LCOFIP` when `hideleg.LCOFI` is set)
       !===
-    type: RW-H
+    type: RW-RH
+    sw_write(csr_value): |
+      if (CSR[mideleg].LCOFI == 1'b1) {
+        CSR[mip].LCOFIP = csr_value.LCOFIP;
+        return csr_value.LCOFIP;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
     definedBy:
       extension:

data/.data/spec/std/isa/csr/stvec.yaml

@@ -19,10 +19,10 @@ fields:
   BASE:
     location: 63-2
     description: |
-      <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 49 :39) -%>
-      Bit 63:0 of the virtual address of the exception vector for any trap taken into S-mode.
+      <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 48 : 39) -%>
+      Bits 63:2 of the virtual address of the exception vector for any trap taken into S-mode.
 
-      If the base address is written with a non-cannonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
+      If the base address is written with a non-canonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
       the write should be ignored.
 
     type: RW-R
@@ -41,14 +41,13 @@ fields:
 
       When Direct, all synchronous exceptions and asynchronous interrupts jump to (`stvec.BASE` << 2).
 
-      When Vectored, asynchronous interrupts jump to (`stvec.BASE` << 2 + `scause.CAUSE`*4) while synchronous exceptions continue to jump to (`stvec.BASE` << 2).
-    type: RW-R
+      When Vectored, asynchronous interrupts jump to (`stvec.BASE` << 2 + `scause.CODE`*4) while synchronous exceptions continue to jump to (`stvec.BASE` << 2).
+    type(): |
+      return ($array_size(STVEC_MODES) == 1) ? CsrFieldType::RO : CsrFieldType::RWR;
     sw_write(csr_value): |
-      if (STVEC_MODE_DIRECT && csr_value.MODE == 0) {
-        return 0;
-      } else if (STVEC_MODE_VECTORED && csr_value.MODE == 1) {
-        return 1;
-      } else {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
+      if ($array_includes?(STVEC_MODES, csr_value.MODE)) {
+        return csr_value.MODE;
       }
-    reset_value: 0
+      return UNDEFINED_LEGAL_DETERMINISTIC;
+    reset_value(): |
+      return ($array_size(STVEC_MODES) == 1) ? STVEC_MODES[0] : UNDEFINED_LEGAL;

data/.data/spec/std/isa/csr/vstval.yaml

@@ -11,7 +11,7 @@ address: 0x243
 writable: true
 virtual_address: 0x143
 description: Holds trap-specific information
-priv_mode: S
+priv_mode: VS
 length: VSXLEN
 definedBy:
   extension:

data/.data/spec/std/isa/csr/vstvec.yaml

@@ -6,11 +6,11 @@
 $schema: "csr_schema.json#"
 kind: csr
 name: vstvec
-long_name: Supervisor Trap Vector
+long_name: Virtual Supervisor Trap Vector
 address: 0x205
 writable: true
 virtual_address: 0x105
-priv_mode: S
+priv_mode: VS
 length: 64
 description: Controls where traps jump.
 definedBy:
@@ -20,17 +20,17 @@ fields:
   BASE:
     location: 63-2
     description: |
-      <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 49 :39) -%>
-      Bit 63:0 of the virtual address of the exception vector for any trap taken into VS-mode.
+      <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 48 : 39) -%>
+      Bits 63:2 of the virtual address of the exception vector for any trap taken into VS-mode.
 
-      If the base address is written with a non-cannonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
+      If the base address is written with a non-canonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
       the write should be ignored.
 
     type: RW-R
     sw_write(csr_value): |
       # Base spec says that BASE must be 4-byte aligned, which will always be the case
       # implementations may put further constraints on BASE when MODE != Direct
-      # If that is the case, stvec should have an override for the implementation
+      # If that is the case, vstvec should have an override for the implementation
       return csr_value.BASE;
     reset_value: 0
   MODE:
@@ -42,14 +42,13 @@ fields:
 
       When Direct, all synchronous exceptions and asynchronous interrupts jump to (`vstvec.BASE` << 2).
 
-      When Vectored, asynchronous interrupts jump to (`vstvec.BASE` << 2 + `vscause.CAUSE`*4) while synchronous exceptions continue to jump to (`vstvec.BASE` << 2).
-    type: RW-R
+      When Vectored, asynchronous interrupts jump to (`vstvec.BASE` << 2 + `vscause.CODE`*4) while synchronous exceptions continue to jump to (`vstvec.BASE` << 2).
+    type(): |
+      return ($array_size(VSTVEC_MODES) == 1) ? CsrFieldType::RO : CsrFieldType::RWR;
     sw_write(csr_value): |
-      if (VSTVEC_MODE_DIRECT && csr_value.MODE == 0) {
-        return 0;
-      } else if (VSTVEC_MODE_VECTORED && csr_value.MODE == 1) {
-        return 1;
-      } else {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
+      if ($array_includes?(VSTVEC_MODES, csr_value.MODE)) {
+        return csr_value.MODE;
       }
-    reset_value: 0
+      return UNDEFINED_LEGAL_DETERMINISTIC;
+    reset_value(): |
+      return ($array_size(VSTVEC_MODES) == 1) ? VSTVEC_MODES[0] : UNDEFINED_LEGAL;

data/.data/spec/std/isa/ext/Q.yaml

@@ -17,7 +17,7 @@ description: |
   a double-precision value which is itself NaN-boxed inside a quad-precision value.
 type: unprivileged
 versions:
-  - version: "1.0.0"
+  - version: "2.2.0"
     state: ratified
     ratification_date: 2019-04
     requirements:

data/.data/spec/std/isa/ext/Shlcofideleg.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Shlcofideleg
+long_name: Hypervisor local counter overflow interrupt delegation
+description: |
+  Shlcofideleg supports delegating Local Counter Overflow Interrupts
+  (LCOFIs) to VS-mode.
+
+  When Shlcofideleg is implemented, `hideleg` bit 13 is writable.
+type: privileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2024-10
+requirements:
+  extension:
+    allOf:
+      - name: H
+      - name: Sscofpmf

data/.data/spec/std/isa/ext/Shvstvecd.yaml

@@ -22,5 +22,5 @@ versions:
 requirements:
   # Shvstvecd mandates that `vstvec.MODE` must be capable of holding the value 0 (Direct).
   param:
-    name: VSTVEC_MODE_DIRECT
-    equal: true
+    name: VSTVEC_MODES
+    includes: 0

data/.data/spec/std/isa/ext/Sspm.yaml

@@ -21,3 +21,8 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  extension:
+    allOf:
+      - name: S
+      - name: Smnpm

data/.data/spec/std/isa/ext/Sstvecd.yaml

@@ -25,5 +25,5 @@ versions:
         company: SiFive, Inc.
 requirements:
   param:
-    name: STVEC_MODE_DIRECT
-    equal: true
+    name: STVEC_MODES
+    includes: 0

data/.data/spec/std/isa/ext/Sstvecv.yaml

@@ -26,5 +26,5 @@ versions:
         company: SiFive, Inc.
 requirements:
   param:
-    name: STVEC_MODE_VECTORED
-    equal: true
+    name: STVEC_MODES
+    includes: 1

data/.data/spec/std/isa/ext/Supm.yaml

@@ -21,3 +21,20 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - extension:
+        name: U
+    - if:
+        extension:
+          name: S
+      then:
+        extension:
+          name: Ssnpm
+    - if:
+        not:
+          extension:
+            name: S
+      then:
+        extension:
+          name: Smnpm

data/.data/spec/std/isa/ext/Zcb.yaml

@@ -43,3 +43,6 @@ versions:
       - name: Graeme Smecher
       - name: Nicolas Brunie
       - name: Jiawei
+requirements:
+  extension:
+    name: Zca

data/.data/spec/std/isa/ext/Zfbfmin.yaml

@@ -12,8 +12,8 @@ description: |
   It enables BF16 as an interchange format as it provides conversion between BF16 values and
   FP32 values.
 
-  This extension depends upon the single-precision floating-point extension `F`,
-  and the `flh`, `fsh`, `fmv.x.h`, and `fmv.h.x` instructions as defined in the `Zfh` extension.
+  This extension includes the `flh`, `fsh`, `fmv.x.h`, and `fmv.h.x`
+  instructions defined in the `Zfh` extension.
 
 type: unprivileged
 versions:
@@ -22,6 +22,4 @@ versions:
     ratification_date: 2024-06
 requirements:
   extension:
-    allOf:
-      - name: F
-      - name: Zfh
+    name: F

data/.data/spec/std/isa/ext/Ziccid.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Ziccid
+long_name: Instruction/Data Coherence and Consistency
+description: |
+  The `Ziccid` extension mandates more stringent requirements for consistency
+  between instruction fetches and other memory accesses than those imposed by
+  the base ISA.
+
+  `Ziccid` guarantees that a hart's instruction fetches appear to occur in
+  program order with respect to each other, and that stores eventually become
+  visible to all harts' instruction fetches.
+
+  [NOTE]
+  The primary intent of the `Ziccid` extension is to accelerate JIT compilation
+  in multiprocessor systems.
+type: unprivileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-06
+requirements:
+  extension:
+    name: Ziccif

data/.data/spec/std/isa/ext/Zicfilp.yaml

@@ -8,9 +8,13 @@ kind: extension
 name: Zicfilp
 long_name: Landing Pad
 description: |
-  TODO
+  The Zicfilp extension introduces a landing-pad instruction and related
+  execution state to enforce forward-edge control-flow integrity.
 type: unprivileged
 versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-07
+requirements:
+  extension:
+    name: Zicsr

data/.data/spec/std/isa/ext/Zicfiss.yaml

@@ -8,9 +8,28 @@ kind: extension
 name: Zicfiss
 long_name: Shadow Stack
 description: |
-  TODO
+  The Zicfiss extension introduces a shadow stack to enforce
+  backward-edge control-flow integrity.
+
+  The extension provides instructions to store and load the link register
+  to and from the shadow stack, check the integrity of the return address,
+  read the shadow stack pointer, and perform atomic swaps on shadow stack
+  locations.
 type: unprivileged
 versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-07
+requirements:
+  allOf:
+    - extension:
+        allOf:
+          - name: Zicsr
+          - name: Zimop
+          - name: Zaamo
+    - if:
+        extension:
+          name: U
+      then:
+        extension:
+          name: S

data/.data/spec/std/isa/ext/Zihpm.yaml

@@ -13,3 +13,6 @@ versions:
   - version: "2.0.0"
     state: ratified
     ratification_date: 2023-03
+requirements:
+  extension:
+    name: Zicsr

data/.data/spec/std/isa/ext/Zilx.yaml

@@ -0,0 +1,58 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zilx
+long_name: Indexed Integer Load Instructions
+description: |
+  The Zilx extension provides integer load instructions that compute their
+  effective address from a base register and an index register. The extension
+  defines unscaled indexed loads and scaled indexed loads. On RV64, the
+  extension also defines scaled loads that zero-extend the low 32 bits of the
+  index register before scaling and forming the effective address.
+
+  Each Zilx instruction uses `xs1` as the index operand and `xs2` as the base
+  operand, computes an effective address, loads a byte, halfword, word, or
+  doubleword from memory, and writes the extended load result to `xd`. The
+  operand roles match the shift-add instructions of the `Zba` extension, in
+  which the shifted operand is `xs1` and the added base is `xs2`.
+
+  Effective addresses are computed using XLEN-bit two's-complement address
+  arithmetic, and address arithmetic overflow is ignored:
+
+  * For an unscaled indexed load, the effective address is the low XLEN bits of
+    `X[xs2] + X[xs1]`.
+  * For a scaled indexed load, the effective address is the low XLEN bits of
+    `X[xs2] + (X[xs1] << log2(access-size))`, where _access-size_ is the number
+    of bytes loaded by the instruction.
+  * For a scaled unsigned-word-index load (mnemonic prefix `lxsuw`), the index
+    operand is zero-extended from `X[xs1][31:0]` to 64 bits before scaling.
+    These instructions are defined only for RV64.
+
+  Byte loads are provided only as scaled forms (mnemonic prefixes `lxs` and
+  `lxsuw`). Because the scale factor for a byte access is 1, an unscaled byte
+  load would be identical to the scaled byte load, so no unscaled byte load is
+  defined. For convenience, `lxb` and `lxbu` are provided as assembler
+  pseudoinstructions for `lxsb` and `lxsbu`, respectively.
+
+  Zilx adds no architectural state, CSRs, or memory-ordering rules. Except for
+  the effective-address calculation, each Zilx instruction behaves as the
+  corresponding base integer load of the same access size and signedness, and
+  follows the same exception, address-alignment, access-fault, page-fault, PMP,
+  PMA, privilege, atomicity, and memory-ordering rules.
+
+  Zilx instructions reuse the `AMO` major opcode. The access width and
+  signedness are encoded in _funct3_ using the same encoding as base integer
+  loads, and the addressing mode is encoded in _funct5_. For all Zilx
+  instructions the _aq_ and _rl_ bits must be 0; encodings with _aq_ or _rl_
+  set are reserved.
+type: unprivileged
+versions:
+  - version: "0.1.0"
+    state: development
+    repositories:
+      - url: https://github.com/riscv/riscv-zilx
+        branch: main

data/.data/spec/std/isa/ext/Zkt.yaml

@@ -203,6 +203,21 @@ description: |
   |          | ✓ | sraw  _rd_, _rs1_, _rs2_ |  'sraw'
   |===
 
+  ===  Zicond (Conditional Zero)
+
+  All instructions are included.
+
+  [%header,cols="^1,^1,4,8"]
+  |===
+  |RV32
+  |RV64
+  |Mnemonic
+  |Instruction
+
+  | ✓ | ✓ | czero.eqz _rd_, _rs1_, _rs2_ | 'czero.eqz'
+  | ✓ | ✓ | czero.nez _rd_, _rs1_, _rs2_ | 'czero.nez'
+  |===
+
   ===	RVM (Multiply)
 
   Multiplication is included; division and remaindering excluded.
@@ -221,7 +236,7 @@ description: |
   |          | ✓ | mulw   _rd_, _rs1_, _rs2_ | 'mulw'
   |===
 
-  ===	RVC (Compressed)
+  ===	Zca (Compressed)
 
   Same criteria as in RVI. Organised by quadrants.
 
@@ -250,6 +265,23 @@ description: |
   | ✓ | ✓ | c.add      | 'c_add'
   |===
 
+  ===	Zcb Extension
+
+  These instructions are compressed versions of `I` and `M` instructions that are
+  included in `Zkt`.
+
+  [%header,cols="^1,^1,4,8"]
+  |===
+  |RV32
+  |RV64
+  |Mnemonic
+  |Instruction
+
+  | ✓ | ✓ | c.mul       | 'c_mul'
+  | ✓ | ✓ | c.not       | 'c_not'
+  | ✓ | ✓ | c.zext.b    | 'c_zext_b'
+  |===
+
   ===	RVK (Scalar Cryptography)
 
   All K-specific instructions are included.

data/.data/spec/std/isa/ext/Zvabd.yaml

@@ -0,0 +1,21 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvabd
+long_name: Vector Integer Absolute Difference
+description: |
+  The Zvabd extension defines element-wise absolute difference instructions for
+  vectors of integers, including widening absolute-difference-and-accumulate
+  variants. These operations are widely used in image registration, object
+  recognition, motion estimation, and loop filters for video workloads.
+type: unprivileged
+versions:
+  - version: "0.7.0"
+    state: frozen
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvbc.yaml

@@ -17,3 +17,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve64x

data/.data/spec/std/isa/ext/Zvkb.yaml

@@ -14,3 +14,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvkg.yaml

@@ -24,3 +24,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvkned.yaml

@@ -20,3 +20,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvknha.yaml

@@ -15,3 +15,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvknhb.yaml

@@ -17,5 +17,7 @@ versions:
     ratification_date: 2023-09
     requirements:
       extension:
-        name: Zvknha
-        version: "= 1.0.0"
+        allOf:
+          - name: Zvknha
+            version: "= 1.0.0"
+          - name: Zve64x

data/.data/spec/std/isa/ext/Zvksed.yaml

@@ -22,3 +22,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvksh.yaml

@@ -18,3 +18,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zve32x

data/.data/spec/std/isa/ext/Zvkt.yaml

@@ -26,3 +26,6 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2023-09
+requirements:
+  extension:
+    name: Zvl32b

data/.data/spec/std/isa/inst/B/andn.yaml

@@ -16,17 +16,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ANDN
-      value: 0b0100000
-    funct3:
-      display_name: ANDN
-      value: 0b111
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------111-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always
@@ -38,4 +36,4 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[xd] = X[xs2] & ~X[xs1];
+  X[xd] = X[xs1] & ~X[xs2];