udb 0.1.13 → 0.1.15
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +20 -24
- data/.data/cfgs/mc100-32-full-example.yaml +2 -2
- data/.data/cfgs/qc_iu.yaml +7 -3
- data/.data/cfgs/rv32-riscv-tests.yaml +8 -5
- data/.data/cfgs/rv32-vector.yaml +8 -5
- data/.data/cfgs/rv64-riscv-tests.yaml +8 -5
- data/.data/cfgs/rv64-vector.yaml +8 -5
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +107 -36
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +52 -69
- data/.data/spec/custom/isa/qc_iu/isa/globals.isa +27 -5
- data/.data/spec/schemas/README.adoc +3 -0
- data/.data/spec/schemas/config_schema.json +1 -1
- data/.data/spec/schemas/mmr_schema.json +3 -3
- data/.data/spec/schemas/schema_defs.json +8 -3
- data/.data/spec/std/isa/csr/H/hcounteren.layout +3 -3
- data/.data/spec/std/isa/csr/H/hcounteren.yaml +31 -31
- data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
- data/.data/spec/std/isa/csr/H/htinst.yaml +3 -3
- data/.data/spec/std/isa/csr/H/htval.yaml +3 -3
- data/.data/spec/std/isa/csr/H/mtinst.yaml +1 -1
- data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
- data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfgN.layout +15 -18
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +1 -1
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +1 -1
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +1 -1
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +1 -1
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +1 -1
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +29 -29
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +1 -1
- data/.data/spec/std/isa/csr/hstatus.yaml +1 -1
- data/.data/spec/std/isa/csr/jvt.yaml +1 -0
- data/.data/spec/std/isa/csr/mcycle.yaml +6 -6
- data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
- data/.data/spec/std/isa/csr/minstret.yaml +3 -3
- data/.data/spec/std/isa/csr/minstreth.yaml +1 -1
- data/.data/spec/std/isa/csr/mstatus.yaml +21 -25
- data/.data/spec/std/isa/csr/mtvec.yaml +16 -57
- data/.data/spec/std/isa/csr/senvcfg.yaml +26 -0
- data/.data/spec/std/isa/csr/sie.yaml +30 -4
- data/.data/spec/std/isa/csr/sip.yaml +16 -2
- data/.data/spec/std/isa/csr/stvec.yaml +11 -12
- data/.data/spec/std/isa/csr/vstval.yaml +1 -1
- data/.data/spec/std/isa/csr/vstvec.yaml +14 -15
- data/.data/spec/std/isa/ext/Q.yaml +1 -1
- data/.data/spec/std/isa/ext/Shlcofideleg.yaml +24 -0
- data/.data/spec/std/isa/ext/Shvstvecd.yaml +2 -2
- data/.data/spec/std/isa/ext/Sspm.yaml +5 -0
- data/.data/spec/std/isa/ext/Sstvecd.yaml +2 -2
- data/.data/spec/std/isa/ext/Sstvecv.yaml +2 -2
- data/.data/spec/std/isa/ext/Supm.yaml +17 -0
- data/.data/spec/std/isa/ext/Zcb.yaml +3 -0
- data/.data/spec/std/isa/ext/Zfbfmin.yaml +3 -5
- data/.data/spec/std/isa/ext/Ziccid.yaml +29 -0
- data/.data/spec/std/isa/ext/Zicfilp.yaml +5 -1
- data/.data/spec/std/isa/ext/Zicfiss.yaml +20 -1
- data/.data/spec/std/isa/ext/Zihpm.yaml +3 -0
- data/.data/spec/std/isa/ext/Zilx.yaml +58 -0
- data/.data/spec/std/isa/ext/Zkt.yaml +33 -1
- data/.data/spec/std/isa/ext/Zvabd.yaml +21 -0
- data/.data/spec/std/isa/ext/Zvbc.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkb.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkg.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkned.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvknha.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvknhb.yaml +4 -2
- data/.data/spec/std/isa/ext/Zvksed.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvksh.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkt.yaml +3 -0
- data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
- data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
- data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
- data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
- data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
- data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
- data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
- data/.data/spec/std/isa/inst/C/c.add.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.and.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +3 -3
- data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.nop.yaml +13 -2
- data/.data/spec/std/isa/inst/C/c.or.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.slli.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.srai.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.srli.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.sub.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.subw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.xor.yaml +1 -0
- data/.data/spec/std/isa/inst/D/fld.yaml +1 -0
- data/.data/spec/std/isa/inst/D/fsd.yaml +1 -0
- data/.data/spec/std/isa/inst/F/fadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/feq.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fle.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fleq.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/flt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fltq.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/flw.yaml +2 -1
- data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmax.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmin.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsw.yaml +2 -1
- data/.data/spec/std/isa/inst/I/addi.yaml +1 -0
- data/.data/spec/std/isa/inst/I/addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/andi.yaml +1 -0
- data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
- data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sd.yaml +2 -1
- data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
- data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/xori.yaml +1 -0
- data/.data/spec/std/isa/inst/Q/fadd.q.yaml +2 -2
- data/.data/spec/std/isa/inst/Q/fclass.q.yaml +5 -5
- data/.data/spec/std/isa/inst/Q/fleq.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fli.q.yaml +1 -1
- data/.data/spec/std/isa/inst/Q/flq.yaml +1 -0
- data/.data/spec/std/isa/inst/Q/fltq.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fminm.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml +1 -1
- data/.data/spec/std/isa/inst/Q/fsq.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -0
- data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
- data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
- data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
- data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +1 -0
- data/.data/spec/std/isa/inst/Zcb/c.not.yaml +1 -0
- data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml +2 -7
- data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml +2 -0
- data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml +2 -0
- data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout +7 -0
- data/.data/spec/std/isa/inst/Zfa/fli.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/flh.yaml +5 -2
- data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +3 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +3 -1
- data/.data/spec/std/isa/inst/Zfh/fsh.yaml +4 -1
- data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml +30 -0
- data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml +29 -0
- data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +12 -0
- data/.data/spec/std/isa/inst/Zilx/lxd.yaml +38 -0
- data/.data/spec/std/isa/inst/Zilx/lxh.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxhu.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxsb.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsd.yaml +38 -0
- data/.data/spec/std/isa/inst/Zilx/lxsh.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxshu.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml +39 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsw.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxswu.yaml +39 -0
- data/.data/spec/std/isa/inst/Zilx/lxw.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxwu.yaml +39 -0
- data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +67 -0
- data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +67 -0
- data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml +61 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +72 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +72 -0
- data/.data/spec/std/isa/isa/builtin_functions.idl +1 -0
- data/.data/spec/std/isa/isa/fp.idl +42 -18
- data/.data/spec/std/isa/isa/globals.isa +27 -7
- data/.data/spec/std/isa/isa/interrupts.idl +1 -0
- data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml +70 -6
- data/.data/spec/std/isa/param/ELEN.yaml +27 -5
- data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +13 -0
- data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml +13 -3
- data/.data/spec/std/isa/param/HPM_EVENTS.yaml +0 -3
- data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
- data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +8 -0
- data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
- data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +71 -64
- data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +71 -64
- data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
- data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
- data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
- data/.data/spec/std/isa/param/{STVEC_MODE_VECTORED.yaml → PMP_NAPOT_SUPPORTED.yaml} +9 -9
- data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
- data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
- data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +3 -2
- data/.data/spec/std/isa/param/STVEC_BASE_ALIGNMENT_VECTORED.yaml +100 -0
- data/.data/spec/std/isa/param/STVEC_MODES.yaml +31 -0
- data/.data/spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml +1 -1
- data/.data/spec/std/isa/param/SXLEN.yaml +2 -2
- data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
- data/.data/spec/std/isa/param/UXLEN.yaml +1 -1
- data/.data/spec/std/isa/param/VLEN.yaml +16 -7
- data/.data/spec/std/isa/param/VSTVEC_MODES.yaml +31 -0
- data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
- data/lib/udb/ESPRESSO_VERSION +1 -1
- data/lib/udb/Z3_VERSION +1 -1
- data/lib/udb/config.rb +14 -2
- data/lib/udb/doc_link.rb +3 -4
- data/lib/udb/obj/csr.rb +1 -1
- data/lib/udb/obj/csr_field.rb +1 -1
- data/lib/udb/obj/extension.rb +1 -1
- data/lib/udb/obj/instruction.rb +1 -1
- data/lib/udb/obj/non_isa_specification.rb +22 -100
- data/lib/udb/version.rb +1 -1
- data/lib/udb/version_spec.rb +1 -1
- data/lib/udb/z3.rb +31 -9
- metadata +42 -9
- data/.data/spec/std/isa/param/STVEC_MODE_DIRECT.yaml +0 -21
- data/.data/spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml +0 -21
- data/.data/spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml +0 -21
|
@@ -38,21 +38,13 @@ fields:
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38
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h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
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39
39
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h! MT ! 6:5 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
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h! A ! 4:3
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a! Address matching mode.
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a! Address matching mode. Encodings:
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[when="PMP_GRANULARITY < 2"]
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* *OFF* (0) - Null region (disabled)
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44
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* *TOR* (1) - Top of range
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* *NA4* (2) - Naturally aligned four-byte region
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46
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* *NAPOT* (3) - Naturally aligned power of two
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47
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49
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[when="PMP_GRANULARITY >= 2"]
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50
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* *OFF* (0) - Null region (disabled)
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* *TOR* (1) - Top of range
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52
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* *NAPOT* (3) - Naturally aligned power of two
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54
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[when="PMP_GRANULARITY >= 2"]
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Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
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48
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49
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h! X ! 2 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
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h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
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The combination of R = 0, W = 1 is reserved.
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type(): |
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if (
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if (NUM_USABLE_PMP_ENTRIES > 36) {
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return CsrFieldType::RWR;
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# entry is either not implemented or implemented as read-only zero
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return CsrFieldType::RO;
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reset_value(): |
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return 0;
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sw_write(csr_value): |
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if ((CSR[pmpcfg9].pmp36cfg & 0x80) == 0) {
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# entry is not locked
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if (NUM_USABLE_PMP_ENTRIES > 36 && (CSR[pmpcfg9].pmp36cfg & 0x80) == 0) {
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# entry is usable and not locked
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Bits<8> new_cfg = csr_value.pmp36cfg;
|
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Bits<2> a_mode = (new_cfg & 0x18) >> 3;
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if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
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# not R = 0, W = 1, which is reserved
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if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
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((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
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73
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((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
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# unsupported address matching mode; keep old value
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return CSR[pmpcfg9].pmp36cfg;
|
|
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76
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}
|
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return new_cfg;
|
|
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}
|
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}
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# fall through: keep old value
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@@ -96,21 +93,13 @@ fields:
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h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
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94
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h! MT ! 14:13 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
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95
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h! A ! 12:11
|
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a! Address matching mode.
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a! Address matching mode. Encodings:
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[when="PMP_GRANULARITY < 2"]
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98
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* *OFF* (0) - Null region (disabled)
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99
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* *TOR* (1) - Top of range
|
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100
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* *NA4* (2) - Naturally aligned four-byte region
|
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105
101
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* *NAPOT* (3) - Naturally aligned power of two
|
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102
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[when="PMP_GRANULARITY >= 2"]
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108
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* *OFF* (0) - Null region (disabled)
|
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109
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* *TOR* (1) - Top of range
|
|
110
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* *NAPOT* (3) - Naturally aligned power of two
|
|
111
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-
|
|
112
|
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[when="PMP_GRANULARITY >= 2"]
|
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113
|
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Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
114
103
|
|
|
115
104
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h! X ! 10 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
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105
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h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
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@@ -119,23 +108,28 @@ fields:
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108
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109
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The combination of R = 0, W = 1 is reserved.
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110
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type(): |
|
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if (
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111
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+
if (NUM_USABLE_PMP_ENTRIES > 37) {
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112
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return CsrFieldType::RWR;
|
|
124
113
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} else {
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# entry is either not implemented or implemented as read-only zero
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115
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return CsrFieldType::RO;
|
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116
|
}
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117
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reset_value(): |
|
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118
|
return 0;
|
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119
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sw_write(csr_value): |
|
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130
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if ((CSR[pmpcfg9].pmp37cfg & 0x80) == 0) {
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131
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# entry is not locked
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132
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133
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134
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136
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120
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if (NUM_USABLE_PMP_ENTRIES > 37 && (CSR[pmpcfg9].pmp37cfg & 0x80) == 0) {
|
|
121
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+
# entry is usable and not locked
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122
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+
Bits<8> new_cfg = csr_value.pmp37cfg;
|
|
123
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
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124
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+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
125
|
+
# not R = 0, W = 1, which is reserved
|
|
126
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
127
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
128
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
129
|
+
# unsupported address matching mode; keep old value
|
|
130
|
+
return CSR[pmpcfg9].pmp37cfg;
|
|
138
131
|
}
|
|
132
|
+
return new_cfg;
|
|
139
133
|
}
|
|
140
134
|
}
|
|
141
135
|
# fall through: keep old value
|
|
@@ -154,21 +148,13 @@ fields:
|
|
|
154
148
|
h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
155
149
|
h! MT ! 22:21 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
156
150
|
h! A ! 20:19
|
|
157
|
-
a! Address matching mode.
|
|
151
|
+
a! Address matching mode. Encodings:
|
|
158
152
|
|
|
159
|
-
[when="PMP_GRANULARITY < 2"]
|
|
160
153
|
* *OFF* (0) - Null region (disabled)
|
|
161
154
|
* *TOR* (1) - Top of range
|
|
162
155
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
163
156
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
164
157
|
|
|
165
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
166
|
-
* *OFF* (0) - Null region (disabled)
|
|
167
|
-
* *TOR* (1) - Top of range
|
|
168
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
169
|
-
|
|
170
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
171
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
172
158
|
|
|
173
159
|
h! X ! 18 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
174
160
|
h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -177,23 +163,28 @@ fields:
|
|
|
177
163
|
|
|
178
164
|
The combination of R = 0, W = 1 is reserved.
|
|
179
165
|
type(): |
|
|
180
|
-
if (
|
|
166
|
+
if (NUM_USABLE_PMP_ENTRIES > 38) {
|
|
181
167
|
return CsrFieldType::RWR;
|
|
182
168
|
} else {
|
|
169
|
+
# entry is either not implemented or implemented as read-only zero
|
|
183
170
|
return CsrFieldType::RO;
|
|
184
171
|
}
|
|
185
172
|
reset_value(): |
|
|
186
173
|
return 0;
|
|
187
174
|
sw_write(csr_value): |
|
|
188
|
-
if ((CSR[pmpcfg9].pmp38cfg & 0x80) == 0) {
|
|
189
|
-
# entry is not locked
|
|
190
|
-
|
|
191
|
-
|
|
192
|
-
|
|
193
|
-
|
|
194
|
-
|
|
195
|
-
|
|
175
|
+
if (NUM_USABLE_PMP_ENTRIES > 38 && (CSR[pmpcfg9].pmp38cfg & 0x80) == 0) {
|
|
176
|
+
# entry is usable and not locked
|
|
177
|
+
Bits<8> new_cfg = csr_value.pmp38cfg;
|
|
178
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
179
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
180
|
+
# not R = 0, W = 1, which is reserved
|
|
181
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
182
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
183
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
184
|
+
# unsupported address matching mode; keep old value
|
|
185
|
+
return CSR[pmpcfg9].pmp38cfg;
|
|
196
186
|
}
|
|
187
|
+
return new_cfg;
|
|
197
188
|
}
|
|
198
189
|
}
|
|
199
190
|
# fall through: keep old value
|
|
@@ -212,21 +203,13 @@ fields:
|
|
|
212
203
|
h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
213
204
|
h! MT ! 30:29 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
214
205
|
h! A ! 28:27
|
|
215
|
-
a! Address matching mode.
|
|
206
|
+
a! Address matching mode. Encodings:
|
|
216
207
|
|
|
217
|
-
[when="PMP_GRANULARITY < 2"]
|
|
218
208
|
* *OFF* (0) - Null region (disabled)
|
|
219
209
|
* *TOR* (1) - Top of range
|
|
220
210
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
221
211
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
222
212
|
|
|
223
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
224
|
-
* *OFF* (0) - Null region (disabled)
|
|
225
|
-
* *TOR* (1) - Top of range
|
|
226
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
227
|
-
|
|
228
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
229
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
230
213
|
|
|
231
214
|
h! X ! 26 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
232
215
|
h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -235,23 +218,28 @@ fields:
|
|
|
235
218
|
|
|
236
219
|
The combination of R = 0, W = 1 is reserved.
|
|
237
220
|
type(): |
|
|
238
|
-
if (
|
|
221
|
+
if (NUM_USABLE_PMP_ENTRIES > 39) {
|
|
239
222
|
return CsrFieldType::RWR;
|
|
240
223
|
} else {
|
|
224
|
+
# entry is either not implemented or implemented as read-only zero
|
|
241
225
|
return CsrFieldType::RO;
|
|
242
226
|
}
|
|
243
227
|
reset_value(): |
|
|
244
228
|
return 0;
|
|
245
229
|
sw_write(csr_value): |
|
|
246
|
-
if ((CSR[pmpcfg9].pmp39cfg & 0x80) == 0) {
|
|
247
|
-
# entry is not locked
|
|
248
|
-
|
|
249
|
-
|
|
250
|
-
|
|
251
|
-
|
|
252
|
-
|
|
253
|
-
|
|
230
|
+
if (NUM_USABLE_PMP_ENTRIES > 39 && (CSR[pmpcfg9].pmp39cfg & 0x80) == 0) {
|
|
231
|
+
# entry is usable and not locked
|
|
232
|
+
Bits<8> new_cfg = csr_value.pmp39cfg;
|
|
233
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
234
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
235
|
+
# not R = 0, W = 1, which is reserved
|
|
236
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
237
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
238
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
239
|
+
# unsupported address matching mode; keep old value
|
|
240
|
+
return CSR[pmpcfg9].pmp39cfg;
|
|
254
241
|
}
|
|
242
|
+
return new_cfg;
|
|
255
243
|
}
|
|
256
244
|
}
|
|
257
245
|
# fall through: keep old value
|
|
@@ -50,21 +50,13 @@ fields:
|
|
|
50
50
|
h! L ! <%= ((i+1)*8)-1 %> ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
51
51
|
h! MT ! <%= ((i+1)*8)-2 %>:<%= ((i+1)*8)-3 %> ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
52
52
|
h! A ! <%= ((i+1)*8)-4 %>:<%= ((i+1)*8)-5 %>
|
|
53
|
-
a! Address matching mode.
|
|
53
|
+
a! Address matching mode. Encodings:
|
|
54
54
|
|
|
55
|
-
[when="PMP_GRANULARITY < 2"]
|
|
56
55
|
* *OFF* (0) - Null region (disabled)
|
|
57
56
|
* *TOR* (1) - Top of range
|
|
58
57
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
59
58
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
60
59
|
|
|
61
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
62
|
-
* *OFF* (0) - Null region (disabled)
|
|
63
|
-
* *TOR* (1) - Top of range
|
|
64
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
65
|
-
|
|
66
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
67
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
68
60
|
|
|
69
61
|
h! X ! <%= ((i)*8)+2 %> ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
70
62
|
h! W ! <%= ((i)*8)+1 %> ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -73,23 +65,28 @@ fields:
|
|
|
73
65
|
|
|
74
66
|
The combination of R = 0, W = 1 is reserved.
|
|
75
67
|
type(): |
|
|
76
|
-
if (
|
|
68
|
+
if (NUM_USABLE_PMP_ENTRIES > <%= pmpcfg_num*4 + i %>) {
|
|
77
69
|
return CsrFieldType::RWR;
|
|
78
70
|
} else {
|
|
71
|
+
# entry is either not implemented or implemented as read-only zero
|
|
79
72
|
return CsrFieldType::RO;
|
|
80
73
|
}
|
|
81
74
|
reset_value(): |
|
|
82
75
|
return 0;
|
|
83
76
|
sw_write(csr_value): |
|
|
84
|
-
if (<%- if i > 4 -%>(xlen() == 64) && <%- end -%>(CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg & 0x80) == 0) {
|
|
85
|
-
# entry is not locked
|
|
86
|
-
|
|
87
|
-
|
|
88
|
-
|
|
89
|
-
|
|
90
|
-
|
|
91
|
-
|
|
77
|
+
if (<%- if i > 4 -%>(xlen() == 64) && <%- end -%>NUM_USABLE_PMP_ENTRIES > <%= pmpcfg_num*4 + i %> && (CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg & 0x80) == 0) {
|
|
78
|
+
# entry is usable and not locked
|
|
79
|
+
Bits<8> new_cfg = csr_value.pmp<%= pmpcfg_num*4 + i %>cfg;
|
|
80
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
81
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
82
|
+
# not R = 0, W = 1, which is reserved
|
|
83
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
84
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
85
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
86
|
+
# unsupported address matching mode; keep old value
|
|
87
|
+
return CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg;
|
|
92
88
|
}
|
|
89
|
+
return new_cfg;
|
|
93
90
|
}
|
|
94
91
|
}
|
|
95
92
|
# fall through: keep old value
|
|
@@ -41,7 +41,7 @@ fields:
|
|
|
41
41
|
[when="HPM_COUNTER_EN[<%= of_num %>] == false"]
|
|
42
42
|
This field is read-only zero because the counter is not enabled.
|
|
43
43
|
type(): |
|
|
44
|
-
return HPM_COUNTER_EN[<%= of_num %>] ? CsrFieldType::
|
|
44
|
+
return HPM_COUNTER_EN[<%= of_num %>] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
45
45
|
reset_value(): |
|
|
46
46
|
return HPM_COUNTER_EN[<%= of_num %>] ? UNDEFINED_LEGAL : 0;
|
|
47
47
|
<%- end -%>
|
|
@@ -43,7 +43,7 @@ fields:
|
|
|
43
43
|
[when="HPM_COUNTER_EN[3] == false"]
|
|
44
44
|
This field is read-only zero because the counter is not enabled.
|
|
45
45
|
type(): |
|
|
46
|
-
return HPM_COUNTER_EN[3] ? CsrFieldType::
|
|
46
|
+
return HPM_COUNTER_EN[3] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
47
47
|
reset_value(): |
|
|
48
48
|
return HPM_COUNTER_EN[3] ? UNDEFINED_LEGAL : 0;
|
|
49
49
|
OF4:
|
|
@@ -56,7 +56,7 @@ fields:
|
|
|
56
56
|
[when="HPM_COUNTER_EN[4] == false"]
|
|
57
57
|
This field is read-only zero because the counter is not enabled.
|
|
58
58
|
type(): |
|
|
59
|
-
return HPM_COUNTER_EN[4] ? CsrFieldType::
|
|
59
|
+
return HPM_COUNTER_EN[4] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
60
60
|
reset_value(): |
|
|
61
61
|
return HPM_COUNTER_EN[4] ? UNDEFINED_LEGAL : 0;
|
|
62
62
|
OF5:
|
|
@@ -69,7 +69,7 @@ fields:
|
|
|
69
69
|
[when="HPM_COUNTER_EN[5] == false"]
|
|
70
70
|
This field is read-only zero because the counter is not enabled.
|
|
71
71
|
type(): |
|
|
72
|
-
return HPM_COUNTER_EN[5] ? CsrFieldType::
|
|
72
|
+
return HPM_COUNTER_EN[5] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
73
73
|
reset_value(): |
|
|
74
74
|
return HPM_COUNTER_EN[5] ? UNDEFINED_LEGAL : 0;
|
|
75
75
|
OF6:
|
|
@@ -82,7 +82,7 @@ fields:
|
|
|
82
82
|
[when="HPM_COUNTER_EN[6] == false"]
|
|
83
83
|
This field is read-only zero because the counter is not enabled.
|
|
84
84
|
type(): |
|
|
85
|
-
return HPM_COUNTER_EN[6] ? CsrFieldType::
|
|
85
|
+
return HPM_COUNTER_EN[6] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
86
86
|
reset_value(): |
|
|
87
87
|
return HPM_COUNTER_EN[6] ? UNDEFINED_LEGAL : 0;
|
|
88
88
|
OF7:
|
|
@@ -95,7 +95,7 @@ fields:
|
|
|
95
95
|
[when="HPM_COUNTER_EN[7] == false"]
|
|
96
96
|
This field is read-only zero because the counter is not enabled.
|
|
97
97
|
type(): |
|
|
98
|
-
return HPM_COUNTER_EN[7] ? CsrFieldType::
|
|
98
|
+
return HPM_COUNTER_EN[7] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
99
99
|
reset_value(): |
|
|
100
100
|
return HPM_COUNTER_EN[7] ? UNDEFINED_LEGAL : 0;
|
|
101
101
|
OF8:
|
|
@@ -108,7 +108,7 @@ fields:
|
|
|
108
108
|
[when="HPM_COUNTER_EN[8] == false"]
|
|
109
109
|
This field is read-only zero because the counter is not enabled.
|
|
110
110
|
type(): |
|
|
111
|
-
return HPM_COUNTER_EN[8] ? CsrFieldType::
|
|
111
|
+
return HPM_COUNTER_EN[8] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
112
112
|
reset_value(): |
|
|
113
113
|
return HPM_COUNTER_EN[8] ? UNDEFINED_LEGAL : 0;
|
|
114
114
|
OF9:
|
|
@@ -121,7 +121,7 @@ fields:
|
|
|
121
121
|
[when="HPM_COUNTER_EN[9] == false"]
|
|
122
122
|
This field is read-only zero because the counter is not enabled.
|
|
123
123
|
type(): |
|
|
124
|
-
return HPM_COUNTER_EN[9] ? CsrFieldType::
|
|
124
|
+
return HPM_COUNTER_EN[9] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
125
125
|
reset_value(): |
|
|
126
126
|
return HPM_COUNTER_EN[9] ? UNDEFINED_LEGAL : 0;
|
|
127
127
|
OF10:
|
|
@@ -134,7 +134,7 @@ fields:
|
|
|
134
134
|
[when="HPM_COUNTER_EN[10] == false"]
|
|
135
135
|
This field is read-only zero because the counter is not enabled.
|
|
136
136
|
type(): |
|
|
137
|
-
return HPM_COUNTER_EN[10] ? CsrFieldType::
|
|
137
|
+
return HPM_COUNTER_EN[10] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
138
138
|
reset_value(): |
|
|
139
139
|
return HPM_COUNTER_EN[10] ? UNDEFINED_LEGAL : 0;
|
|
140
140
|
OF11:
|
|
@@ -147,7 +147,7 @@ fields:
|
|
|
147
147
|
[when="HPM_COUNTER_EN[11] == false"]
|
|
148
148
|
This field is read-only zero because the counter is not enabled.
|
|
149
149
|
type(): |
|
|
150
|
-
return HPM_COUNTER_EN[11] ? CsrFieldType::
|
|
150
|
+
return HPM_COUNTER_EN[11] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
151
151
|
reset_value(): |
|
|
152
152
|
return HPM_COUNTER_EN[11] ? UNDEFINED_LEGAL : 0;
|
|
153
153
|
OF12:
|
|
@@ -160,7 +160,7 @@ fields:
|
|
|
160
160
|
[when="HPM_COUNTER_EN[12] == false"]
|
|
161
161
|
This field is read-only zero because the counter is not enabled.
|
|
162
162
|
type(): |
|
|
163
|
-
return HPM_COUNTER_EN[12] ? CsrFieldType::
|
|
163
|
+
return HPM_COUNTER_EN[12] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
164
164
|
reset_value(): |
|
|
165
165
|
return HPM_COUNTER_EN[12] ? UNDEFINED_LEGAL : 0;
|
|
166
166
|
OF13:
|
|
@@ -173,7 +173,7 @@ fields:
|
|
|
173
173
|
[when="HPM_COUNTER_EN[13] == false"]
|
|
174
174
|
This field is read-only zero because the counter is not enabled.
|
|
175
175
|
type(): |
|
|
176
|
-
return HPM_COUNTER_EN[13] ? CsrFieldType::
|
|
176
|
+
return HPM_COUNTER_EN[13] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
177
177
|
reset_value(): |
|
|
178
178
|
return HPM_COUNTER_EN[13] ? UNDEFINED_LEGAL : 0;
|
|
179
179
|
OF14:
|
|
@@ -186,7 +186,7 @@ fields:
|
|
|
186
186
|
[when="HPM_COUNTER_EN[14] == false"]
|
|
187
187
|
This field is read-only zero because the counter is not enabled.
|
|
188
188
|
type(): |
|
|
189
|
-
return HPM_COUNTER_EN[14] ? CsrFieldType::
|
|
189
|
+
return HPM_COUNTER_EN[14] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
190
190
|
reset_value(): |
|
|
191
191
|
return HPM_COUNTER_EN[14] ? UNDEFINED_LEGAL : 0;
|
|
192
192
|
OF15:
|
|
@@ -199,7 +199,7 @@ fields:
|
|
|
199
199
|
[when="HPM_COUNTER_EN[15] == false"]
|
|
200
200
|
This field is read-only zero because the counter is not enabled.
|
|
201
201
|
type(): |
|
|
202
|
-
return HPM_COUNTER_EN[15] ? CsrFieldType::
|
|
202
|
+
return HPM_COUNTER_EN[15] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
203
203
|
reset_value(): |
|
|
204
204
|
return HPM_COUNTER_EN[15] ? UNDEFINED_LEGAL : 0;
|
|
205
205
|
OF16:
|
|
@@ -212,7 +212,7 @@ fields:
|
|
|
212
212
|
[when="HPM_COUNTER_EN[16] == false"]
|
|
213
213
|
This field is read-only zero because the counter is not enabled.
|
|
214
214
|
type(): |
|
|
215
|
-
return HPM_COUNTER_EN[16] ? CsrFieldType::
|
|
215
|
+
return HPM_COUNTER_EN[16] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
216
216
|
reset_value(): |
|
|
217
217
|
return HPM_COUNTER_EN[16] ? UNDEFINED_LEGAL : 0;
|
|
218
218
|
OF17:
|
|
@@ -225,7 +225,7 @@ fields:
|
|
|
225
225
|
[when="HPM_COUNTER_EN[17] == false"]
|
|
226
226
|
This field is read-only zero because the counter is not enabled.
|
|
227
227
|
type(): |
|
|
228
|
-
return HPM_COUNTER_EN[17] ? CsrFieldType::
|
|
228
|
+
return HPM_COUNTER_EN[17] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
229
229
|
reset_value(): |
|
|
230
230
|
return HPM_COUNTER_EN[17] ? UNDEFINED_LEGAL : 0;
|
|
231
231
|
OF18:
|
|
@@ -238,7 +238,7 @@ fields:
|
|
|
238
238
|
[when="HPM_COUNTER_EN[18] == false"]
|
|
239
239
|
This field is read-only zero because the counter is not enabled.
|
|
240
240
|
type(): |
|
|
241
|
-
return HPM_COUNTER_EN[18] ? CsrFieldType::
|
|
241
|
+
return HPM_COUNTER_EN[18] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
242
242
|
reset_value(): |
|
|
243
243
|
return HPM_COUNTER_EN[18] ? UNDEFINED_LEGAL : 0;
|
|
244
244
|
OF19:
|
|
@@ -251,7 +251,7 @@ fields:
|
|
|
251
251
|
[when="HPM_COUNTER_EN[19] == false"]
|
|
252
252
|
This field is read-only zero because the counter is not enabled.
|
|
253
253
|
type(): |
|
|
254
|
-
return HPM_COUNTER_EN[19] ? CsrFieldType::
|
|
254
|
+
return HPM_COUNTER_EN[19] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
255
255
|
reset_value(): |
|
|
256
256
|
return HPM_COUNTER_EN[19] ? UNDEFINED_LEGAL : 0;
|
|
257
257
|
OF20:
|
|
@@ -264,7 +264,7 @@ fields:
|
|
|
264
264
|
[when="HPM_COUNTER_EN[20] == false"]
|
|
265
265
|
This field is read-only zero because the counter is not enabled.
|
|
266
266
|
type(): |
|
|
267
|
-
return HPM_COUNTER_EN[20] ? CsrFieldType::
|
|
267
|
+
return HPM_COUNTER_EN[20] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
268
268
|
reset_value(): |
|
|
269
269
|
return HPM_COUNTER_EN[20] ? UNDEFINED_LEGAL : 0;
|
|
270
270
|
OF21:
|
|
@@ -277,7 +277,7 @@ fields:
|
|
|
277
277
|
[when="HPM_COUNTER_EN[21] == false"]
|
|
278
278
|
This field is read-only zero because the counter is not enabled.
|
|
279
279
|
type(): |
|
|
280
|
-
return HPM_COUNTER_EN[21] ? CsrFieldType::
|
|
280
|
+
return HPM_COUNTER_EN[21] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
281
281
|
reset_value(): |
|
|
282
282
|
return HPM_COUNTER_EN[21] ? UNDEFINED_LEGAL : 0;
|
|
283
283
|
OF22:
|
|
@@ -290,7 +290,7 @@ fields:
|
|
|
290
290
|
[when="HPM_COUNTER_EN[22] == false"]
|
|
291
291
|
This field is read-only zero because the counter is not enabled.
|
|
292
292
|
type(): |
|
|
293
|
-
return HPM_COUNTER_EN[22] ? CsrFieldType::
|
|
293
|
+
return HPM_COUNTER_EN[22] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
294
294
|
reset_value(): |
|
|
295
295
|
return HPM_COUNTER_EN[22] ? UNDEFINED_LEGAL : 0;
|
|
296
296
|
OF23:
|
|
@@ -303,7 +303,7 @@ fields:
|
|
|
303
303
|
[when="HPM_COUNTER_EN[23] == false"]
|
|
304
304
|
This field is read-only zero because the counter is not enabled.
|
|
305
305
|
type(): |
|
|
306
|
-
return HPM_COUNTER_EN[23] ? CsrFieldType::
|
|
306
|
+
return HPM_COUNTER_EN[23] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
307
307
|
reset_value(): |
|
|
308
308
|
return HPM_COUNTER_EN[23] ? UNDEFINED_LEGAL : 0;
|
|
309
309
|
OF24:
|
|
@@ -316,7 +316,7 @@ fields:
|
|
|
316
316
|
[when="HPM_COUNTER_EN[24] == false"]
|
|
317
317
|
This field is read-only zero because the counter is not enabled.
|
|
318
318
|
type(): |
|
|
319
|
-
return HPM_COUNTER_EN[24] ? CsrFieldType::
|
|
319
|
+
return HPM_COUNTER_EN[24] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
320
320
|
reset_value(): |
|
|
321
321
|
return HPM_COUNTER_EN[24] ? UNDEFINED_LEGAL : 0;
|
|
322
322
|
OF25:
|
|
@@ -329,7 +329,7 @@ fields:
|
|
|
329
329
|
[when="HPM_COUNTER_EN[25] == false"]
|
|
330
330
|
This field is read-only zero because the counter is not enabled.
|
|
331
331
|
type(): |
|
|
332
|
-
return HPM_COUNTER_EN[25] ? CsrFieldType::
|
|
332
|
+
return HPM_COUNTER_EN[25] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
333
333
|
reset_value(): |
|
|
334
334
|
return HPM_COUNTER_EN[25] ? UNDEFINED_LEGAL : 0;
|
|
335
335
|
OF26:
|
|
@@ -342,7 +342,7 @@ fields:
|
|
|
342
342
|
[when="HPM_COUNTER_EN[26] == false"]
|
|
343
343
|
This field is read-only zero because the counter is not enabled.
|
|
344
344
|
type(): |
|
|
345
|
-
return HPM_COUNTER_EN[26] ? CsrFieldType::
|
|
345
|
+
return HPM_COUNTER_EN[26] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
346
346
|
reset_value(): |
|
|
347
347
|
return HPM_COUNTER_EN[26] ? UNDEFINED_LEGAL : 0;
|
|
348
348
|
OF27:
|
|
@@ -355,7 +355,7 @@ fields:
|
|
|
355
355
|
[when="HPM_COUNTER_EN[27] == false"]
|
|
356
356
|
This field is read-only zero because the counter is not enabled.
|
|
357
357
|
type(): |
|
|
358
|
-
return HPM_COUNTER_EN[27] ? CsrFieldType::
|
|
358
|
+
return HPM_COUNTER_EN[27] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
359
359
|
reset_value(): |
|
|
360
360
|
return HPM_COUNTER_EN[27] ? UNDEFINED_LEGAL : 0;
|
|
361
361
|
OF28:
|
|
@@ -368,7 +368,7 @@ fields:
|
|
|
368
368
|
[when="HPM_COUNTER_EN[28] == false"]
|
|
369
369
|
This field is read-only zero because the counter is not enabled.
|
|
370
370
|
type(): |
|
|
371
|
-
return HPM_COUNTER_EN[28] ? CsrFieldType::
|
|
371
|
+
return HPM_COUNTER_EN[28] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
372
372
|
reset_value(): |
|
|
373
373
|
return HPM_COUNTER_EN[28] ? UNDEFINED_LEGAL : 0;
|
|
374
374
|
OF29:
|
|
@@ -381,7 +381,7 @@ fields:
|
|
|
381
381
|
[when="HPM_COUNTER_EN[29] == false"]
|
|
382
382
|
This field is read-only zero because the counter is not enabled.
|
|
383
383
|
type(): |
|
|
384
|
-
return HPM_COUNTER_EN[29] ? CsrFieldType::
|
|
384
|
+
return HPM_COUNTER_EN[29] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
385
385
|
reset_value(): |
|
|
386
386
|
return HPM_COUNTER_EN[29] ? UNDEFINED_LEGAL : 0;
|
|
387
387
|
OF30:
|
|
@@ -394,7 +394,7 @@ fields:
|
|
|
394
394
|
[when="HPM_COUNTER_EN[30] == false"]
|
|
395
395
|
This field is read-only zero because the counter is not enabled.
|
|
396
396
|
type(): |
|
|
397
|
-
return HPM_COUNTER_EN[30] ? CsrFieldType::
|
|
397
|
+
return HPM_COUNTER_EN[30] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
398
398
|
reset_value(): |
|
|
399
399
|
return HPM_COUNTER_EN[30] ? UNDEFINED_LEGAL : 0;
|
|
400
400
|
OF31:
|
|
@@ -407,7 +407,7 @@ fields:
|
|
|
407
407
|
[when="HPM_COUNTER_EN[31] == false"]
|
|
408
408
|
This field is read-only zero because the counter is not enabled.
|
|
409
409
|
type(): |
|
|
410
|
-
return HPM_COUNTER_EN[31] ? CsrFieldType::
|
|
410
|
+
return HPM_COUNTER_EN[31] ? CsrFieldType::ROH : CsrFieldType::RO;
|
|
411
411
|
reset_value(): |
|
|
412
412
|
return HPM_COUNTER_EN[31] ? UNDEFINED_LEGAL : 0;
|
|
413
413
|
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent10.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent10.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10
|
|
87
|
+
* `mhpmevent10.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent10.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.
|
|
90
|
+
* `mhpmevent10.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent10.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.
|
|
94
|
-
* `mhpmevent10.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.
|
|
93
|
+
* `mhpmevent10.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent10.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent10.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|