udb 0.1.13 → 0.1.15
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +20 -24
- data/.data/cfgs/mc100-32-full-example.yaml +2 -2
- data/.data/cfgs/qc_iu.yaml +7 -3
- data/.data/cfgs/rv32-riscv-tests.yaml +8 -5
- data/.data/cfgs/rv32-vector.yaml +8 -5
- data/.data/cfgs/rv64-riscv-tests.yaml +8 -5
- data/.data/cfgs/rv64-vector.yaml +8 -5
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +107 -36
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +52 -69
- data/.data/spec/custom/isa/qc_iu/isa/globals.isa +27 -5
- data/.data/spec/schemas/README.adoc +3 -0
- data/.data/spec/schemas/config_schema.json +1 -1
- data/.data/spec/schemas/mmr_schema.json +3 -3
- data/.data/spec/schemas/schema_defs.json +8 -3
- data/.data/spec/std/isa/csr/H/hcounteren.layout +3 -3
- data/.data/spec/std/isa/csr/H/hcounteren.yaml +31 -31
- data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
- data/.data/spec/std/isa/csr/H/htinst.yaml +3 -3
- data/.data/spec/std/isa/csr/H/htval.yaml +3 -3
- data/.data/spec/std/isa/csr/H/mtinst.yaml +1 -1
- data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
- data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +120 -144
- data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +60 -72
- data/.data/spec/std/isa/csr/I/pmpcfgN.layout +15 -18
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +1 -1
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +1 -1
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +1 -1
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +1 -1
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +1 -1
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +29 -29
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +1 -1
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +1 -1
- data/.data/spec/std/isa/csr/hstatus.yaml +1 -1
- data/.data/spec/std/isa/csr/jvt.yaml +1 -0
- data/.data/spec/std/isa/csr/mcycle.yaml +6 -6
- data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
- data/.data/spec/std/isa/csr/minstret.yaml +3 -3
- data/.data/spec/std/isa/csr/minstreth.yaml +1 -1
- data/.data/spec/std/isa/csr/mstatus.yaml +21 -25
- data/.data/spec/std/isa/csr/mtvec.yaml +16 -57
- data/.data/spec/std/isa/csr/senvcfg.yaml +26 -0
- data/.data/spec/std/isa/csr/sie.yaml +30 -4
- data/.data/spec/std/isa/csr/sip.yaml +16 -2
- data/.data/spec/std/isa/csr/stvec.yaml +11 -12
- data/.data/spec/std/isa/csr/vstval.yaml +1 -1
- data/.data/spec/std/isa/csr/vstvec.yaml +14 -15
- data/.data/spec/std/isa/ext/Q.yaml +1 -1
- data/.data/spec/std/isa/ext/Shlcofideleg.yaml +24 -0
- data/.data/spec/std/isa/ext/Shvstvecd.yaml +2 -2
- data/.data/spec/std/isa/ext/Sspm.yaml +5 -0
- data/.data/spec/std/isa/ext/Sstvecd.yaml +2 -2
- data/.data/spec/std/isa/ext/Sstvecv.yaml +2 -2
- data/.data/spec/std/isa/ext/Supm.yaml +17 -0
- data/.data/spec/std/isa/ext/Zcb.yaml +3 -0
- data/.data/spec/std/isa/ext/Zfbfmin.yaml +3 -5
- data/.data/spec/std/isa/ext/Ziccid.yaml +29 -0
- data/.data/spec/std/isa/ext/Zicfilp.yaml +5 -1
- data/.data/spec/std/isa/ext/Zicfiss.yaml +20 -1
- data/.data/spec/std/isa/ext/Zihpm.yaml +3 -0
- data/.data/spec/std/isa/ext/Zilx.yaml +58 -0
- data/.data/spec/std/isa/ext/Zkt.yaml +33 -1
- data/.data/spec/std/isa/ext/Zvabd.yaml +21 -0
- data/.data/spec/std/isa/ext/Zvbc.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkb.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkg.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkned.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvknha.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvknhb.yaml +4 -2
- data/.data/spec/std/isa/ext/Zvksed.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvksh.yaml +3 -0
- data/.data/spec/std/isa/ext/Zvkt.yaml +3 -0
- data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
- data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
- data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
- data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
- data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
- data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
- data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
- data/.data/spec/std/isa/inst/C/c.add.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.and.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +3 -3
- data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.nop.yaml +13 -2
- data/.data/spec/std/isa/inst/C/c.or.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.slli.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.srai.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.srli.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.sub.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.subw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.xor.yaml +1 -0
- data/.data/spec/std/isa/inst/D/fld.yaml +1 -0
- data/.data/spec/std/isa/inst/D/fsd.yaml +1 -0
- data/.data/spec/std/isa/inst/F/fadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/feq.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fle.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fleq.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/flt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fltq.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/flw.yaml +2 -1
- data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmax.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmin.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsw.yaml +2 -1
- data/.data/spec/std/isa/inst/I/addi.yaml +1 -0
- data/.data/spec/std/isa/inst/I/addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/andi.yaml +1 -0
- data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
- data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sd.yaml +2 -1
- data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
- data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/xori.yaml +1 -0
- data/.data/spec/std/isa/inst/Q/fadd.q.yaml +2 -2
- data/.data/spec/std/isa/inst/Q/fclass.q.yaml +5 -5
- data/.data/spec/std/isa/inst/Q/fleq.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fli.q.yaml +1 -1
- data/.data/spec/std/isa/inst/Q/flq.yaml +1 -0
- data/.data/spec/std/isa/inst/Q/fltq.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fminm.q.yaml +0 -1
- data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml +1 -1
- data/.data/spec/std/isa/inst/Q/fsq.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -0
- data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
- data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
- data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
- data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +1 -0
- data/.data/spec/std/isa/inst/Zcb/c.not.yaml +1 -0
- data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml +2 -7
- data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml +2 -0
- data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml +2 -0
- data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout +7 -0
- data/.data/spec/std/isa/inst/Zfa/fli.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/flh.yaml +5 -2
- data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +3 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +3 -1
- data/.data/spec/std/isa/inst/Zfh/fsh.yaml +4 -1
- data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml +30 -0
- data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml +29 -0
- data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +12 -0
- data/.data/spec/std/isa/inst/Zilx/lxd.yaml +38 -0
- data/.data/spec/std/isa/inst/Zilx/lxh.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxhu.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxsb.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsd.yaml +38 -0
- data/.data/spec/std/isa/inst/Zilx/lxsh.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxshu.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml +39 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml +40 -0
- data/.data/spec/std/isa/inst/Zilx/lxsw.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxswu.yaml +39 -0
- data/.data/spec/std/isa/inst/Zilx/lxw.yaml +35 -0
- data/.data/spec/std/isa/inst/Zilx/lxwu.yaml +39 -0
- data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +67 -0
- data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +67 -0
- data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml +61 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +72 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +72 -0
- data/.data/spec/std/isa/isa/builtin_functions.idl +1 -0
- data/.data/spec/std/isa/isa/fp.idl +42 -18
- data/.data/spec/std/isa/isa/globals.isa +27 -7
- data/.data/spec/std/isa/isa/interrupts.idl +1 -0
- data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml +70 -6
- data/.data/spec/std/isa/param/ELEN.yaml +27 -5
- data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +13 -0
- data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml +13 -3
- data/.data/spec/std/isa/param/HPM_EVENTS.yaml +0 -3
- data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
- data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +8 -0
- data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
- data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +71 -64
- data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +71 -64
- data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
- data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
- data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
- data/.data/spec/std/isa/param/{STVEC_MODE_VECTORED.yaml → PMP_NAPOT_SUPPORTED.yaml} +9 -9
- data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
- data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
- data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +3 -2
- data/.data/spec/std/isa/param/STVEC_BASE_ALIGNMENT_VECTORED.yaml +100 -0
- data/.data/spec/std/isa/param/STVEC_MODES.yaml +31 -0
- data/.data/spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml +1 -1
- data/.data/spec/std/isa/param/SXLEN.yaml +2 -2
- data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml +1 -1
- data/.data/spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
- data/.data/spec/std/isa/param/UXLEN.yaml +1 -1
- data/.data/spec/std/isa/param/VLEN.yaml +16 -7
- data/.data/spec/std/isa/param/VSTVEC_MODES.yaml +31 -0
- data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
- data/lib/udb/ESPRESSO_VERSION +1 -1
- data/lib/udb/Z3_VERSION +1 -1
- data/lib/udb/config.rb +14 -2
- data/lib/udb/doc_link.rb +3 -4
- data/lib/udb/obj/csr.rb +1 -1
- data/lib/udb/obj/csr_field.rb +1 -1
- data/lib/udb/obj/extension.rb +1 -1
- data/lib/udb/obj/instruction.rb +1 -1
- data/lib/udb/obj/non_isa_specification.rb +22 -100
- data/lib/udb/version.rb +1 -1
- data/lib/udb/version_spec.rb +1 -1
- data/lib/udb/z3.rb +31 -9
- metadata +42 -9
- data/.data/spec/std/isa/param/STVEC_MODE_DIRECT.yaml +0 -21
- data/.data/spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml +0 -21
- data/.data/spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml +0 -21
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent30.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent30.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30
|
|
87
|
+
* `mhpmevent30.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent30.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.
|
|
90
|
+
* `mhpmevent30.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent30.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.
|
|
94
|
-
* `mhpmevent30.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.
|
|
93
|
+
* `mhpmevent30.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent30.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent31.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent31.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31
|
|
87
|
+
* `mhpmevent31.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent31.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.
|
|
90
|
+
* `mhpmevent31.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent31.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.
|
|
94
|
-
* `mhpmevent31.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.
|
|
93
|
+
* `mhpmevent31.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent31.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent4.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent4.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4
|
|
87
|
+
* `mhpmevent4.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent4.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.
|
|
90
|
+
* `mhpmevent4.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent4.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.
|
|
94
|
-
* `mhpmevent4.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.
|
|
93
|
+
* `mhpmevent4.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent4.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent5.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent5.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5
|
|
87
|
+
* `mhpmevent5.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent5.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.
|
|
90
|
+
* `mhpmevent5.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent5.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.
|
|
94
|
-
* `mhpmevent5.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.
|
|
93
|
+
* `mhpmevent5.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent5.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent6.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent6.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6
|
|
87
|
+
* `mhpmevent6.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent6.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.
|
|
90
|
+
* `mhpmevent6.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent6.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.
|
|
94
|
-
* `mhpmevent6.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.
|
|
93
|
+
* `mhpmevent6.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent6.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent7.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent7.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7
|
|
87
|
+
* `mhpmevent7.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent7.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.
|
|
90
|
+
* `mhpmevent7.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent7.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.
|
|
94
|
-
* `mhpmevent7.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.
|
|
93
|
+
* `mhpmevent7.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent7.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent8.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent8.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8
|
|
87
|
+
* `mhpmevent8.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent8.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.
|
|
90
|
+
* `mhpmevent8.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent8.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.
|
|
94
|
-
* `mhpmevent8.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.
|
|
93
|
+
* `mhpmevent8.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent8.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -84,14 +84,14 @@ fields:
|
|
|
84
84
|
<%- if ext?(:Sscofpmf) -%>
|
|
85
85
|
* `mhpmevent9.MINH` is set and the current privilege level is M
|
|
86
86
|
<%- if ext?(:S) -%>
|
|
87
|
-
* `mhpmevent9.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9
|
|
87
|
+
* `mhpmevent9.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
88
88
|
<%- end -%>
|
|
89
89
|
<%- if ext?(:U) -%>
|
|
90
|
-
* `mhpmevent9.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.
|
|
90
|
+
* `mhpmevent9.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.UINH`<%- end -%> is set and the current privilege level is U
|
|
91
91
|
<%- end -%>
|
|
92
92
|
<%- if ext?(:H) -%>
|
|
93
|
-
* `mhpmevent9.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.
|
|
94
|
-
* `mhpmevent9.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.
|
|
93
|
+
* `mhpmevent9.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
94
|
+
* `mhpmevent9.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
95
95
|
<%- end -%>
|
|
96
96
|
<%- end -%>
|
|
97
97
|
--
|
|
@@ -82,14 +82,14 @@ fields:
|
|
|
82
82
|
<%%- if ext?(:Sscofpmf) -%>
|
|
83
83
|
* `mhpmevent<%= hpm_num %>.MINH` is set and the current privilege level is M
|
|
84
84
|
<%%- if ext?(:S) -%>
|
|
85
|
-
* `mhpmevent<%= hpm_num %>.SINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num
|
|
85
|
+
* `mhpmevent<%= hpm_num %>.SINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is (H)S
|
|
86
86
|
<%%- end -%>
|
|
87
87
|
<%%- if ext?(:U) -%>
|
|
88
|
-
* `mhpmevent<%= hpm_num %>.UINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.
|
|
88
|
+
* `mhpmevent<%= hpm_num %>.UINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.UINH`<%%- end -%> is set and the current privilege level is U
|
|
89
89
|
<%%- end -%>
|
|
90
90
|
<%%- if ext?(:H) -%>
|
|
91
|
-
* `mhpmevent<%= hpm_num %>.VSINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.
|
|
92
|
-
* `mhpmevent<%= hpm_num %>.VUINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.
|
|
91
|
+
* `mhpmevent<%= hpm_num %>.VSINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.VSINH`<%%- end -%> is set and the current privilege level is VS
|
|
92
|
+
* `mhpmevent<%= hpm_num %>.VUINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.VUINH`<%%- end -%> is set and the current privilege level is VU
|
|
93
93
|
<%%- end -%>
|
|
94
94
|
<%%- end -%>
|
|
95
95
|
--
|
|
@@ -138,7 +138,7 @@ fields:
|
|
|
138
138
|
|
|
139
139
|
Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
|
|
140
140
|
|
|
141
|
-
`mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.
|
|
141
|
+
`mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.VTVM`.
|
|
142
142
|
type: RW
|
|
143
143
|
reset_value: UNDEFINED_LEGAL
|
|
144
144
|
VGEIN:
|
|
@@ -32,7 +32,7 @@ fields:
|
|
|
32
32
|
# since writes to this register may not be hart-local, it must be handled
|
|
33
33
|
# as a special case
|
|
34
34
|
if (xlen() == 32) {
|
|
35
|
-
return sw_write_mcycle({read_mcycle()[63:
|
|
35
|
+
return sw_write_mcycle({read_mcycle()[63:32], csr_value.COUNT[31:0]});
|
|
36
36
|
} else {
|
|
37
37
|
return sw_write_mcycle(csr_value.COUNT);
|
|
38
38
|
}
|
|
@@ -40,7 +40,7 @@ fields:
|
|
|
40
40
|
Cycle counter.
|
|
41
41
|
|
|
42
42
|
<%- if ext?(:Zicntr) -%>
|
|
43
|
-
Aliased as `cycle.
|
|
43
|
+
Aliased as `cycle.COUNT`.
|
|
44
44
|
<%- end -%>
|
|
45
45
|
|
|
46
46
|
Increments every cycle unless:
|
|
@@ -49,14 +49,14 @@ fields:
|
|
|
49
49
|
<%- if ext?(:Smcntrpmf) -%>
|
|
50
50
|
* `mcyclecfg.MINH` is set and the current privilege level is M
|
|
51
51
|
<%- if ext?(:S) -%>
|
|
52
|
-
* `mcyclecfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `
|
|
52
|
+
* `mcyclecfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
53
53
|
<%- end -%>
|
|
54
54
|
<%- if ext?(:U) -%>
|
|
55
|
-
* `mcyclecfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `
|
|
55
|
+
* `mcyclecfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.UINH`<%- end -%> is set and the current privilege level is U
|
|
56
56
|
<%- end -%>
|
|
57
57
|
<%- if ext?(:H) -%>
|
|
58
|
-
* `mcyclecfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `
|
|
59
|
-
* `mcyclecfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `
|
|
58
|
+
* `mcyclecfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
59
|
+
* `mcyclecfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
60
60
|
<%- end -%>
|
|
61
61
|
<%- end -%>
|
|
62
62
|
reset_value: UNDEFINED_LEGAL
|
|
@@ -296,6 +296,26 @@ fields:
|
|
|
296
296
|
name: Zicfiss
|
|
297
297
|
type: RW
|
|
298
298
|
reset_value: UNDEFINED_LEGAL
|
|
299
|
+
LPE:
|
|
300
|
+
location: 2
|
|
301
|
+
description: |
|
|
302
|
+
*Landing Pad Enable*
|
|
303
|
+
|
|
304
|
+
When the LPE field is set to 1 and S-mode is implemented, the Zicfilp
|
|
305
|
+
extension is enabled in S-mode. If the LPE field is set to 1 and S-mode
|
|
306
|
+
is not implemented, the Zicfilp extension is enabled in U-mode. When the
|
|
307
|
+
LPE field is 0, the Zicfilp extension is not enabled in S-mode (or U-mode
|
|
308
|
+
if S-mode is not implemented), and the following rules apply:
|
|
309
|
+
|
|
310
|
+
* The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
|
|
311
|
+
* The `LPAD` instruction operates as a no-op.
|
|
312
|
+
|
|
313
|
+
When `menvcfg.LPE` is 0, `henvcfg.LPE` and `senvcfg.LPE` are read-only zero.
|
|
314
|
+
definedBy:
|
|
315
|
+
extension:
|
|
316
|
+
name: Zicfilp
|
|
317
|
+
type: RW
|
|
318
|
+
reset_value: UNDEFINED_LEGAL
|
|
299
319
|
FIOM:
|
|
300
320
|
location: 0
|
|
301
321
|
description: |
|
|
@@ -37,11 +37,11 @@ fields:
|
|
|
37
37
|
* `minstretcfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is (H)S
|
|
38
38
|
<%- end -%>
|
|
39
39
|
<%- if ext?(:U) -%>
|
|
40
|
-
* `minstretcfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.
|
|
40
|
+
* `minstretcfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.UINH`<%- end -%> is set and the current privilege level is U
|
|
41
41
|
<%- end -%>
|
|
42
42
|
<%- if ext?(:H) -%>
|
|
43
|
-
* `minstretcfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.
|
|
44
|
-
* `minstretcfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.
|
|
43
|
+
* `minstretcfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.VSINH`<%- end -%> is set and the current privilege level is VS
|
|
44
|
+
* `minstretcfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.VUINH`<%- end -%> is set and the current privilege level is VU
|
|
45
45
|
<%- end -%>
|
|
46
46
|
<%- end -%>
|
|
47
47
|
|
|
@@ -28,7 +28,7 @@ fields:
|
|
|
28
28
|
reset_value: UNDEFINED_LEGAL
|
|
29
29
|
affectedBy: [Zicntr, Smcntrpmf, Smcdeleg, Ssccfg]
|
|
30
30
|
sw_write(csr_value): |
|
|
31
|
-
CSR[
|
|
31
|
+
CSR[minstret].COUNT = {csr_value.COUNT[31:0], CSR[minstret].COUNT[31:0]};
|
|
32
32
|
return csr_value.COUNT;
|
|
33
33
|
definedBy:
|
|
34
34
|
allOf:
|
|
@@ -111,7 +111,11 @@ fields:
|
|
|
111
111
|
long_name: Guest Virtual Address
|
|
112
112
|
description: |
|
|
113
113
|
When a trap is taken and a guest virtual address is written into mtval, GVA is set.
|
|
114
|
-
|
|
114
|
+
GVA is written by the implementation whenever a trap is taken into
|
|
115
|
+
HS mode. For any trap (breakpoint, address misaligned, access fault,
|
|
116
|
+
page fault, or guest-page fault) that writes a guest virtual address to
|
|
117
|
+
`stval`, GVA is set to 1. For any other trap into HS-mode,
|
|
118
|
+
GVA is set to 0.
|
|
115
119
|
type: RW-H
|
|
116
120
|
reset_value: 0
|
|
117
121
|
definedBy:
|
|
@@ -328,6 +332,8 @@ fields:
|
|
|
328
332
|
type(): |
|
|
329
333
|
if (CSR[misa].S == 1'b0) {
|
|
330
334
|
return CsrFieldType::RO;
|
|
335
|
+
} else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
|
|
336
|
+
return CsrFieldType::RO;
|
|
331
337
|
} else {
|
|
332
338
|
return CsrFieldType::RW;
|
|
333
339
|
}
|
|
@@ -337,18 +343,18 @@ fields:
|
|
|
337
343
|
reset_value(): |
|
|
338
344
|
if (CSR[misa].S == 1'b0) {
|
|
339
345
|
return 0;
|
|
340
|
-
} else if (
|
|
341
|
-
return UNDEFINED_LEGAL;
|
|
342
|
-
} else {
|
|
346
|
+
} else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
|
|
343
347
|
return 0;
|
|
348
|
+
} else {
|
|
349
|
+
return UNDEFINED_LEGAL;
|
|
344
350
|
}
|
|
345
351
|
sw_write(csr_value): |
|
|
346
352
|
if (CSR[misa].S == 1'b0) {
|
|
347
353
|
return 0;
|
|
348
|
-
} else if (
|
|
349
|
-
return csr_value.TVM;
|
|
350
|
-
} else {
|
|
354
|
+
} else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
|
|
351
355
|
return 0;
|
|
356
|
+
} else {
|
|
357
|
+
return csr_value.TVM;
|
|
352
358
|
}
|
|
353
359
|
MXR:
|
|
354
360
|
location: 19
|
|
@@ -434,6 +440,10 @@ fields:
|
|
|
434
440
|
- name: F
|
|
435
441
|
- name: S
|
|
436
442
|
reset_value(): |
|
|
443
|
+
if (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
|
|
444
|
+
# must be read-only-0
|
|
445
|
+
return 0;
|
|
446
|
+
}
|
|
437
447
|
return $array_size(MSTATUS_FS_LEGAL_VALUES) == 1 ? MSTATUS_FS_LEGAL_VALUES[0] : UNDEFINED_LEGAL;
|
|
438
448
|
sw_write(csr_value): |
|
|
439
449
|
if (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
|
|
@@ -497,31 +507,17 @@ fields:
|
|
|
497
507
|
return $array_size(MSTATUS_VS_LEGAL_VALUES) == 1 ? CsrFieldType::RO : CsrFieldType::RW;
|
|
498
508
|
}
|
|
499
509
|
reset_value(): |
|
|
500
|
-
if (CSR[misa].V == 1'
|
|
501
|
-
return UNDEFINED_LEGAL;
|
|
502
|
-
} else if ((CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0)) {
|
|
510
|
+
if ((!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) || (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0))) {
|
|
503
511
|
# must be read-only-0
|
|
504
512
|
return 0;
|
|
505
|
-
} else {
|
|
506
|
-
# there will be no hardware update in this case because we know the V extension isn't implemented
|
|
507
|
-
if ($array_size(MSTATUS_VS_LEGAL_VALUES) == 0) {
|
|
508
|
-
return 0;
|
|
509
|
-
} else if ($array_size(MSTATUS_VS_LEGAL_VALUES) == 1) {
|
|
510
|
-
return MSTATUS_VS_LEGAL_VALUES[0];
|
|
511
|
-
} else {
|
|
512
|
-
return UNDEFINED_LEGAL;
|
|
513
|
-
}
|
|
514
513
|
}
|
|
514
|
+
return $array_size(MSTATUS_VS_LEGAL_VALUES) == 1 ? MSTATUS_VS_LEGAL_VALUES[0] : UNDEFINED_LEGAL;
|
|
515
515
|
sw_write(csr_value): |
|
|
516
|
-
if (implemented?(ExtensionName::V) && CSR[misa].V == 1'
|
|
517
|
-
return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
|
|
518
|
-
} else if (!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) {
|
|
516
|
+
if ((!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) || (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0))) {
|
|
519
517
|
# must be read-only-0
|
|
520
518
|
return 0;
|
|
521
|
-
} else {
|
|
522
|
-
# there will be no hardware update in this case because we know the V extension isn't implemented
|
|
523
|
-
return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
|
|
524
519
|
}
|
|
520
|
+
return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
|
|
525
521
|
SPP:
|
|
526
522
|
location: 8
|
|
527
523
|
long_name: S-mode Previous Privilege
|
|
@@ -30,37 +30,15 @@ fields:
|
|
|
30
30
|
# implementations may put further constraints on BASE when MODE != Direct
|
|
31
31
|
# If that is the case, stvec should have an override for the implementation
|
|
32
32
|
|
|
33
|
-
if (csr_value.MODE
|
|
34
|
-
|
|
35
|
-
return csr_value.BASE;
|
|
36
|
-
}
|
|
37
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
38
|
-
return CSR[mtvec].BASE;
|
|
39
|
-
}
|
|
40
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
41
|
-
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
42
|
-
}
|
|
43
|
-
unreachable();
|
|
44
|
-
} else if (csr_value.MODE == 1) {
|
|
45
|
-
if ($array_includes?(MTVEC_MODES, 1)) {
|
|
46
|
-
return csr_value.BASE;
|
|
47
|
-
}
|
|
48
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
49
|
-
return CSR[mtvec].BASE;
|
|
50
|
-
}
|
|
51
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
52
|
-
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
53
|
-
}
|
|
54
|
-
unreachable();
|
|
55
|
-
} else {
|
|
56
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
57
|
-
return CSR[mtvec].BASE;
|
|
58
|
-
}
|
|
59
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
60
|
-
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
61
|
-
}
|
|
62
|
-
unreachable();
|
|
33
|
+
if ($array_includes?(MTVEC_MODES, csr_value.MODE)) {
|
|
34
|
+
return csr_value.BASE;
|
|
63
35
|
}
|
|
36
|
+
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
37
|
+
return CSR[mtvec].BASE;
|
|
38
|
+
} else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
39
|
+
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
40
|
+
}
|
|
41
|
+
unreachable();
|
|
64
42
|
reset_value: 0
|
|
65
43
|
MODE:
|
|
66
44
|
location: 1-0
|
|
@@ -71,7 +49,7 @@ fields:
|
|
|
71
49
|
|
|
72
50
|
When Direct, all synchronous exceptions and asynchronous interrupts jump to (`mtvec.BASE` << 2).
|
|
73
51
|
|
|
74
|
-
When Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.
|
|
52
|
+
When Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.CODE`*4) while synchronous exceptions continue to jump to (`mtvec.BASE` << 2).
|
|
75
53
|
type(): |
|
|
76
54
|
if (MTVEC_ACCESS == "ro") {
|
|
77
55
|
return CsrFieldType::RO;
|
|
@@ -79,32 +57,13 @@ fields:
|
|
|
79
57
|
|
|
80
58
|
return ($array_size(MTVEC_MODES) == 1) ? CsrFieldType::RO : CsrFieldType::RWR;
|
|
81
59
|
sw_write(csr_value): |
|
|
82
|
-
if (csr_value.MODE
|
|
83
|
-
|
|
84
|
-
|
|
85
|
-
|
|
86
|
-
|
|
87
|
-
|
|
88
|
-
|
|
89
|
-
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
90
|
-
}
|
|
91
|
-
}
|
|
92
|
-
} else if (csr_value.MODE == 1) {
|
|
93
|
-
if ($array_includes?(MTVEC_MODES, 1)) {
|
|
94
|
-
return csr_value.MODE;
|
|
95
|
-
} else {
|
|
96
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
97
|
-
return CSR[mtvec].MODE;
|
|
98
|
-
} else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
99
|
-
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
100
|
-
}
|
|
101
|
-
}
|
|
102
|
-
} else {
|
|
103
|
-
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
104
|
-
return CSR[mtvec].MODE;
|
|
105
|
-
} else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
106
|
-
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
107
|
-
}
|
|
60
|
+
if ($array_includes?(MTVEC_MODES, csr_value.MODE)) {
|
|
61
|
+
return csr_value.MODE;
|
|
62
|
+
}
|
|
63
|
+
if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
|
|
64
|
+
return CSR[mtvec].MODE;
|
|
65
|
+
} else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
|
|
66
|
+
return UNDEFINED_LEGAL_DETERMINISTIC;
|
|
108
67
|
}
|
|
109
68
|
unreachable();
|
|
110
69
|
reset_value(): |
|
|
@@ -165,6 +165,28 @@ fields:
|
|
|
165
165
|
return 0;
|
|
166
166
|
}
|
|
167
167
|
return csr_value.SSE;
|
|
168
|
+
LPE:
|
|
169
|
+
location: 2
|
|
170
|
+
description: |
|
|
171
|
+
*Landing Pad Enable*
|
|
172
|
+
|
|
173
|
+
When the LPE field is set to 1 and `menvcfg.LPE` is 1, the Zicfilp extension
|
|
174
|
+
is enabled in U/VU-mode. Read-only zero when `menvcfg.LPE` is 0. When the LPE
|
|
175
|
+
field is 0, the Zicfilp extension is not enabled in U/VU-mode and the following
|
|
176
|
+
rules apply:
|
|
177
|
+
|
|
178
|
+
* The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
|
|
179
|
+
* The `LPAD` instruction operates as a no-op.
|
|
180
|
+
definedBy:
|
|
181
|
+
extension:
|
|
182
|
+
name: Zicfilp
|
|
183
|
+
type: RW
|
|
184
|
+
reset_value: UNDEFINED_LEGAL
|
|
185
|
+
sw_write(csr_value): |
|
|
186
|
+
if (CSR[menvcfg].LPE == 0) {
|
|
187
|
+
return 0;
|
|
188
|
+
}
|
|
189
|
+
return csr_value.LPE;
|
|
168
190
|
FIOM:
|
|
169
191
|
location: 0
|
|
170
192
|
description: |
|
|
@@ -202,4 +224,8 @@ sw_read(): |
|
|
|
202
224
|
# senvcfg.SSE must read-as-zero
|
|
203
225
|
value = value & ~(1 `<< 3);
|
|
204
226
|
}
|
|
227
|
+
if (implemented?(ExtensionName::Zicfilp) && CSR[menvcfg].LPE == 0) {
|
|
228
|
+
# senvcfg.LPE must read-as-zero when menvcfg.LPE is 0
|
|
229
|
+
value = value & ~(1 `<< 2);
|
|
230
|
+
}
|
|
205
231
|
return value;
|