udb 0.1.13 → 0.1.15

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (429) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +20 -24
  3. data/.data/cfgs/mc100-32-full-example.yaml +2 -2
  4. data/.data/cfgs/qc_iu.yaml +7 -3
  5. data/.data/cfgs/rv32-riscv-tests.yaml +8 -5
  6. data/.data/cfgs/rv32-vector.yaml +8 -5
  7. data/.data/cfgs/rv64-riscv-tests.yaml +8 -5
  8. data/.data/cfgs/rv64-vector.yaml +8 -5
  9. data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +107 -36
  10. data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +52 -69
  11. data/.data/spec/custom/isa/qc_iu/isa/globals.isa +27 -5
  12. data/.data/spec/schemas/README.adoc +3 -0
  13. data/.data/spec/schemas/config_schema.json +1 -1
  14. data/.data/spec/schemas/mmr_schema.json +3 -3
  15. data/.data/spec/schemas/schema_defs.json +8 -3
  16. data/.data/spec/std/isa/csr/H/hcounteren.layout +3 -3
  17. data/.data/spec/std/isa/csr/H/hcounteren.yaml +31 -31
  18. data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
  19. data/.data/spec/std/isa/csr/H/htinst.yaml +3 -3
  20. data/.data/spec/std/isa/csr/H/htval.yaml +3 -3
  21. data/.data/spec/std/isa/csr/H/mtinst.yaml +1 -1
  22. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
  23. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
  24. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
  25. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
  26. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
  27. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
  28. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
  29. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
  30. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
  31. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
  32. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
  33. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
  34. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
  35. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
  36. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
  37. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
  38. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
  39. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
  40. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
  41. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
  42. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
  43. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
  44. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
  45. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
  46. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
  47. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
  48. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
  49. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
  50. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
  51. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
  52. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
  53. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
  54. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
  55. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
  56. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
  57. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
  58. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
  59. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
  60. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
  61. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
  62. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
  63. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
  64. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
  65. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
  66. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
  67. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
  68. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
  69. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
  70. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
  71. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
  72. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
  73. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
  74. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
  75. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
  76. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
  77. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
  78. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
  79. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
  80. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
  81. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
  82. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
  83. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
  84. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
  85. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
  86. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
  87. data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +120 -144
  88. data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +60 -72
  89. data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +120 -144
  90. data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +60 -72
  91. data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +120 -144
  92. data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +60 -72
  93. data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +120 -144
  94. data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +60 -72
  95. data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +120 -144
  96. data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +60 -72
  97. data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +120 -144
  98. data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +60 -72
  99. data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +120 -144
  100. data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +60 -72
  101. data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +120 -144
  102. data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +60 -72
  103. data/.data/spec/std/isa/csr/I/pmpcfgN.layout +15 -18
  104. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +1 -1
  105. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +1 -1
  106. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +1 -1
  107. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +1 -1
  108. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +1 -1
  109. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +29 -29
  110. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -4
  111. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +1 -1
  112. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -4
  113. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +1 -1
  114. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -4
  115. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +1 -1
  116. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -4
  117. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +1 -1
  118. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -4
  119. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +1 -1
  120. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -4
  121. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +1 -1
  122. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -4
  123. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +1 -1
  124. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -4
  125. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +1 -1
  126. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -4
  127. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +1 -1
  128. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -4
  129. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +1 -1
  130. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -4
  131. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +1 -1
  132. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -4
  133. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +1 -1
  134. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -4
  135. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +1 -1
  136. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -4
  137. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +1 -1
  138. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -4
  139. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +1 -1
  140. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -4
  141. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +1 -1
  142. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -4
  143. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +1 -1
  144. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -4
  145. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +1 -1
  146. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -4
  147. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +1 -1
  148. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -4
  149. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +1 -1
  150. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -4
  151. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -4
  152. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +1 -1
  153. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -4
  154. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +1 -1
  155. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +1 -1
  156. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -4
  157. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +1 -1
  158. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -4
  159. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +1 -1
  160. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -4
  161. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +1 -1
  162. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -4
  163. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +1 -1
  164. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -4
  165. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +1 -1
  166. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -4
  167. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +1 -1
  168. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -4
  169. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +1 -1
  170. data/.data/spec/std/isa/csr/hstatus.yaml +1 -1
  171. data/.data/spec/std/isa/csr/jvt.yaml +1 -0
  172. data/.data/spec/std/isa/csr/mcycle.yaml +6 -6
  173. data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
  174. data/.data/spec/std/isa/csr/minstret.yaml +3 -3
  175. data/.data/spec/std/isa/csr/minstreth.yaml +1 -1
  176. data/.data/spec/std/isa/csr/mstatus.yaml +21 -25
  177. data/.data/spec/std/isa/csr/mtvec.yaml +16 -57
  178. data/.data/spec/std/isa/csr/senvcfg.yaml +26 -0
  179. data/.data/spec/std/isa/csr/sie.yaml +30 -4
  180. data/.data/spec/std/isa/csr/sip.yaml +16 -2
  181. data/.data/spec/std/isa/csr/stvec.yaml +11 -12
  182. data/.data/spec/std/isa/csr/vstval.yaml +1 -1
  183. data/.data/spec/std/isa/csr/vstvec.yaml +14 -15
  184. data/.data/spec/std/isa/ext/Q.yaml +1 -1
  185. data/.data/spec/std/isa/ext/Shlcofideleg.yaml +24 -0
  186. data/.data/spec/std/isa/ext/Shvstvecd.yaml +2 -2
  187. data/.data/spec/std/isa/ext/Sspm.yaml +5 -0
  188. data/.data/spec/std/isa/ext/Sstvecd.yaml +2 -2
  189. data/.data/spec/std/isa/ext/Sstvecv.yaml +2 -2
  190. data/.data/spec/std/isa/ext/Supm.yaml +17 -0
  191. data/.data/spec/std/isa/ext/Zcb.yaml +3 -0
  192. data/.data/spec/std/isa/ext/Zfbfmin.yaml +3 -5
  193. data/.data/spec/std/isa/ext/Ziccid.yaml +29 -0
  194. data/.data/spec/std/isa/ext/Zicfilp.yaml +5 -1
  195. data/.data/spec/std/isa/ext/Zicfiss.yaml +20 -1
  196. data/.data/spec/std/isa/ext/Zihpm.yaml +3 -0
  197. data/.data/spec/std/isa/ext/Zilx.yaml +58 -0
  198. data/.data/spec/std/isa/ext/Zkt.yaml +33 -1
  199. data/.data/spec/std/isa/ext/Zvabd.yaml +21 -0
  200. data/.data/spec/std/isa/ext/Zvbc.yaml +3 -0
  201. data/.data/spec/std/isa/ext/Zvkb.yaml +3 -0
  202. data/.data/spec/std/isa/ext/Zvkg.yaml +3 -0
  203. data/.data/spec/std/isa/ext/Zvkned.yaml +3 -0
  204. data/.data/spec/std/isa/ext/Zvknha.yaml +3 -0
  205. data/.data/spec/std/isa/ext/Zvknhb.yaml +4 -2
  206. data/.data/spec/std/isa/ext/Zvksed.yaml +3 -0
  207. data/.data/spec/std/isa/ext/Zvksh.yaml +3 -0
  208. data/.data/spec/std/isa/ext/Zvkt.yaml +3 -0
  209. data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
  210. data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
  211. data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
  212. data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
  213. data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
  214. data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
  215. data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
  216. data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
  217. data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
  218. data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
  219. data/.data/spec/std/isa/inst/C/c.add.yaml +1 -0
  220. data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
  221. data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
  222. data/.data/spec/std/isa/inst/C/c.addw.yaml +1 -0
  223. data/.data/spec/std/isa/inst/C/c.and.yaml +1 -0
  224. data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
  225. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +3 -3
  226. data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
  227. data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -0
  228. data/.data/spec/std/isa/inst/C/c.nop.yaml +13 -2
  229. data/.data/spec/std/isa/inst/C/c.or.yaml +1 -0
  230. data/.data/spec/std/isa/inst/C/c.slli.yaml +1 -0
  231. data/.data/spec/std/isa/inst/C/c.srai.yaml +1 -0
  232. data/.data/spec/std/isa/inst/C/c.srli.yaml +1 -0
  233. data/.data/spec/std/isa/inst/C/c.sub.yaml +1 -0
  234. data/.data/spec/std/isa/inst/C/c.subw.yaml +1 -0
  235. data/.data/spec/std/isa/inst/C/c.xor.yaml +1 -0
  236. data/.data/spec/std/isa/inst/D/fld.yaml +1 -0
  237. data/.data/spec/std/isa/inst/D/fsd.yaml +1 -0
  238. data/.data/spec/std/isa/inst/F/fadd.s.yaml +1 -1
  239. data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
  240. data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
  241. data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
  242. data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
  243. data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
  244. data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
  245. data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
  246. data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
  247. data/.data/spec/std/isa/inst/F/feq.s.yaml +1 -1
  248. data/.data/spec/std/isa/inst/F/fle.s.yaml +1 -1
  249. data/.data/spec/std/isa/inst/F/fleq.s.yaml +1 -1
  250. data/.data/spec/std/isa/inst/F/flt.s.yaml +1 -1
  251. data/.data/spec/std/isa/inst/F/fltq.s.yaml +1 -1
  252. data/.data/spec/std/isa/inst/F/flw.yaml +2 -1
  253. data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
  254. data/.data/spec/std/isa/inst/F/fmax.s.yaml +1 -1
  255. data/.data/spec/std/isa/inst/F/fmin.s.yaml +1 -1
  256. data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
  257. data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
  258. data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +1 -1
  259. data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
  260. data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +1 -1
  261. data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
  262. data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
  263. data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
  264. data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
  265. data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
  266. data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
  267. data/.data/spec/std/isa/inst/F/fsw.yaml +2 -1
  268. data/.data/spec/std/isa/inst/I/addi.yaml +1 -0
  269. data/.data/spec/std/isa/inst/I/addiw.yaml +1 -0
  270. data/.data/spec/std/isa/inst/I/andi.yaml +1 -0
  271. data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
  272. data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
  273. data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
  274. data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
  275. data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
  276. data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
  277. data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
  278. data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
  279. data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
  280. data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
  281. data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
  282. data/.data/spec/std/isa/inst/I/sd.yaml +2 -1
  283. data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
  284. data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
  285. data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -0
  286. data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
  287. data/.data/spec/std/isa/inst/I/xori.yaml +1 -0
  288. data/.data/spec/std/isa/inst/Q/fadd.q.yaml +2 -2
  289. data/.data/spec/std/isa/inst/Q/fclass.q.yaml +5 -5
  290. data/.data/spec/std/isa/inst/Q/fleq.q.yaml +0 -1
  291. data/.data/spec/std/isa/inst/Q/fli.q.yaml +1 -1
  292. data/.data/spec/std/isa/inst/Q/flq.yaml +1 -0
  293. data/.data/spec/std/isa/inst/Q/fltq.q.yaml +0 -1
  294. data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml +0 -1
  295. data/.data/spec/std/isa/inst/Q/fminm.q.yaml +0 -1
  296. data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml +1 -1
  297. data/.data/spec/std/isa/inst/Q/fsq.yaml +1 -0
  298. data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
  299. data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
  300. data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
  301. data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -0
  302. data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
  303. data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
  304. data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
  305. data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
  306. data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +1 -0
  307. data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +1 -0
  308. data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +1 -0
  309. data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +1 -0
  310. data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
  311. data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +1 -0
  312. data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
  313. data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
  314. data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
  315. data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
  316. data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -0
  317. data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
  318. data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
  319. data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
  320. data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
  321. data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
  322. data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
  323. data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
  324. data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
  325. data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +1 -0
  326. data/.data/spec/std/isa/inst/Zcb/c.not.yaml +1 -0
  327. data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml +2 -7
  328. data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +1 -1
  329. data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml +2 -0
  330. data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml +2 -0
  331. data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout +7 -0
  332. data/.data/spec/std/isa/inst/Zfa/fli.s.yaml +1 -1
  333. data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml +1 -1
  334. data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml +1 -1
  335. data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
  336. data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml +1 -1
  337. data/.data/spec/std/isa/inst/Zfh/flh.yaml +5 -2
  338. data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +3 -1
  339. data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +3 -1
  340. data/.data/spec/std/isa/inst/Zfh/fsh.yaml +4 -1
  341. data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
  342. data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
  343. data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
  344. data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml +30 -0
  345. data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml +29 -0
  346. data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml +1 -1
  347. data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml +1 -1
  348. data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +12 -0
  349. data/.data/spec/std/isa/inst/Zilx/lxd.yaml +38 -0
  350. data/.data/spec/std/isa/inst/Zilx/lxh.yaml +35 -0
  351. data/.data/spec/std/isa/inst/Zilx/lxhu.yaml +35 -0
  352. data/.data/spec/std/isa/inst/Zilx/lxsb.yaml +40 -0
  353. data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml +40 -0
  354. data/.data/spec/std/isa/inst/Zilx/lxsd.yaml +38 -0
  355. data/.data/spec/std/isa/inst/Zilx/lxsh.yaml +35 -0
  356. data/.data/spec/std/isa/inst/Zilx/lxshu.yaml +35 -0
  357. data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml +40 -0
  358. data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml +40 -0
  359. data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml +39 -0
  360. data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml +40 -0
  361. data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml +40 -0
  362. data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml +40 -0
  363. data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml +40 -0
  364. data/.data/spec/std/isa/inst/Zilx/lxsw.yaml +35 -0
  365. data/.data/spec/std/isa/inst/Zilx/lxswu.yaml +39 -0
  366. data/.data/spec/std/isa/inst/Zilx/lxw.yaml +35 -0
  367. data/.data/spec/std/isa/inst/Zilx/lxwu.yaml +39 -0
  368. data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
  369. data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
  370. data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
  371. data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
  372. data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +67 -0
  373. data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +67 -0
  374. data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml +61 -0
  375. data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +72 -0
  376. data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +72 -0
  377. data/.data/spec/std/isa/isa/builtin_functions.idl +1 -0
  378. data/.data/spec/std/isa/isa/fp.idl +42 -18
  379. data/.data/spec/std/isa/isa/globals.isa +27 -7
  380. data/.data/spec/std/isa/isa/interrupts.idl +1 -0
  381. data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml +70 -6
  382. data/.data/spec/std/isa/param/ELEN.yaml +27 -5
  383. data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +13 -0
  384. data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml +13 -3
  385. data/.data/spec/std/isa/param/HPM_EVENTS.yaml +0 -3
  386. data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
  387. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +8 -0
  388. data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
  389. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +71 -64
  390. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +71 -64
  391. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
  392. data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
  393. data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
  394. data/.data/spec/std/isa/param/{STVEC_MODE_VECTORED.yaml → PMP_NAPOT_SUPPORTED.yaml} +9 -9
  395. data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
  396. data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
  397. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +3 -2
  398. data/.data/spec/std/isa/param/STVEC_BASE_ALIGNMENT_VECTORED.yaml +100 -0
  399. data/.data/spec/std/isa/param/STVEC_MODES.yaml +31 -0
  400. data/.data/spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml +1 -1
  401. data/.data/spec/std/isa/param/SXLEN.yaml +2 -2
  402. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml +1 -1
  403. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml +1 -1
  404. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml +1 -1
  405. data/.data/spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml +1 -1
  406. data/.data/spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml +1 -1
  407. data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
  408. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
  409. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
  410. data/.data/spec/std/isa/param/UXLEN.yaml +1 -1
  411. data/.data/spec/std/isa/param/VLEN.yaml +16 -7
  412. data/.data/spec/std/isa/param/VSTVEC_MODES.yaml +31 -0
  413. data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
  414. data/lib/udb/ESPRESSO_VERSION +1 -1
  415. data/lib/udb/Z3_VERSION +1 -1
  416. data/lib/udb/config.rb +14 -2
  417. data/lib/udb/doc_link.rb +3 -4
  418. data/lib/udb/obj/csr.rb +1 -1
  419. data/lib/udb/obj/csr_field.rb +1 -1
  420. data/lib/udb/obj/extension.rb +1 -1
  421. data/lib/udb/obj/instruction.rb +1 -1
  422. data/lib/udb/obj/non_isa_specification.rb +22 -100
  423. data/lib/udb/version.rb +1 -1
  424. data/lib/udb/version_spec.rb +1 -1
  425. data/lib/udb/z3.rb +31 -9
  426. metadata +42 -9
  427. data/.data/spec/std/isa/param/STVEC_MODE_DIRECT.yaml +0 -21
  428. data/.data/spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml +0 -21
  429. data/.data/spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml +0 -21
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
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  * `mhpmevent30.MINH` is set and the current privilege level is M
86
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  <%- if ext?(:S) -%>
87
- * `mhpmevent30.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent30.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.SINH`<%- end -%> is set and the current privilege level is (H)S
88
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  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent30.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent30.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent30.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent30.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent30.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent30.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent30.VUINH`<%- end -%> is set and the current privilege level is VU
95
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  <%- end -%>
96
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  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT30[63:32]
77
+ alias: mhpmcounter30.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent31.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent31.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent31.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.SINH`<%- end -%> is set and the current privilege level is (H)S
88
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  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent31.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent31.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.UINH`<%- end -%> is set and the current privilege level is U
91
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  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent31.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent31.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent31.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent31.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent31.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
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  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT31[63:32]
77
+ alias: mhpmcounter31.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT3[63:32]
77
+ alias: mhpmcounter3.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent4.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent4.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent4.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.SINH`<%- end -%> is set and the current privilege level is (H)S
88
88
  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent4.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent4.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent4.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent4.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent4.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent4.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent4.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
96
  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT4[63:32]
77
+ alias: mhpmcounter4.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent5.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent5.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent5.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.SINH`<%- end -%> is set and the current privilege level is (H)S
88
88
  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent5.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent5.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent5.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent5.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent5.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent5.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent5.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
96
  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT5[63:32]
77
+ alias: mhpmcounter5.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent6.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent6.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent6.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.SINH`<%- end -%> is set and the current privilege level is (H)S
88
88
  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent6.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent6.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent6.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent6.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent6.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent6.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent6.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
96
  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT6[63:32]
77
+ alias: mhpmcounter6.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent7.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent7.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent7.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.SINH`<%- end -%> is set and the current privilege level is (H)S
88
88
  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent7.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent7.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent7.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent7.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent7.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent7.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent7.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
96
  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT7[63:32]
77
+ alias: mhpmcounter7.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent8.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent8.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent8.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.SINH`<%- end -%> is set and the current privilege level is (H)S
88
88
  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent8.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent8.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent8.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent8.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent8.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent8.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent8.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
96
  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT8[63:32]
77
+ alias: mhpmcounter8.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -84,14 +84,14 @@ fields:
84
84
  <%- if ext?(:Sscofpmf) -%>
85
85
  * `mhpmevent9.MINH` is set and the current privilege level is M
86
86
  <%- if ext?(:S) -%>
87
- * `mhpmevent9.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9..SINH`<%- end -%> is set and the current privilege level is (H)S
87
+ * `mhpmevent9.SINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.SINH`<%- end -%> is set and the current privilege level is (H)S
88
88
  <%- end -%>
89
89
  <%- if ext?(:U) -%>
90
- * `mhpmevent9.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.SINH`<%- end -%> is set and the current privilege level is U
90
+ * `mhpmevent9.UINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.UINH`<%- end -%> is set and the current privilege level is U
91
91
  <%- end -%>
92
92
  <%- if ext?(:H) -%>
93
- * `mhpmevent9.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.SINH`<%- end -%> is set and the current privilege level is VS
94
- * `mhpmevent9.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.SINH`<%- end -%> is set and the current privilege level is VU
93
+ * `mhpmevent9.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.VSINH`<%- end -%> is set and the current privilege level is VS
94
+ * `mhpmevent9.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `hpmevent9.VUINH`<%- end -%> is set and the current privilege level is VU
95
95
  <%- end -%>
96
96
  <%- end -%>
97
97
  --
@@ -74,7 +74,7 @@ definedBy:
74
74
  fields:
75
75
  COUNT:
76
76
  location: 31-0
77
- alias: mhpmcounter.COUNT9[63:32]
77
+ alias: mhpmcounter9.COUNT[63:32]
78
78
  description: |
79
79
  Upper bits of counter.
80
80
  type(): |
@@ -82,14 +82,14 @@ fields:
82
82
  <%%- if ext?(:Sscofpmf) -%>
83
83
  * `mhpmevent<%= hpm_num %>.MINH` is set and the current privilege level is M
84
84
  <%%- if ext?(:S) -%>
85
- * `mhpmevent<%= hpm_num %>.SINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>..SINH`<%%- end -%> is set and the current privilege level is (H)S
85
+ * `mhpmevent<%= hpm_num %>.SINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is (H)S
86
86
  <%%- end -%>
87
87
  <%%- if ext?(:U) -%>
88
- * `mhpmevent<%= hpm_num %>.UINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is U
88
+ * `mhpmevent<%= hpm_num %>.UINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.UINH`<%%- end -%> is set and the current privilege level is U
89
89
  <%%- end -%>
90
90
  <%%- if ext?(:H) -%>
91
- * `mhpmevent<%= hpm_num %>.VSINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is VS
92
- * `mhpmevent<%= hpm_num %>.VUINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is VU
91
+ * `mhpmevent<%= hpm_num %>.VSINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.VSINH`<%%- end -%> is set and the current privilege level is VS
92
+ * `mhpmevent<%= hpm_num %>.VUINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.VUINH`<%%- end -%> is set and the current privilege level is VU
93
93
  <%%- end -%>
94
94
  <%%- end -%>
95
95
  --
@@ -72,7 +72,7 @@ definedBy:
72
72
  fields:
73
73
  COUNT:
74
74
  location: 31-0
75
- alias: mhpmcounter.COUNT<%= hpm_num %>[63:32]
75
+ alias: mhpmcounter<%= hpm_num %>.COUNT[63:32]
76
76
  description: |
77
77
  Upper bits of counter.
78
78
  type(): |
@@ -138,7 +138,7 @@ fields:
138
138
 
139
139
  Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
140
140
 
141
- `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.TVTM`.
141
+ `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.VTVM`.
142
142
  type: RW
143
143
  reset_value: UNDEFINED_LEGAL
144
144
  VGEIN:
@@ -56,6 +56,7 @@ fields:
56
56
  && (CSR[sstateen0].JVT == 1'b0 || CSR[hstateen0].JVT == 1'b0) )) {
57
57
 
58
58
  unimplemented_csr($encoding);
59
+ return 0;
59
60
  }
60
61
  else {
61
62
  if (JVT_BASE_TYPE == "custom") {
@@ -32,7 +32,7 @@ fields:
32
32
  # since writes to this register may not be hart-local, it must be handled
33
33
  # as a special case
34
34
  if (xlen() == 32) {
35
- return sw_write_mcycle({read_mcycle()[63:31], csr_value.COUNT[31:0]});
35
+ return sw_write_mcycle({read_mcycle()[63:32], csr_value.COUNT[31:0]});
36
36
  } else {
37
37
  return sw_write_mcycle(csr_value.COUNT);
38
38
  }
@@ -40,7 +40,7 @@ fields:
40
40
  Cycle counter.
41
41
 
42
42
  <%- if ext?(:Zicntr) -%>
43
- Aliased as `cycle.CYCLE`.
43
+ Aliased as `cycle.COUNT`.
44
44
  <%- end -%>
45
45
 
46
46
  Increments every cycle unless:
@@ -49,14 +49,14 @@ fields:
49
49
  <%- if ext?(:Smcntrpmf) -%>
50
50
  * `mcyclecfg.MINH` is set and the current privilege level is M
51
51
  <%- if ext?(:S) -%>
52
- * `mcyclecfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is (H)S
52
+ * `mcyclecfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.SINH`<%- end -%> is set and the current privilege level is (H)S
53
53
  <%- end -%>
54
54
  <%- if ext?(:U) -%>
55
- * `mcyclecfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is U
55
+ * `mcyclecfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.UINH`<%- end -%> is set and the current privilege level is U
56
56
  <%- end -%>
57
57
  <%- if ext?(:H) -%>
58
- * `mcyclecfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VS
59
- * `mcyclecfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VU
58
+ * `mcyclecfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.VSINH`<%- end -%> is set and the current privilege level is VS
59
+ * `mcyclecfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.VUINH`<%- end -%> is set and the current privilege level is VU
60
60
  <%- end -%>
61
61
  <%- end -%>
62
62
  reset_value: UNDEFINED_LEGAL
@@ -296,6 +296,26 @@ fields:
296
296
  name: Zicfiss
297
297
  type: RW
298
298
  reset_value: UNDEFINED_LEGAL
299
+ LPE:
300
+ location: 2
301
+ description: |
302
+ *Landing Pad Enable*
303
+
304
+ When the LPE field is set to 1 and S-mode is implemented, the Zicfilp
305
+ extension is enabled in S-mode. If the LPE field is set to 1 and S-mode
306
+ is not implemented, the Zicfilp extension is enabled in U-mode. When the
307
+ LPE field is 0, the Zicfilp extension is not enabled in S-mode (or U-mode
308
+ if S-mode is not implemented), and the following rules apply:
309
+
310
+ * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
311
+ * The `LPAD` instruction operates as a no-op.
312
+
313
+ When `menvcfg.LPE` is 0, `henvcfg.LPE` and `senvcfg.LPE` are read-only zero.
314
+ definedBy:
315
+ extension:
316
+ name: Zicfilp
317
+ type: RW
318
+ reset_value: UNDEFINED_LEGAL
299
319
  FIOM:
300
320
  location: 0
301
321
  description: |
@@ -37,11 +37,11 @@ fields:
37
37
  * `minstretcfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is (H)S
38
38
  <%- end -%>
39
39
  <%- if ext?(:U) -%>
40
- * `minstretcfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is U
40
+ * `minstretcfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.UINH`<%- end -%> is set and the current privilege level is U
41
41
  <%- end -%>
42
42
  <%- if ext?(:H) -%>
43
- * `minstretcfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VS
44
- * `minstretcfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VU
43
+ * `minstretcfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.VSINH`<%- end -%> is set and the current privilege level is VS
44
+ * `minstretcfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.VUINH`<%- end -%> is set and the current privilege level is VU
45
45
  <%- end -%>
46
46
  <%- end -%>
47
47
 
@@ -28,7 +28,7 @@ fields:
28
28
  reset_value: UNDEFINED_LEGAL
29
29
  affectedBy: [Zicntr, Smcntrpmf, Smcdeleg, Ssccfg]
30
30
  sw_write(csr_value): |
31
- CSR[mcycle].COUNT = {csr_value.COUNT[31:0], CSR[minstret].COUNT[31:0]};
31
+ CSR[minstret].COUNT = {csr_value.COUNT[31:0], CSR[minstret].COUNT[31:0]};
32
32
  return csr_value.COUNT;
33
33
  definedBy:
34
34
  allOf:
@@ -111,7 +111,11 @@ fields:
111
111
  long_name: Guest Virtual Address
112
112
  description: |
113
113
  When a trap is taken and a guest virtual address is written into mtval, GVA is set.
114
- When a trap is taken and a guest virtual address is written into mtval, GVA is cleared.
114
+ GVA is written by the implementation whenever a trap is taken into
115
+ HS mode. For any trap (breakpoint, address misaligned, access fault,
116
+ page fault, or guest-page fault) that writes a guest virtual address to
117
+ `stval`, GVA is set to 1. For any other trap into HS-mode,
118
+ GVA is set to 0.
115
119
  type: RW-H
116
120
  reset_value: 0
117
121
  definedBy:
@@ -328,6 +332,8 @@ fields:
328
332
  type(): |
329
333
  if (CSR[misa].S == 1'b0) {
330
334
  return CsrFieldType::RO;
335
+ } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
336
+ return CsrFieldType::RO;
331
337
  } else {
332
338
  return CsrFieldType::RW;
333
339
  }
@@ -337,18 +343,18 @@ fields:
337
343
  reset_value(): |
338
344
  if (CSR[misa].S == 1'b0) {
339
345
  return 0;
340
- } else if (MSTATUS_TVM_IMPLEMENTED) {
341
- return UNDEFINED_LEGAL;
342
- } else {
346
+ } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
343
347
  return 0;
348
+ } else {
349
+ return UNDEFINED_LEGAL;
344
350
  }
345
351
  sw_write(csr_value): |
346
352
  if (CSR[misa].S == 1'b0) {
347
353
  return 0;
348
- } else if (MSTATUS_TVM_IMPLEMENTED) {
349
- return csr_value.TVM;
350
- } else {
354
+ } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
351
355
  return 0;
356
+ } else {
357
+ return csr_value.TVM;
352
358
  }
353
359
  MXR:
354
360
  location: 19
@@ -434,6 +440,10 @@ fields:
434
440
  - name: F
435
441
  - name: S
436
442
  reset_value(): |
443
+ if (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
444
+ # must be read-only-0
445
+ return 0;
446
+ }
437
447
  return $array_size(MSTATUS_FS_LEGAL_VALUES) == 1 ? MSTATUS_FS_LEGAL_VALUES[0] : UNDEFINED_LEGAL;
438
448
  sw_write(csr_value): |
439
449
  if (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
@@ -497,31 +507,17 @@ fields:
497
507
  return $array_size(MSTATUS_VS_LEGAL_VALUES) == 1 ? CsrFieldType::RO : CsrFieldType::RW;
498
508
  }
499
509
  reset_value(): |
500
- if (CSR[misa].V == 1'b1){
501
- return UNDEFINED_LEGAL;
502
- } else if ((CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0)) {
510
+ if ((!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) || (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0))) {
503
511
  # must be read-only-0
504
512
  return 0;
505
- } else {
506
- # there will be no hardware update in this case because we know the V extension isn't implemented
507
- if ($array_size(MSTATUS_VS_LEGAL_VALUES) == 0) {
508
- return 0;
509
- } else if ($array_size(MSTATUS_VS_LEGAL_VALUES) == 1) {
510
- return MSTATUS_VS_LEGAL_VALUES[0];
511
- } else {
512
- return UNDEFINED_LEGAL;
513
- }
514
513
  }
514
+ return $array_size(MSTATUS_VS_LEGAL_VALUES) == 1 ? MSTATUS_VS_LEGAL_VALUES[0] : UNDEFINED_LEGAL;
515
515
  sw_write(csr_value): |
516
- if (implemented?(ExtensionName::V) && CSR[misa].V == 1'b1){
517
- return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
518
- } else if (!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) {
516
+ if ((!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) || (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0))) {
519
517
  # must be read-only-0
520
518
  return 0;
521
- } else {
522
- # there will be no hardware update in this case because we know the V extension isn't implemented
523
- return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
524
519
  }
520
+ return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
525
521
  SPP:
526
522
  location: 8
527
523
  long_name: S-mode Previous Privilege
@@ -30,37 +30,15 @@ fields:
30
30
  # implementations may put further constraints on BASE when MODE != Direct
31
31
  # If that is the case, stvec should have an override for the implementation
32
32
 
33
- if (csr_value.MODE == 0) {
34
- if ($array_includes?(MTVEC_MODES, 0)) {
35
- return csr_value.BASE;
36
- }
37
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
38
- return CSR[mtvec].BASE;
39
- }
40
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
41
- return UNDEFINED_LEGAL_DETERMINISTIC;
42
- }
43
- unreachable();
44
- } else if (csr_value.MODE == 1) {
45
- if ($array_includes?(MTVEC_MODES, 1)) {
46
- return csr_value.BASE;
47
- }
48
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
49
- return CSR[mtvec].BASE;
50
- }
51
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
52
- return UNDEFINED_LEGAL_DETERMINISTIC;
53
- }
54
- unreachable();
55
- } else {
56
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
57
- return CSR[mtvec].BASE;
58
- }
59
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
60
- return UNDEFINED_LEGAL_DETERMINISTIC;
61
- }
62
- unreachable();
33
+ if ($array_includes?(MTVEC_MODES, csr_value.MODE)) {
34
+ return csr_value.BASE;
63
35
  }
36
+ if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
37
+ return CSR[mtvec].BASE;
38
+ } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
39
+ return UNDEFINED_LEGAL_DETERMINISTIC;
40
+ }
41
+ unreachable();
64
42
  reset_value: 0
65
43
  MODE:
66
44
  location: 1-0
@@ -71,7 +49,7 @@ fields:
71
49
 
72
50
  When Direct, all synchronous exceptions and asynchronous interrupts jump to (`mtvec.BASE` << 2).
73
51
 
74
- When Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.CAUSE`*4) while synchronous exceptions continue to jump to (`mtvec.BASE` << 2).
52
+ When Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.CODE`*4) while synchronous exceptions continue to jump to (`mtvec.BASE` << 2).
75
53
  type(): |
76
54
  if (MTVEC_ACCESS == "ro") {
77
55
  return CsrFieldType::RO;
@@ -79,32 +57,13 @@ fields:
79
57
 
80
58
  return ($array_size(MTVEC_MODES) == 1) ? CsrFieldType::RO : CsrFieldType::RWR;
81
59
  sw_write(csr_value): |
82
- if (csr_value.MODE == 0) {
83
- if ($array_includes?(MTVEC_MODES, 0)) {
84
- return csr_value.MODE;
85
- } else {
86
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
87
- return CSR[mtvec].MODE;
88
- } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
89
- return UNDEFINED_LEGAL_DETERMINISTIC;
90
- }
91
- }
92
- } else if (csr_value.MODE == 1) {
93
- if ($array_includes?(MTVEC_MODES, 1)) {
94
- return csr_value.MODE;
95
- } else {
96
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
97
- return CSR[mtvec].MODE;
98
- } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
99
- return UNDEFINED_LEGAL_DETERMINISTIC;
100
- }
101
- }
102
- } else {
103
- if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
104
- return CSR[mtvec].MODE;
105
- } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
106
- return UNDEFINED_LEGAL_DETERMINISTIC;
107
- }
60
+ if ($array_includes?(MTVEC_MODES, csr_value.MODE)) {
61
+ return csr_value.MODE;
62
+ }
63
+ if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
64
+ return CSR[mtvec].MODE;
65
+ } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
66
+ return UNDEFINED_LEGAL_DETERMINISTIC;
108
67
  }
109
68
  unreachable();
110
69
  reset_value(): |
@@ -165,6 +165,28 @@ fields:
165
165
  return 0;
166
166
  }
167
167
  return csr_value.SSE;
168
+ LPE:
169
+ location: 2
170
+ description: |
171
+ *Landing Pad Enable*
172
+
173
+ When the LPE field is set to 1 and `menvcfg.LPE` is 1, the Zicfilp extension
174
+ is enabled in U/VU-mode. Read-only zero when `menvcfg.LPE` is 0. When the LPE
175
+ field is 0, the Zicfilp extension is not enabled in U/VU-mode and the following
176
+ rules apply:
177
+
178
+ * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
179
+ * The `LPAD` instruction operates as a no-op.
180
+ definedBy:
181
+ extension:
182
+ name: Zicfilp
183
+ type: RW
184
+ reset_value: UNDEFINED_LEGAL
185
+ sw_write(csr_value): |
186
+ if (CSR[menvcfg].LPE == 0) {
187
+ return 0;
188
+ }
189
+ return csr_value.LPE;
168
190
  FIOM:
169
191
  location: 0
170
192
  description: |
@@ -202,4 +224,8 @@ sw_read(): |
202
224
  # senvcfg.SSE must read-as-zero
203
225
  value = value & ~(1 `<< 3);
204
226
  }
227
+ if (implemented?(ExtensionName::Zicfilp) && CSR[menvcfg].LPE == 0) {
228
+ # senvcfg.LPE must read-as-zero when menvcfg.LPE is 0
229
+ value = value & ~(1 `<< 2);
230
+ }
205
231
  return value;