udb 0.1.13 → 0.1.15

data/.data/spec/std/isa/inst/F/fmv.x.w.yaml

@@ -28,7 +28,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fnmadd.s.yaml

@@ -32,7 +32,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fnmsub.s.yaml

@@ -32,7 +32,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fsgnj.s.yaml

@@ -31,7 +31,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
     to: fmv.s fd, fs1

data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
     to: fneg.s fd, fs1

data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
     to: fabs.s fd, fs1

data/.data/spec/std/isa/inst/F/fsqrt.s.yaml

@@ -27,7 +27,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fsub.s.yaml

@@ -29,7 +29,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1
@@ -29,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/I/addi.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/addiw.yaml

@@ -21,6 +21,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/andi.yaml

@@ -17,6 +17,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/auipc.yaml

@@ -18,6 +18,7 @@ encoding:
     - name: imm
       location: 31-12
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
 hints:

data/.data/spec/std/isa/inst/I/lb.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lbu.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -29,6 +29,7 @@ encoding:
     variables:
       - name: imm
         location: 31-20
+        sign_extend: true
       - name: xs1
         location: 19-15
       - name: xd
@@ -39,6 +40,7 @@ encoding:
     variables:
       - name: imm
         location: 31-20
+        sign_extend: true
       - name: xs1
         location: 19-15
       - name: xd

data/.data/spec/std/isa/inst/I/lh.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lhu.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lui.yaml

@@ -18,6 +18,7 @@ encoding:
     - name: imm
       location: 31-12
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/I/lw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lwu.yaml

@@ -22,6 +22,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/ori.yaml

@@ -17,6 +17,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sb.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -25,6 +25,7 @@ encoding:
     variables:
       - name: imm
         location: 31-25|11-7
+        sign_extend: true
       - name: xs2
         not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
         location: 24-20
@@ -50,7 +51,7 @@ operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
   if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zclsd)) {
+    if (implemented?(ExtensionName::Zilsd)) {
       data = {X[xs2 + 1], X[xs2]};
     } else {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/inst/I/sh.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/slti.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sltiu.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sw.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/xori.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/Q/fadd.q.yaml

@@ -11,8 +11,8 @@ definedBy:
   extension:
     name: Q
 description: |
-  `fadd.q` is analogous to `fadd.d` and performs double-precision floating-point addition between
-  `qs1` and `qs2` and writes the final result to `qd`.
+  `fadd.q` is analogous to `fadd.d` and performs quad-precision floating-point addition between
+  `fs1` and `fs2` and writes the final result to `fd`.
 assembly: fd, fs1, fs2, rm
 encoding:
   match: 0000011------------------1010011

data/.data/spec/std/isa/inst/Q/fclass.q.yaml

@@ -8,13 +8,13 @@ kind: instruction
 name: fclass.q
 long_name: Floating-Point Classify Quad-Precision
 description: |
-  The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
-  register `rd` a 10-bit mask that indicates the class of the floating-point number.
+  The `fclass.q` instruction examines the value in floating-point register `fs1` and writes to integer
+  register `xd` a 10-bit mask that indicates the class of the floating-point number.
 
-  The format of the mask is described in table given below. The corresponding bit in `rd`
-  will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+  The format of the mask is described in table given below. The corresponding bit in `xd`
+  will be set if the property is true and clear otherwise. All other bits in `xd` are cleared.
 
-  Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
+  Note that exactly one bit in `xd` will be set. `fclass.q` does not set the floating-point
   exception flags.
 
   .Format of result of `fclass` instruction.

data/.data/spec/std/isa/inst/Q/fleq.q.yaml

@@ -13,7 +13,6 @@ description: |
 
   `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
   operation exception flag to be set.
-  This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fli.q.yaml

@@ -9,7 +9,7 @@ name: fli.q
 long_name: Floating-Point Load Immediate Quad-Precision
 description: |
   The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1`
-  field, into floating-point register `rd`.
+  field, into floating-point register `fd`.
   `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
 definedBy:
   extension:

data/.data/spec/std/isa/inst/Q/flq.yaml

@@ -24,6 +24,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd

data/.data/spec/std/isa/inst/Q/fltq.q.yaml

@@ -13,7 +13,6 @@ description: |
 
   `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
   operation exception flag to be set.
-  This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml

@@ -13,7 +13,6 @@ description: |
   If both inputs are _NaN_s, the result is the canonical _NaN_.
   If either input is _NaN_, the result is the canonical _NaN_.
   Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fminm.q.yaml

@@ -13,7 +13,6 @@ description: |
   If both inputs are _NaN_s, the result is the canonical _NaN_.
   If either input is _NaN_, the result is the canonical _NaN_.
   Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: fmvp.q.x
 long_name: Floating-Point Move Pair from Integer Registers to Quad-Precision Register
 description: |
-  The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
+  The `fmvp.q.x` instruction moves a quad-precision number from a pair of integer registers into
   a floating-point register.
   Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to
   floating-point register `fd`.

data/.data/spec/std/isa/inst/Q/fsq.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/V/vadc.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vadd.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vand.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vle8.v.yaml

@@ -36,3 +36,4 @@ operation(): |
     U32 end_bit_pos = start_bit_pos + 7;
     V[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
   }
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vmadc.vi.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmadc.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmerge.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmseq.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsle.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsne.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmv.v.i.yaml

@@ -24,6 +24,7 @@ encoding:
   variables:
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vor.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vrsub.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vsadd.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vse8.v.yaml

@@ -36,3 +36,4 @@ operation(): |
     U32 end_bit_pos = start_bit_pos + 7;
     write_memory(8, virtual_address + i, V[vs3][end_bit_pos:start_bit_pos], $encoding);
   }
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml

@@ -73,5 +73,7 @@ operation(): |
     }
   }
 
-  # stall while the reservation set is valid and no interrupt is pending
-  wrs_nto();
+  if (!ZAWRS_NTO_IS_NOP) {
+    # stall while the reservation set is valid and no interrupt is pending
+    wrs_nto();
+  }

data/.data/spec/std/isa/inst/Zba/add.uw.yaml

@@ -16,17 +16,15 @@ definedBy:
     - extension:
         name: Zba
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ADD.UW
-      value: 0b0000100
-    funct3:
-      display_name: ADD.UW
-      value: 0b000
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0000100----------000-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/Zbb/orc.b.yaml

@@ -35,7 +35,7 @@ operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for (U32 i=0; i<(xlen() - 8); i = i+8) {
+  for (U32 i=0; i < xlen(); i = i+8) {
     output[(i+7):i] = (input[(i+7):i] == 0) ? 8'd0 : ~8'd0;
   }
 

data/.data/spec/std/isa/inst/Zbkb/brev8.yaml

@@ -25,14 +25,14 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-8); i = i+8) {
+  for(U32 i=0; i < xlen(); i = i+8) {
     for(U32 j=0; j<8; j = j+1) {
-      output[(i*8)+(7-j)] = input[(i*8)+j];
+      output[i+(7-j)] = input[i+j];
     }
   }