therubyracer 0.4.9-x86-linux

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Files changed (637) hide show
  1. data/.gitignore +11 -0
  2. data/.gitmodules +3 -0
  3. data/Doxyfile +1514 -0
  4. data/History.txt +43 -0
  5. data/README.rdoc +157 -0
  6. data/Rakefile +51 -0
  7. data/docs/data_conversion.txt +18 -0
  8. data/ext/v8/callbacks.cpp +160 -0
  9. data/ext/v8/callbacks.h +14 -0
  10. data/ext/v8/convert_ruby.cpp +8 -0
  11. data/ext/v8/convert_ruby.h +99 -0
  12. data/ext/v8/convert_string.cpp +10 -0
  13. data/ext/v8/convert_string.h +73 -0
  14. data/ext/v8/convert_v8.cpp +9 -0
  15. data/ext/v8/convert_v8.h +121 -0
  16. data/ext/v8/converters.cpp +83 -0
  17. data/ext/v8/converters.h +23 -0
  18. data/ext/v8/extconf.rb +36 -0
  19. data/ext/v8/upstream/2.0.6/.gitignore +26 -0
  20. data/ext/v8/upstream/2.0.6/AUTHORS +23 -0
  21. data/ext/v8/upstream/2.0.6/ChangeLog +1479 -0
  22. data/ext/v8/upstream/2.0.6/LICENSE +55 -0
  23. data/ext/v8/upstream/2.0.6/SConstruct +1028 -0
  24. data/ext/v8/upstream/2.0.6/include/v8-debug.h +275 -0
  25. data/ext/v8/upstream/2.0.6/include/v8.h +3236 -0
  26. data/ext/v8/upstream/2.0.6/src/SConscript +283 -0
  27. data/ext/v8/upstream/2.0.6/src/accessors.cc +695 -0
  28. data/ext/v8/upstream/2.0.6/src/accessors.h +114 -0
  29. data/ext/v8/upstream/2.0.6/src/allocation.cc +198 -0
  30. data/ext/v8/upstream/2.0.6/src/allocation.h +169 -0
  31. data/ext/v8/upstream/2.0.6/src/api.cc +3831 -0
  32. data/ext/v8/upstream/2.0.6/src/api.h +479 -0
  33. data/ext/v8/upstream/2.0.6/src/apinatives.js +110 -0
  34. data/ext/v8/upstream/2.0.6/src/apiutils.h +69 -0
  35. data/ext/v8/upstream/2.0.6/src/arguments.h +97 -0
  36. data/ext/v8/upstream/2.0.6/src/arm/assembler-arm-inl.h +277 -0
  37. data/ext/v8/upstream/2.0.6/src/arm/assembler-arm.cc +1821 -0
  38. data/ext/v8/upstream/2.0.6/src/arm/assembler-arm.h +1027 -0
  39. data/ext/v8/upstream/2.0.6/src/arm/assembler-thumb2-inl.h +267 -0
  40. data/ext/v8/upstream/2.0.6/src/arm/assembler-thumb2.cc +1821 -0
  41. data/ext/v8/upstream/2.0.6/src/arm/assembler-thumb2.h +1027 -0
  42. data/ext/v8/upstream/2.0.6/src/arm/builtins-arm.cc +1271 -0
  43. data/ext/v8/upstream/2.0.6/src/arm/codegen-arm-inl.h +74 -0
  44. data/ext/v8/upstream/2.0.6/src/arm/codegen-arm.cc +6682 -0
  45. data/ext/v8/upstream/2.0.6/src/arm/codegen-arm.h +535 -0
  46. data/ext/v8/upstream/2.0.6/src/arm/constants-arm.cc +112 -0
  47. data/ext/v8/upstream/2.0.6/src/arm/constants-arm.h +347 -0
  48. data/ext/v8/upstream/2.0.6/src/arm/cpu-arm.cc +132 -0
  49. data/ext/v8/upstream/2.0.6/src/arm/debug-arm.cc +213 -0
  50. data/ext/v8/upstream/2.0.6/src/arm/disasm-arm.cc +1166 -0
  51. data/ext/v8/upstream/2.0.6/src/arm/fast-codegen-arm.cc +1698 -0
  52. data/ext/v8/upstream/2.0.6/src/arm/frames-arm.cc +123 -0
  53. data/ext/v8/upstream/2.0.6/src/arm/frames-arm.h +162 -0
  54. data/ext/v8/upstream/2.0.6/src/arm/ic-arm.cc +849 -0
  55. data/ext/v8/upstream/2.0.6/src/arm/jump-target-arm.cc +238 -0
  56. data/ext/v8/upstream/2.0.6/src/arm/macro-assembler-arm.cc +1259 -0
  57. data/ext/v8/upstream/2.0.6/src/arm/macro-assembler-arm.h +423 -0
  58. data/ext/v8/upstream/2.0.6/src/arm/regexp-macro-assembler-arm.cc +1266 -0
  59. data/ext/v8/upstream/2.0.6/src/arm/regexp-macro-assembler-arm.h +282 -0
  60. data/ext/v8/upstream/2.0.6/src/arm/register-allocator-arm-inl.h +103 -0
  61. data/ext/v8/upstream/2.0.6/src/arm/register-allocator-arm.cc +59 -0
  62. data/ext/v8/upstream/2.0.6/src/arm/register-allocator-arm.h +43 -0
  63. data/ext/v8/upstream/2.0.6/src/arm/simulator-arm.cc +2264 -0
  64. data/ext/v8/upstream/2.0.6/src/arm/simulator-arm.h +306 -0
  65. data/ext/v8/upstream/2.0.6/src/arm/stub-cache-arm.cc +1516 -0
  66. data/ext/v8/upstream/2.0.6/src/arm/virtual-frame-arm.cc +412 -0
  67. data/ext/v8/upstream/2.0.6/src/arm/virtual-frame-arm.h +532 -0
  68. data/ext/v8/upstream/2.0.6/src/array.js +1154 -0
  69. data/ext/v8/upstream/2.0.6/src/assembler.cc +772 -0
  70. data/ext/v8/upstream/2.0.6/src/assembler.h +525 -0
  71. data/ext/v8/upstream/2.0.6/src/ast.cc +512 -0
  72. data/ext/v8/upstream/2.0.6/src/ast.h +1820 -0
  73. data/ext/v8/upstream/2.0.6/src/bootstrapper.cc +1680 -0
  74. data/ext/v8/upstream/2.0.6/src/bootstrapper.h +103 -0
  75. data/ext/v8/upstream/2.0.6/src/builtins.cc +851 -0
  76. data/ext/v8/upstream/2.0.6/src/builtins.h +245 -0
  77. data/ext/v8/upstream/2.0.6/src/bytecodes-irregexp.h +104 -0
  78. data/ext/v8/upstream/2.0.6/src/char-predicates-inl.h +86 -0
  79. data/ext/v8/upstream/2.0.6/src/char-predicates.h +65 -0
  80. data/ext/v8/upstream/2.0.6/src/checks.cc +100 -0
  81. data/ext/v8/upstream/2.0.6/src/checks.h +284 -0
  82. data/ext/v8/upstream/2.0.6/src/code-stubs.cc +164 -0
  83. data/ext/v8/upstream/2.0.6/src/code-stubs.h +164 -0
  84. data/ext/v8/upstream/2.0.6/src/code.h +68 -0
  85. data/ext/v8/upstream/2.0.6/src/codegen-inl.h +88 -0
  86. data/ext/v8/upstream/2.0.6/src/codegen.cc +504 -0
  87. data/ext/v8/upstream/2.0.6/src/codegen.h +522 -0
  88. data/ext/v8/upstream/2.0.6/src/compilation-cache.cc +490 -0
  89. data/ext/v8/upstream/2.0.6/src/compilation-cache.h +98 -0
  90. data/ext/v8/upstream/2.0.6/src/compiler.cc +1132 -0
  91. data/ext/v8/upstream/2.0.6/src/compiler.h +107 -0
  92. data/ext/v8/upstream/2.0.6/src/contexts.cc +256 -0
  93. data/ext/v8/upstream/2.0.6/src/contexts.h +345 -0
  94. data/ext/v8/upstream/2.0.6/src/conversions-inl.h +95 -0
  95. data/ext/v8/upstream/2.0.6/src/conversions.cc +709 -0
  96. data/ext/v8/upstream/2.0.6/src/conversions.h +118 -0
  97. data/ext/v8/upstream/2.0.6/src/counters.cc +78 -0
  98. data/ext/v8/upstream/2.0.6/src/counters.h +239 -0
  99. data/ext/v8/upstream/2.0.6/src/cpu.h +65 -0
  100. data/ext/v8/upstream/2.0.6/src/d8-debug.cc +345 -0
  101. data/ext/v8/upstream/2.0.6/src/d8-debug.h +155 -0
  102. data/ext/v8/upstream/2.0.6/src/d8-posix.cc +675 -0
  103. data/ext/v8/upstream/2.0.6/src/d8-readline.cc +128 -0
  104. data/ext/v8/upstream/2.0.6/src/d8-windows.cc +42 -0
  105. data/ext/v8/upstream/2.0.6/src/d8.cc +776 -0
  106. data/ext/v8/upstream/2.0.6/src/d8.h +225 -0
  107. data/ext/v8/upstream/2.0.6/src/d8.js +1625 -0
  108. data/ext/v8/upstream/2.0.6/src/date-delay.js +1138 -0
  109. data/ext/v8/upstream/2.0.6/src/dateparser-inl.h +114 -0
  110. data/ext/v8/upstream/2.0.6/src/dateparser.cc +186 -0
  111. data/ext/v8/upstream/2.0.6/src/dateparser.h +240 -0
  112. data/ext/v8/upstream/2.0.6/src/debug-agent.cc +425 -0
  113. data/ext/v8/upstream/2.0.6/src/debug-agent.h +129 -0
  114. data/ext/v8/upstream/2.0.6/src/debug-delay.js +2073 -0
  115. data/ext/v8/upstream/2.0.6/src/debug.cc +2751 -0
  116. data/ext/v8/upstream/2.0.6/src/debug.h +866 -0
  117. data/ext/v8/upstream/2.0.6/src/disasm.h +77 -0
  118. data/ext/v8/upstream/2.0.6/src/disassembler.cc +318 -0
  119. data/ext/v8/upstream/2.0.6/src/disassembler.h +56 -0
  120. data/ext/v8/upstream/2.0.6/src/dtoa-config.c +91 -0
  121. data/ext/v8/upstream/2.0.6/src/execution.cc +701 -0
  122. data/ext/v8/upstream/2.0.6/src/execution.h +312 -0
  123. data/ext/v8/upstream/2.0.6/src/factory.cc +957 -0
  124. data/ext/v8/upstream/2.0.6/src/factory.h +393 -0
  125. data/ext/v8/upstream/2.0.6/src/fast-codegen.cc +725 -0
  126. data/ext/v8/upstream/2.0.6/src/fast-codegen.h +371 -0
  127. data/ext/v8/upstream/2.0.6/src/flag-definitions.h +426 -0
  128. data/ext/v8/upstream/2.0.6/src/flags.cc +555 -0
  129. data/ext/v8/upstream/2.0.6/src/flags.h +81 -0
  130. data/ext/v8/upstream/2.0.6/src/frame-element.cc +45 -0
  131. data/ext/v8/upstream/2.0.6/src/frame-element.h +235 -0
  132. data/ext/v8/upstream/2.0.6/src/frames-inl.h +215 -0
  133. data/ext/v8/upstream/2.0.6/src/frames.cc +749 -0
  134. data/ext/v8/upstream/2.0.6/src/frames.h +659 -0
  135. data/ext/v8/upstream/2.0.6/src/func-name-inferrer.cc +76 -0
  136. data/ext/v8/upstream/2.0.6/src/func-name-inferrer.h +135 -0
  137. data/ext/v8/upstream/2.0.6/src/global-handles.cc +516 -0
  138. data/ext/v8/upstream/2.0.6/src/global-handles.h +180 -0
  139. data/ext/v8/upstream/2.0.6/src/globals.h +608 -0
  140. data/ext/v8/upstream/2.0.6/src/handles-inl.h +76 -0
  141. data/ext/v8/upstream/2.0.6/src/handles.cc +811 -0
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  143. data/ext/v8/upstream/2.0.6/src/hashmap.cc +226 -0
  144. data/ext/v8/upstream/2.0.6/src/hashmap.h +120 -0
  145. data/ext/v8/upstream/2.0.6/src/heap-inl.h +407 -0
  146. data/ext/v8/upstream/2.0.6/src/heap-profiler.cc +695 -0
  147. data/ext/v8/upstream/2.0.6/src/heap-profiler.h +277 -0
  148. data/ext/v8/upstream/2.0.6/src/heap.cc +4204 -0
  149. data/ext/v8/upstream/2.0.6/src/heap.h +1704 -0
  150. data/ext/v8/upstream/2.0.6/src/ia32/assembler-ia32-inl.h +325 -0
  151. data/ext/v8/upstream/2.0.6/src/ia32/assembler-ia32.cc +2375 -0
  152. data/ext/v8/upstream/2.0.6/src/ia32/assembler-ia32.h +914 -0
  153. data/ext/v8/upstream/2.0.6/src/ia32/builtins-ia32.cc +1222 -0
  154. data/ext/v8/upstream/2.0.6/src/ia32/codegen-ia32-inl.h +46 -0
  155. data/ext/v8/upstream/2.0.6/src/ia32/codegen-ia32.cc +9770 -0
  156. data/ext/v8/upstream/2.0.6/src/ia32/codegen-ia32.h +834 -0
  157. data/ext/v8/upstream/2.0.6/src/ia32/cpu-ia32.cc +79 -0
  158. data/ext/v8/upstream/2.0.6/src/ia32/debug-ia32.cc +208 -0
  159. data/ext/v8/upstream/2.0.6/src/ia32/disasm-ia32.cc +1357 -0
  160. data/ext/v8/upstream/2.0.6/src/ia32/fast-codegen-ia32.cc +1813 -0
  161. data/ext/v8/upstream/2.0.6/src/ia32/frames-ia32.cc +111 -0
  162. data/ext/v8/upstream/2.0.6/src/ia32/frames-ia32.h +135 -0
  163. data/ext/v8/upstream/2.0.6/src/ia32/ic-ia32.cc +1490 -0
  164. data/ext/v8/upstream/2.0.6/src/ia32/jump-target-ia32.cc +432 -0
  165. data/ext/v8/upstream/2.0.6/src/ia32/macro-assembler-ia32.cc +1517 -0
  166. data/ext/v8/upstream/2.0.6/src/ia32/macro-assembler-ia32.h +528 -0
  167. data/ext/v8/upstream/2.0.6/src/ia32/regexp-macro-assembler-ia32.cc +1219 -0
  168. data/ext/v8/upstream/2.0.6/src/ia32/regexp-macro-assembler-ia32.h +230 -0
  169. data/ext/v8/upstream/2.0.6/src/ia32/register-allocator-ia32-inl.h +82 -0
  170. data/ext/v8/upstream/2.0.6/src/ia32/register-allocator-ia32.cc +99 -0
  171. data/ext/v8/upstream/2.0.6/src/ia32/register-allocator-ia32.h +43 -0
  172. data/ext/v8/upstream/2.0.6/src/ia32/simulator-ia32.cc +30 -0
  173. data/ext/v8/upstream/2.0.6/src/ia32/simulator-ia32.h +62 -0
  174. data/ext/v8/upstream/2.0.6/src/ia32/stub-cache-ia32.cc +1961 -0
  175. data/ext/v8/upstream/2.0.6/src/ia32/virtual-frame-ia32.cc +1105 -0
  176. data/ext/v8/upstream/2.0.6/src/ia32/virtual-frame-ia32.h +580 -0
  177. data/ext/v8/upstream/2.0.6/src/ic-inl.h +93 -0
  178. data/ext/v8/upstream/2.0.6/src/ic.cc +1426 -0
  179. data/ext/v8/upstream/2.0.6/src/ic.h +443 -0
  180. data/ext/v8/upstream/2.0.6/src/interpreter-irregexp.cc +646 -0
  181. data/ext/v8/upstream/2.0.6/src/interpreter-irregexp.h +48 -0
  182. data/ext/v8/upstream/2.0.6/src/json-delay.js +254 -0
  183. data/ext/v8/upstream/2.0.6/src/jsregexp.cc +5234 -0
  184. data/ext/v8/upstream/2.0.6/src/jsregexp.h +1439 -0
  185. data/ext/v8/upstream/2.0.6/src/jump-target-inl.h +49 -0
  186. data/ext/v8/upstream/2.0.6/src/jump-target.cc +383 -0
  187. data/ext/v8/upstream/2.0.6/src/jump-target.h +280 -0
  188. data/ext/v8/upstream/2.0.6/src/list-inl.h +166 -0
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  190. data/ext/v8/upstream/2.0.6/src/log-inl.h +126 -0
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  195. data/ext/v8/upstream/2.0.6/src/macro-assembler.h +93 -0
  196. data/ext/v8/upstream/2.0.6/src/macros.py +137 -0
  197. data/ext/v8/upstream/2.0.6/src/mark-compact.cc +2007 -0
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  215. data/ext/v8/upstream/2.0.6/src/platform-freebsd.cc +645 -0
  216. data/ext/v8/upstream/2.0.6/src/platform-linux.cc +808 -0
  217. data/ext/v8/upstream/2.0.6/src/platform-macos.cc +643 -0
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  231. data/ext/v8/upstream/2.0.6/src/regexp-macro-assembler-tracer.cc +356 -0
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  489. data/ext/v8/upstream/scons/engine/SCons/Tool/f90.py +62 -0
  490. data/ext/v8/upstream/scons/engine/SCons/Tool/f95.py +63 -0
  491. data/ext/v8/upstream/scons/engine/SCons/Tool/filesystem.py +98 -0
  492. data/ext/v8/upstream/scons/engine/SCons/Tool/fortran.py +63 -0
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  494. data/ext/v8/upstream/scons/engine/SCons/Tool/g77.py +73 -0
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  496. data/ext/v8/upstream/scons/engine/SCons/Tool/gcc.py +80 -0
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  528. data/ext/v8/upstream/scons/engine/SCons/Tool/mwcc.py +208 -0
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  550. data/ext/v8/upstream/scons/engine/SCons/Tool/sgicc.py +53 -0
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  559. data/ext/v8/upstream/scons/engine/SCons/Tool/swig.py +186 -0
  560. data/ext/v8/upstream/scons/engine/SCons/Tool/tar.py +73 -0
  561. data/ext/v8/upstream/scons/engine/SCons/Tool/tex.py +805 -0
  562. data/ext/v8/upstream/scons/engine/SCons/Tool/textfile.py +175 -0
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  564. data/ext/v8/upstream/scons/engine/SCons/Tool/wix.py +100 -0
  565. data/ext/v8/upstream/scons/engine/SCons/Tool/yacc.py +131 -0
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  567. data/ext/v8/upstream/scons/engine/SCons/Util.py +1645 -0
  568. data/ext/v8/upstream/scons/engine/SCons/Variables/BoolVariable.py +91 -0
  569. data/ext/v8/upstream/scons/engine/SCons/Variables/EnumVariable.py +107 -0
  570. data/ext/v8/upstream/scons/engine/SCons/Variables/ListVariable.py +139 -0
  571. data/ext/v8/upstream/scons/engine/SCons/Variables/PackageVariable.py +109 -0
  572. data/ext/v8/upstream/scons/engine/SCons/Variables/PathVariable.py +147 -0
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@@ -0,0 +1,267 @@
1
+ // Copyright (c) 1994-2006 Sun Microsystems Inc.
2
+ // All Rights Reserved.
3
+ //
4
+ // Redistribution and use in source and binary forms, with or without
5
+ // modification, are permitted provided that the following conditions
6
+ // are met:
7
+ //
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+ // - Redistributions of source code must retain the above copyright notice,
9
+ // this list of conditions and the following disclaimer.
10
+ //
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+ // - Redistribution in binary form must reproduce the above copyright
12
+ // notice, this list of conditions and the following disclaimer in the
13
+ // documentation and/or other materials provided with the
14
+ // distribution.
15
+ //
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+ // - Neither the name of Sun Microsystems or the names of contributors may
17
+ // be used to endorse or promote products derived from this software without
18
+ // specific prior written permission.
19
+ //
20
+ // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21
+ // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22
+ // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23
+ // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24
+ // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25
+ // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26
+ // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27
+ // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28
+ // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29
+ // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30
+ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31
+ // OF THE POSSIBILITY OF SUCH DAMAGE.
32
+
33
+ // The original source code covered by the above license above has been modified
34
+ // significantly by Google Inc.
35
+ // Copyright 2006-2008 the V8 project authors. All rights reserved.
36
+
37
+ #ifndef V8_ARM_ASSEMBLER_THUMB2_INL_H_
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+ #define V8_ARM_ASSEMBLER_THUMB2_INL_H_
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+
40
+ #include "arm/assembler-thumb2.h"
41
+ #include "cpu.h"
42
+
43
+
44
+ namespace v8 {
45
+ namespace internal {
46
+
47
+ Condition NegateCondition(Condition cc) {
48
+ ASSERT(cc != al);
49
+ return static_cast<Condition>(cc ^ ne);
50
+ }
51
+
52
+
53
+ void RelocInfo::apply(intptr_t delta) {
54
+ if (RelocInfo::IsInternalReference(rmode_)) {
55
+ // absolute code pointer inside code object moves with the code object.
56
+ int32_t* p = reinterpret_cast<int32_t*>(pc_);
57
+ *p += delta; // relocate entry
58
+ }
59
+ // We do not use pc relative addressing on ARM, so there is
60
+ // nothing else to do.
61
+ }
62
+
63
+
64
+ Address RelocInfo::target_address() {
65
+ ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
66
+ return Assembler::target_address_at(pc_);
67
+ }
68
+
69
+
70
+ Address RelocInfo::target_address_address() {
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+ ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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+ return reinterpret_cast<Address>(Assembler::target_address_address_at(pc_));
73
+ }
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+
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+
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+ void RelocInfo::set_target_address(Address target) {
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+ ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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+ Assembler::set_target_address_at(pc_, target);
79
+ }
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+
81
+
82
+ Object* RelocInfo::target_object() {
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+ ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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+ return Memory::Object_at(Assembler::target_address_address_at(pc_));
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+ }
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+
87
+
88
+ Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
89
+ ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
90
+ return Memory::Object_Handle_at(Assembler::target_address_address_at(pc_));
91
+ }
92
+
93
+
94
+ Object** RelocInfo::target_object_address() {
95
+ ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
96
+ return reinterpret_cast<Object**>(Assembler::target_address_address_at(pc_));
97
+ }
98
+
99
+
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+ void RelocInfo::set_target_object(Object* target) {
101
+ ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
102
+ Assembler::set_target_address_at(pc_, reinterpret_cast<Address>(target));
103
+ }
104
+
105
+
106
+ Address* RelocInfo::target_reference_address() {
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+ ASSERT(rmode_ == EXTERNAL_REFERENCE);
108
+ return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_));
109
+ }
110
+
111
+
112
+ Address RelocInfo::call_address() {
113
+ ASSERT(IsPatchedReturnSequence());
114
+ // The 2 instructions offset assumes patched return sequence.
115
+ ASSERT(IsJSReturn(rmode()));
116
+ return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize);
117
+ }
118
+
119
+
120
+ void RelocInfo::set_call_address(Address target) {
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+ ASSERT(IsPatchedReturnSequence());
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+ // The 2 instructions offset assumes patched return sequence.
123
+ ASSERT(IsJSReturn(rmode()));
124
+ Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target;
125
+ }
126
+
127
+
128
+ Object* RelocInfo::call_object() {
129
+ return *call_object_address();
130
+ }
131
+
132
+
133
+ Object** RelocInfo::call_object_address() {
134
+ ASSERT(IsPatchedReturnSequence());
135
+ // The 2 instructions offset assumes patched return sequence.
136
+ ASSERT(IsJSReturn(rmode()));
137
+ return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize);
138
+ }
139
+
140
+
141
+ void RelocInfo::set_call_object(Object* target) {
142
+ *call_object_address() = target;
143
+ }
144
+
145
+
146
+ bool RelocInfo::IsPatchedReturnSequence() {
147
+ // On ARM a "call instruction" is actually two instructions.
148
+ // mov lr, pc
149
+ // ldr pc, [pc, #XXX]
150
+ return (Assembler::instr_at(pc_) == kMovLrPc)
151
+ && ((Assembler::instr_at(pc_ + Assembler::kInstrSize) & kLdrPCPattern)
152
+ == kLdrPCPattern);
153
+ }
154
+
155
+
156
+ Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) {
157
+ rm_ = no_reg;
158
+ imm32_ = immediate;
159
+ rmode_ = rmode;
160
+ }
161
+
162
+
163
+ Operand::Operand(const char* s) {
164
+ rm_ = no_reg;
165
+ imm32_ = reinterpret_cast<int32_t>(s);
166
+ rmode_ = RelocInfo::EMBEDDED_STRING;
167
+ }
168
+
169
+
170
+ Operand::Operand(const ExternalReference& f) {
171
+ rm_ = no_reg;
172
+ imm32_ = reinterpret_cast<int32_t>(f.address());
173
+ rmode_ = RelocInfo::EXTERNAL_REFERENCE;
174
+ }
175
+
176
+
177
+ Operand::Operand(Object** opp) {
178
+ rm_ = no_reg;
179
+ imm32_ = reinterpret_cast<int32_t>(opp);
180
+ rmode_ = RelocInfo::NONE;
181
+ }
182
+
183
+
184
+ Operand::Operand(Context** cpp) {
185
+ rm_ = no_reg;
186
+ imm32_ = reinterpret_cast<int32_t>(cpp);
187
+ rmode_ = RelocInfo::NONE;
188
+ }
189
+
190
+
191
+ Operand::Operand(Smi* value) {
192
+ rm_ = no_reg;
193
+ imm32_ = reinterpret_cast<intptr_t>(value);
194
+ rmode_ = RelocInfo::NONE;
195
+ }
196
+
197
+
198
+ Operand::Operand(Register rm) {
199
+ rm_ = rm;
200
+ rs_ = no_reg;
201
+ shift_op_ = LSL;
202
+ shift_imm_ = 0;
203
+ }
204
+
205
+
206
+ bool Operand::is_reg() const {
207
+ return rm_.is_valid() &&
208
+ rs_.is(no_reg) &&
209
+ shift_op_ == LSL &&
210
+ shift_imm_ == 0;
211
+ }
212
+
213
+
214
+ void Assembler::CheckBuffer() {
215
+ if (buffer_space() <= kGap) {
216
+ GrowBuffer();
217
+ }
218
+ if (pc_offset() >= next_buffer_check_) {
219
+ CheckConstPool(false, true);
220
+ }
221
+ }
222
+
223
+
224
+ void Assembler::emit(Instr x) {
225
+ CheckBuffer();
226
+ *reinterpret_cast<Instr*>(pc_) = x;
227
+ pc_ += kInstrSize;
228
+ }
229
+
230
+
231
+ Address Assembler::target_address_address_at(Address pc) {
232
+ Instr instr = Memory::int32_at(pc);
233
+ // Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12].
234
+ ASSERT((instr & 0x0f7f0000) == 0x051f0000);
235
+ int offset = instr & 0xfff; // offset_12 is unsigned
236
+ if ((instr & (1 << 23)) == 0) offset = -offset; // U bit defines offset sign
237
+ // Verify that the constant pool comes after the instruction referencing it.
238
+ ASSERT(offset >= -4);
239
+ return pc + offset + 8;
240
+ }
241
+
242
+
243
+ Address Assembler::target_address_at(Address pc) {
244
+ return Memory::Address_at(target_address_address_at(pc));
245
+ }
246
+
247
+
248
+ void Assembler::set_target_at(Address constant_pool_entry,
249
+ Address target) {
250
+ Memory::Address_at(constant_pool_entry) = target;
251
+ }
252
+
253
+
254
+ void Assembler::set_target_address_at(Address pc, Address target) {
255
+ Memory::Address_at(target_address_address_at(pc)) = target;
256
+ // Intuitively, we would think it is necessary to flush the instruction cache
257
+ // after patching a target address in the code as follows:
258
+ // CPU::FlushICache(pc, sizeof(target));
259
+ // However, on ARM, no instruction was actually patched by the assignment
260
+ // above; the target address is not part of an instruction, it is patched in
261
+ // the constant pool and is read via a data access; the instruction accessing
262
+ // this address in the constant pool remains unchanged.
263
+ }
264
+
265
+ } } // namespace v8::internal
266
+
267
+ #endif // V8_ARM_ASSEMBLER_THUMB2_INL_H_
@@ -0,0 +1,1821 @@
1
+ // Copyright (c) 1994-2006 Sun Microsystems Inc.
2
+ // All Rights Reserved.
3
+ //
4
+ // Redistribution and use in source and binary forms, with or without
5
+ // modification, are permitted provided that the following conditions
6
+ // are met:
7
+ //
8
+ // - Redistributions of source code must retain the above copyright notice,
9
+ // this list of conditions and the following disclaimer.
10
+ //
11
+ // - Redistribution in binary form must reproduce the above copyright
12
+ // notice, this list of conditions and the following disclaimer in the
13
+ // documentation and/or other materials provided with the
14
+ // distribution.
15
+ //
16
+ // - Neither the name of Sun Microsystems or the names of contributors may
17
+ // be used to endorse or promote products derived from this software without
18
+ // specific prior written permission.
19
+ //
20
+ // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21
+ // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22
+ // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23
+ // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24
+ // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25
+ // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26
+ // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27
+ // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28
+ // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29
+ // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30
+ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31
+ // OF THE POSSIBILITY OF SUCH DAMAGE.
32
+
33
+ // The original source code covered by the above license above has been modified
34
+ // significantly by Google Inc.
35
+ // Copyright 2006-2008 the V8 project authors. All rights reserved.
36
+
37
+ #include "v8.h"
38
+
39
+ #include "arm/assembler-thumb2-inl.h"
40
+ #include "serialize.h"
41
+
42
+ namespace v8 {
43
+ namespace internal {
44
+
45
+ // Safe default is no features.
46
+ unsigned CpuFeatures::supported_ = 0;
47
+ unsigned CpuFeatures::enabled_ = 0;
48
+ unsigned CpuFeatures::found_by_runtime_probing_ = 0;
49
+
50
+ void CpuFeatures::Probe() {
51
+ // If the compiler is allowed to use vfp then we can use vfp too in our
52
+ // code generation.
53
+ #if !defined(__arm__)
54
+ // For the simulator=arm build, always use VFP since the arm simulator has
55
+ // VFP support.
56
+ supported_ |= 1u << VFP3;
57
+ #else
58
+ if (Serializer::enabled()) {
59
+ supported_ |= OS::CpuFeaturesImpliedByPlatform();
60
+ return; // No features if we might serialize.
61
+ }
62
+
63
+ if (OS::ArmCpuHasFeature(VFP3)) {
64
+ // This implementation also sets the VFP flags if
65
+ // runtime detection of VFP returns true.
66
+ supported_ |= 1u << VFP3;
67
+ found_by_runtime_probing_ |= 1u << VFP3;
68
+ }
69
+ #endif
70
+ }
71
+
72
+
73
+ // -----------------------------------------------------------------------------
74
+ // Implementation of Register and CRegister
75
+
76
+ Register no_reg = { -1 };
77
+
78
+ Register r0 = { 0 };
79
+ Register r1 = { 1 };
80
+ Register r2 = { 2 };
81
+ Register r3 = { 3 };
82
+ Register r4 = { 4 };
83
+ Register r5 = { 5 };
84
+ Register r6 = { 6 };
85
+ Register r7 = { 7 };
86
+ Register r8 = { 8 };
87
+ Register r9 = { 9 };
88
+ Register r10 = { 10 };
89
+ Register fp = { 11 };
90
+ Register ip = { 12 };
91
+ Register sp = { 13 };
92
+ Register lr = { 14 };
93
+ Register pc = { 15 };
94
+
95
+
96
+ CRegister no_creg = { -1 };
97
+
98
+ CRegister cr0 = { 0 };
99
+ CRegister cr1 = { 1 };
100
+ CRegister cr2 = { 2 };
101
+ CRegister cr3 = { 3 };
102
+ CRegister cr4 = { 4 };
103
+ CRegister cr5 = { 5 };
104
+ CRegister cr6 = { 6 };
105
+ CRegister cr7 = { 7 };
106
+ CRegister cr8 = { 8 };
107
+ CRegister cr9 = { 9 };
108
+ CRegister cr10 = { 10 };
109
+ CRegister cr11 = { 11 };
110
+ CRegister cr12 = { 12 };
111
+ CRegister cr13 = { 13 };
112
+ CRegister cr14 = { 14 };
113
+ CRegister cr15 = { 15 };
114
+
115
+ // Support for the VFP registers s0 to s31 (d0 to d15).
116
+ // Note that "sN:sM" is the same as "dN/2".
117
+ SwVfpRegister s0 = { 0 };
118
+ SwVfpRegister s1 = { 1 };
119
+ SwVfpRegister s2 = { 2 };
120
+ SwVfpRegister s3 = { 3 };
121
+ SwVfpRegister s4 = { 4 };
122
+ SwVfpRegister s5 = { 5 };
123
+ SwVfpRegister s6 = { 6 };
124
+ SwVfpRegister s7 = { 7 };
125
+ SwVfpRegister s8 = { 8 };
126
+ SwVfpRegister s9 = { 9 };
127
+ SwVfpRegister s10 = { 10 };
128
+ SwVfpRegister s11 = { 11 };
129
+ SwVfpRegister s12 = { 12 };
130
+ SwVfpRegister s13 = { 13 };
131
+ SwVfpRegister s14 = { 14 };
132
+ SwVfpRegister s15 = { 15 };
133
+ SwVfpRegister s16 = { 16 };
134
+ SwVfpRegister s17 = { 17 };
135
+ SwVfpRegister s18 = { 18 };
136
+ SwVfpRegister s19 = { 19 };
137
+ SwVfpRegister s20 = { 20 };
138
+ SwVfpRegister s21 = { 21 };
139
+ SwVfpRegister s22 = { 22 };
140
+ SwVfpRegister s23 = { 23 };
141
+ SwVfpRegister s24 = { 24 };
142
+ SwVfpRegister s25 = { 25 };
143
+ SwVfpRegister s26 = { 26 };
144
+ SwVfpRegister s27 = { 27 };
145
+ SwVfpRegister s28 = { 28 };
146
+ SwVfpRegister s29 = { 29 };
147
+ SwVfpRegister s30 = { 30 };
148
+ SwVfpRegister s31 = { 31 };
149
+
150
+ DwVfpRegister d0 = { 0 };
151
+ DwVfpRegister d1 = { 1 };
152
+ DwVfpRegister d2 = { 2 };
153
+ DwVfpRegister d3 = { 3 };
154
+ DwVfpRegister d4 = { 4 };
155
+ DwVfpRegister d5 = { 5 };
156
+ DwVfpRegister d6 = { 6 };
157
+ DwVfpRegister d7 = { 7 };
158
+ DwVfpRegister d8 = { 8 };
159
+ DwVfpRegister d9 = { 9 };
160
+ DwVfpRegister d10 = { 10 };
161
+ DwVfpRegister d11 = { 11 };
162
+ DwVfpRegister d12 = { 12 };
163
+ DwVfpRegister d13 = { 13 };
164
+ DwVfpRegister d14 = { 14 };
165
+ DwVfpRegister d15 = { 15 };
166
+
167
+ // -----------------------------------------------------------------------------
168
+ // Implementation of RelocInfo
169
+
170
+ const int RelocInfo::kApplyMask = 0;
171
+
172
+
173
+ void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
174
+ // Patch the code at the current address with the supplied instructions.
175
+ Instr* pc = reinterpret_cast<Instr*>(pc_);
176
+ Instr* instr = reinterpret_cast<Instr*>(instructions);
177
+ for (int i = 0; i < instruction_count; i++) {
178
+ *(pc + i) = *(instr + i);
179
+ }
180
+
181
+ // Indicate that code has changed.
182
+ CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize);
183
+ }
184
+
185
+
186
+ // Patch the code at the current PC with a call to the target address.
187
+ // Additional guard instructions can be added if required.
188
+ void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
189
+ // Patch the code at the current address with a call to the target.
190
+ UNIMPLEMENTED();
191
+ }
192
+
193
+
194
+ // -----------------------------------------------------------------------------
195
+ // Implementation of Operand and MemOperand
196
+ // See assembler-thumb2-inl.h for inlined constructors
197
+
198
+ Operand::Operand(Handle<Object> handle) {
199
+ rm_ = no_reg;
200
+ // Verify all Objects referred by code are NOT in new space.
201
+ Object* obj = *handle;
202
+ ASSERT(!Heap::InNewSpace(obj));
203
+ if (obj->IsHeapObject()) {
204
+ imm32_ = reinterpret_cast<intptr_t>(handle.location());
205
+ rmode_ = RelocInfo::EMBEDDED_OBJECT;
206
+ } else {
207
+ // no relocation needed
208
+ imm32_ = reinterpret_cast<intptr_t>(obj);
209
+ rmode_ = RelocInfo::NONE;
210
+ }
211
+ }
212
+
213
+
214
+ Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
215
+ ASSERT(is_uint5(shift_imm));
216
+ ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it
217
+ rm_ = rm;
218
+ rs_ = no_reg;
219
+ shift_op_ = shift_op;
220
+ shift_imm_ = shift_imm & 31;
221
+ if (shift_op == RRX) {
222
+ // encoded as ROR with shift_imm == 0
223
+ ASSERT(shift_imm == 0);
224
+ shift_op_ = ROR;
225
+ shift_imm_ = 0;
226
+ }
227
+ }
228
+
229
+
230
+ Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
231
+ ASSERT(shift_op != RRX);
232
+ rm_ = rm;
233
+ rs_ = no_reg;
234
+ shift_op_ = shift_op;
235
+ rs_ = rs;
236
+ }
237
+
238
+
239
+ MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {
240
+ rn_ = rn;
241
+ rm_ = no_reg;
242
+ offset_ = offset;
243
+ am_ = am;
244
+ }
245
+
246
+ MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {
247
+ rn_ = rn;
248
+ rm_ = rm;
249
+ shift_op_ = LSL;
250
+ shift_imm_ = 0;
251
+ am_ = am;
252
+ }
253
+
254
+
255
+ MemOperand::MemOperand(Register rn, Register rm,
256
+ ShiftOp shift_op, int shift_imm, AddrMode am) {
257
+ ASSERT(is_uint5(shift_imm));
258
+ rn_ = rn;
259
+ rm_ = rm;
260
+ shift_op_ = shift_op;
261
+ shift_imm_ = shift_imm & 31;
262
+ am_ = am;
263
+ }
264
+
265
+
266
+ // -----------------------------------------------------------------------------
267
+ // Implementation of Assembler
268
+
269
+ // Instruction encoding bits
270
+ enum {
271
+ H = 1 << 5, // halfword (or byte)
272
+ S6 = 1 << 6, // signed (or unsigned)
273
+ L = 1 << 20, // load (or store)
274
+ S = 1 << 20, // set condition code (or leave unchanged)
275
+ W = 1 << 21, // writeback base register (or leave unchanged)
276
+ A = 1 << 21, // accumulate in multiply instruction (or not)
277
+ B = 1 << 22, // unsigned byte (or word)
278
+ N = 1 << 22, // long (or short)
279
+ U = 1 << 23, // positive (or negative) offset/index
280
+ P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing)
281
+ I = 1 << 25, // immediate shifter operand (or not)
282
+
283
+ B4 = 1 << 4,
284
+ B5 = 1 << 5,
285
+ B6 = 1 << 6,
286
+ B7 = 1 << 7,
287
+ B8 = 1 << 8,
288
+ B9 = 1 << 9,
289
+ B12 = 1 << 12,
290
+ B16 = 1 << 16,
291
+ B18 = 1 << 18,
292
+ B19 = 1 << 19,
293
+ B20 = 1 << 20,
294
+ B21 = 1 << 21,
295
+ B22 = 1 << 22,
296
+ B23 = 1 << 23,
297
+ B24 = 1 << 24,
298
+ B25 = 1 << 25,
299
+ B26 = 1 << 26,
300
+ B27 = 1 << 27,
301
+
302
+ // Instruction bit masks
303
+ RdMask = 15 << 12, // in str instruction
304
+ CondMask = 15 << 28,
305
+ CoprocessorMask = 15 << 8,
306
+ OpCodeMask = 15 << 21, // in data-processing instructions
307
+ Imm24Mask = (1 << 24) - 1,
308
+ Off12Mask = (1 << 12) - 1,
309
+ // Reserved condition
310
+ nv = 15 << 28
311
+ };
312
+
313
+
314
+ // add(sp, sp, 4) instruction (aka Pop())
315
+ static const Instr kPopInstruction =
316
+ al | 4 * B21 | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12;
317
+ // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
318
+ // register r is not encoded.
319
+ static const Instr kPushRegPattern =
320
+ al | B26 | 4 | NegPreIndex | sp.code() * B16;
321
+ // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
322
+ // register r is not encoded.
323
+ static const Instr kPopRegPattern =
324
+ al | B26 | L | 4 | PostIndex | sp.code() * B16;
325
+ // mov lr, pc
326
+ const Instr kMovLrPc = al | 13*B21 | pc.code() | lr.code() * B12;
327
+ // ldr pc, [pc, #XXX]
328
+ const Instr kLdrPCPattern = al | B26 | L | pc.code() * B16;
329
+
330
+ // spare_buffer_
331
+ static const int kMinimalBufferSize = 4*KB;
332
+ static byte* spare_buffer_ = NULL;
333
+
334
+ Assembler::Assembler(void* buffer, int buffer_size) {
335
+ if (buffer == NULL) {
336
+ // do our own buffer management
337
+ if (buffer_size <= kMinimalBufferSize) {
338
+ buffer_size = kMinimalBufferSize;
339
+
340
+ if (spare_buffer_ != NULL) {
341
+ buffer = spare_buffer_;
342
+ spare_buffer_ = NULL;
343
+ }
344
+ }
345
+ if (buffer == NULL) {
346
+ buffer_ = NewArray<byte>(buffer_size);
347
+ } else {
348
+ buffer_ = static_cast<byte*>(buffer);
349
+ }
350
+ buffer_size_ = buffer_size;
351
+ own_buffer_ = true;
352
+
353
+ } else {
354
+ // use externally provided buffer instead
355
+ ASSERT(buffer_size > 0);
356
+ buffer_ = static_cast<byte*>(buffer);
357
+ buffer_size_ = buffer_size;
358
+ own_buffer_ = false;
359
+ }
360
+
361
+ // setup buffer pointers
362
+ ASSERT(buffer_ != NULL);
363
+ pc_ = buffer_;
364
+ reloc_info_writer.Reposition(buffer_ + buffer_size, pc_);
365
+ num_prinfo_ = 0;
366
+ next_buffer_check_ = 0;
367
+ no_const_pool_before_ = 0;
368
+ last_const_pool_end_ = 0;
369
+ last_bound_pos_ = 0;
370
+ current_statement_position_ = RelocInfo::kNoPosition;
371
+ current_position_ = RelocInfo::kNoPosition;
372
+ written_statement_position_ = current_statement_position_;
373
+ written_position_ = current_position_;
374
+ }
375
+
376
+
377
+ Assembler::~Assembler() {
378
+ if (own_buffer_) {
379
+ if (spare_buffer_ == NULL && buffer_size_ == kMinimalBufferSize) {
380
+ spare_buffer_ = buffer_;
381
+ } else {
382
+ DeleteArray(buffer_);
383
+ }
384
+ }
385
+ }
386
+
387
+
388
+ void Assembler::GetCode(CodeDesc* desc) {
389
+ // emit constant pool if necessary
390
+ CheckConstPool(true, false);
391
+ ASSERT(num_prinfo_ == 0);
392
+
393
+ // setup desc
394
+ desc->buffer = buffer_;
395
+ desc->buffer_size = buffer_size_;
396
+ desc->instr_size = pc_offset();
397
+ desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
398
+ }
399
+
400
+
401
+ void Assembler::Align(int m) {
402
+ ASSERT(m >= 4 && IsPowerOf2(m));
403
+ while ((pc_offset() & (m - 1)) != 0) {
404
+ nop();
405
+ }
406
+ }
407
+
408
+
409
+ // Labels refer to positions in the (to be) generated code.
410
+ // There are bound, linked, and unused labels.
411
+ //
412
+ // Bound labels refer to known positions in the already
413
+ // generated code. pos() is the position the label refers to.
414
+ //
415
+ // Linked labels refer to unknown positions in the code
416
+ // to be generated; pos() is the position of the last
417
+ // instruction using the label.
418
+
419
+
420
+ // The link chain is terminated by a negative code position (must be aligned)
421
+ const int kEndOfChain = -4;
422
+
423
+
424
+ int Assembler::target_at(int pos) {
425
+ Instr instr = instr_at(pos);
426
+ if ((instr & ~Imm24Mask) == 0) {
427
+ // Emitted label constant, not part of a branch.
428
+ return instr - (Code::kHeaderSize - kHeapObjectTag);
429
+ }
430
+ ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
431
+ int imm26 = ((instr & Imm24Mask) << 8) >> 6;
432
+ if ((instr & CondMask) == nv && (instr & B24) != 0)
433
+ // blx uses bit 24 to encode bit 2 of imm26
434
+ imm26 += 2;
435
+
436
+ return pos + kPcLoadDelta + imm26;
437
+ }
438
+
439
+
440
+ void Assembler::target_at_put(int pos, int target_pos) {
441
+ Instr instr = instr_at(pos);
442
+ if ((instr & ~Imm24Mask) == 0) {
443
+ ASSERT(target_pos == kEndOfChain || target_pos >= 0);
444
+ // Emitted label constant, not part of a branch.
445
+ // Make label relative to Code* of generated Code object.
446
+ instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
447
+ return;
448
+ }
449
+ int imm26 = target_pos - (pos + kPcLoadDelta);
450
+ ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
451
+ if ((instr & CondMask) == nv) {
452
+ // blx uses bit 24 to encode bit 2 of imm26
453
+ ASSERT((imm26 & 1) == 0);
454
+ instr = (instr & ~(B24 | Imm24Mask)) | ((imm26 & 2) >> 1)*B24;
455
+ } else {
456
+ ASSERT((imm26 & 3) == 0);
457
+ instr &= ~Imm24Mask;
458
+ }
459
+ int imm24 = imm26 >> 2;
460
+ ASSERT(is_int24(imm24));
461
+ instr_at_put(pos, instr | (imm24 & Imm24Mask));
462
+ }
463
+
464
+
465
+ void Assembler::print(Label* L) {
466
+ if (L->is_unused()) {
467
+ PrintF("unused label\n");
468
+ } else if (L->is_bound()) {
469
+ PrintF("bound label to %d\n", L->pos());
470
+ } else if (L->is_linked()) {
471
+ Label l = *L;
472
+ PrintF("unbound label");
473
+ while (l.is_linked()) {
474
+ PrintF("@ %d ", l.pos());
475
+ Instr instr = instr_at(l.pos());
476
+ if ((instr & ~Imm24Mask) == 0) {
477
+ PrintF("value\n");
478
+ } else {
479
+ ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx
480
+ int cond = instr & CondMask;
481
+ const char* b;
482
+ const char* c;
483
+ if (cond == nv) {
484
+ b = "blx";
485
+ c = "";
486
+ } else {
487
+ if ((instr & B24) != 0)
488
+ b = "bl";
489
+ else
490
+ b = "b";
491
+
492
+ switch (cond) {
493
+ case eq: c = "eq"; break;
494
+ case ne: c = "ne"; break;
495
+ case hs: c = "hs"; break;
496
+ case lo: c = "lo"; break;
497
+ case mi: c = "mi"; break;
498
+ case pl: c = "pl"; break;
499
+ case vs: c = "vs"; break;
500
+ case vc: c = "vc"; break;
501
+ case hi: c = "hi"; break;
502
+ case ls: c = "ls"; break;
503
+ case ge: c = "ge"; break;
504
+ case lt: c = "lt"; break;
505
+ case gt: c = "gt"; break;
506
+ case le: c = "le"; break;
507
+ case al: c = ""; break;
508
+ default:
509
+ c = "";
510
+ UNREACHABLE();
511
+ }
512
+ }
513
+ PrintF("%s%s\n", b, c);
514
+ }
515
+ next(&l);
516
+ }
517
+ } else {
518
+ PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
519
+ }
520
+ }
521
+
522
+
523
+ void Assembler::bind_to(Label* L, int pos) {
524
+ ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position
525
+ while (L->is_linked()) {
526
+ int fixup_pos = L->pos();
527
+ next(L); // call next before overwriting link with target at fixup_pos
528
+ target_at_put(fixup_pos, pos);
529
+ }
530
+ L->bind_to(pos);
531
+
532
+ // Keep track of the last bound label so we don't eliminate any instructions
533
+ // before a bound label.
534
+ if (pos > last_bound_pos_)
535
+ last_bound_pos_ = pos;
536
+ }
537
+
538
+
539
+ void Assembler::link_to(Label* L, Label* appendix) {
540
+ if (appendix->is_linked()) {
541
+ if (L->is_linked()) {
542
+ // append appendix to L's list
543
+ int fixup_pos;
544
+ int link = L->pos();
545
+ do {
546
+ fixup_pos = link;
547
+ link = target_at(fixup_pos);
548
+ } while (link > 0);
549
+ ASSERT(link == kEndOfChain);
550
+ target_at_put(fixup_pos, appendix->pos());
551
+ } else {
552
+ // L is empty, simply use appendix
553
+ *L = *appendix;
554
+ }
555
+ }
556
+ appendix->Unuse(); // appendix should not be used anymore
557
+ }
558
+
559
+
560
+ void Assembler::bind(Label* L) {
561
+ ASSERT(!L->is_bound()); // label can only be bound once
562
+ bind_to(L, pc_offset());
563
+ }
564
+
565
+
566
+ void Assembler::next(Label* L) {
567
+ ASSERT(L->is_linked());
568
+ int link = target_at(L->pos());
569
+ if (link > 0) {
570
+ L->link_to(link);
571
+ } else {
572
+ ASSERT(link == kEndOfChain);
573
+ L->Unuse();
574
+ }
575
+ }
576
+
577
+
578
+ // Low-level code emission routines depending on the addressing mode
579
+ static bool fits_shifter(uint32_t imm32,
580
+ uint32_t* rotate_imm,
581
+ uint32_t* immed_8,
582
+ Instr* instr) {
583
+ // imm32 must be unsigned
584
+ for (int rot = 0; rot < 16; rot++) {
585
+ uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot));
586
+ if ((imm8 <= 0xff)) {
587
+ *rotate_imm = rot;
588
+ *immed_8 = imm8;
589
+ return true;
590
+ }
591
+ }
592
+ // if the opcode is mov or mvn and if ~imm32 fits, change the opcode
593
+ if (instr != NULL && (*instr & 0xd*B21) == 0xd*B21) {
594
+ if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
595
+ *instr ^= 0x2*B21;
596
+ return true;
597
+ }
598
+ }
599
+ return false;
600
+ }
601
+
602
+
603
+ // We have to use the temporary register for things that can be relocated even
604
+ // if they can be encoded in the ARM's 12 bits of immediate-offset instruction
605
+ // space. There is no guarantee that the relocated location can be similarly
606
+ // encoded.
607
+ static bool MustUseIp(RelocInfo::Mode rmode) {
608
+ if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
609
+ #ifdef DEBUG
610
+ if (!Serializer::enabled()) {
611
+ Serializer::TooLateToEnableNow();
612
+ }
613
+ #endif
614
+ return Serializer::enabled();
615
+ } else if (rmode == RelocInfo::NONE) {
616
+ return false;
617
+ }
618
+ return true;
619
+ }
620
+
621
+
622
+ void Assembler::addrmod1(Instr instr,
623
+ Register rn,
624
+ Register rd,
625
+ const Operand& x) {
626
+ CheckBuffer();
627
+ ASSERT((instr & ~(CondMask | OpCodeMask | S)) == 0);
628
+ if (!x.rm_.is_valid()) {
629
+ // immediate
630
+ uint32_t rotate_imm;
631
+ uint32_t immed_8;
632
+ if (MustUseIp(x.rmode_) ||
633
+ !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {
634
+ // The immediate operand cannot be encoded as a shifter operand, so load
635
+ // it first to register ip and change the original instruction to use ip.
636
+ // However, if the original instruction is a 'mov rd, x' (not setting the
637
+ // condition code), then replace it with a 'ldr rd, [pc]'
638
+ RecordRelocInfo(x.rmode_, x.imm32_);
639
+ CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed
640
+ Condition cond = static_cast<Condition>(instr & CondMask);
641
+ if ((instr & ~CondMask) == 13*B21) { // mov, S not set
642
+ ldr(rd, MemOperand(pc, 0), cond);
643
+ } else {
644
+ ldr(ip, MemOperand(pc, 0), cond);
645
+ addrmod1(instr, rn, rd, Operand(ip));
646
+ }
647
+ return;
648
+ }
649
+ instr |= I | rotate_imm*B8 | immed_8;
650
+ } else if (!x.rs_.is_valid()) {
651
+ // immediate shift
652
+ instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
653
+ } else {
654
+ // register shift
655
+ ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
656
+ instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();
657
+ }
658
+ emit(instr | rn.code()*B16 | rd.code()*B12);
659
+ if (rn.is(pc) || x.rm_.is(pc))
660
+ // block constant pool emission for one instruction after reading pc
661
+ BlockConstPoolBefore(pc_offset() + kInstrSize);
662
+ }
663
+
664
+
665
+ void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
666
+ ASSERT((instr & ~(CondMask | B | L)) == B26);
667
+ int am = x.am_;
668
+ if (!x.rm_.is_valid()) {
669
+ // immediate offset
670
+ int offset_12 = x.offset_;
671
+ if (offset_12 < 0) {
672
+ offset_12 = -offset_12;
673
+ am ^= U;
674
+ }
675
+ if (!is_uint12(offset_12)) {
676
+ // immediate offset cannot be encoded, load it first to register ip
677
+ // rn (and rd in a load) should never be ip, or will be trashed
678
+ ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
679
+ mov(ip, Operand(x.offset_), LeaveCC,
680
+ static_cast<Condition>(instr & CondMask));
681
+ addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));
682
+ return;
683
+ }
684
+ ASSERT(offset_12 >= 0); // no masking needed
685
+ instr |= offset_12;
686
+ } else {
687
+ // register offset (shift_imm_ and shift_op_ are 0) or scaled
688
+ // register offset the constructors make sure than both shift_imm_
689
+ // and shift_op_ are initialized
690
+ ASSERT(!x.rm_.is(pc));
691
+ instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
692
+ }
693
+ ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
694
+ emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
695
+ }
696
+
697
+
698
+ void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
699
+ ASSERT((instr & ~(CondMask | L | S6 | H)) == (B4 | B7));
700
+ ASSERT(x.rn_.is_valid());
701
+ int am = x.am_;
702
+ if (!x.rm_.is_valid()) {
703
+ // immediate offset
704
+ int offset_8 = x.offset_;
705
+ if (offset_8 < 0) {
706
+ offset_8 = -offset_8;
707
+ am ^= U;
708
+ }
709
+ if (!is_uint8(offset_8)) {
710
+ // immediate offset cannot be encoded, load it first to register ip
711
+ // rn (and rd in a load) should never be ip, or will be trashed
712
+ ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
713
+ mov(ip, Operand(x.offset_), LeaveCC,
714
+ static_cast<Condition>(instr & CondMask));
715
+ addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
716
+ return;
717
+ }
718
+ ASSERT(offset_8 >= 0); // no masking needed
719
+ instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf);
720
+ } else if (x.shift_imm_ != 0) {
721
+ // scaled register offset not supported, load index first
722
+ // rn (and rd in a load) should never be ip, or will be trashed
723
+ ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
724
+ mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,
725
+ static_cast<Condition>(instr & CondMask));
726
+ addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
727
+ return;
728
+ } else {
729
+ // register offset
730
+ ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback
731
+ instr |= x.rm_.code();
732
+ }
733
+ ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
734
+ emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
735
+ }
736
+
737
+
738
+ void Assembler::addrmod4(Instr instr, Register rn, RegList rl) {
739
+ ASSERT((instr & ~(CondMask | P | U | W | L)) == B27);
740
+ ASSERT(rl != 0);
741
+ ASSERT(!rn.is(pc));
742
+ emit(instr | rn.code()*B16 | rl);
743
+ }
744
+
745
+
746
+ void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
747
+ // unindexed addressing is not encoded by this function
748
+ ASSERT_EQ((B27 | B26),
749
+ (instr & ~(CondMask | CoprocessorMask | P | U | N | W | L)));
750
+ ASSERT(x.rn_.is_valid() && !x.rm_.is_valid());
751
+ int am = x.am_;
752
+ int offset_8 = x.offset_;
753
+ ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset
754
+ offset_8 >>= 2;
755
+ if (offset_8 < 0) {
756
+ offset_8 = -offset_8;
757
+ am ^= U;
758
+ }
759
+ ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte
760
+ ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
761
+
762
+ // post-indexed addressing requires W == 1; different than in addrmod2/3
763
+ if ((am & P) == 0)
764
+ am |= W;
765
+
766
+ ASSERT(offset_8 >= 0); // no masking needed
767
+ emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8);
768
+ }
769
+
770
+
771
+ int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
772
+ int target_pos;
773
+ if (L->is_bound()) {
774
+ target_pos = L->pos();
775
+ } else {
776
+ if (L->is_linked()) {
777
+ target_pos = L->pos(); // L's link
778
+ } else {
779
+ target_pos = kEndOfChain;
780
+ }
781
+ L->link_to(pc_offset());
782
+ }
783
+
784
+ // Block the emission of the constant pool, since the branch instruction must
785
+ // be emitted at the pc offset recorded by the label
786
+ BlockConstPoolBefore(pc_offset() + kInstrSize);
787
+ return target_pos - (pc_offset() + kPcLoadDelta);
788
+ }
789
+
790
+
791
+ void Assembler::label_at_put(Label* L, int at_offset) {
792
+ int target_pos;
793
+ if (L->is_bound()) {
794
+ target_pos = L->pos();
795
+ } else {
796
+ if (L->is_linked()) {
797
+ target_pos = L->pos(); // L's link
798
+ } else {
799
+ target_pos = kEndOfChain;
800
+ }
801
+ L->link_to(at_offset);
802
+ instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
803
+ }
804
+ }
805
+
806
+
807
+ // Branch instructions
808
+ void Assembler::b(int branch_offset, Condition cond) {
809
+ ASSERT((branch_offset & 3) == 0);
810
+ int imm24 = branch_offset >> 2;
811
+ ASSERT(is_int24(imm24));
812
+ emit(cond | B27 | B25 | (imm24 & Imm24Mask));
813
+
814
+ if (cond == al)
815
+ // dead code is a good location to emit the constant pool
816
+ CheckConstPool(false, false);
817
+ }
818
+
819
+
820
+ void Assembler::bl(int branch_offset, Condition cond) {
821
+ ASSERT((branch_offset & 3) == 0);
822
+ int imm24 = branch_offset >> 2;
823
+ ASSERT(is_int24(imm24));
824
+ emit(cond | B27 | B25 | B24 | (imm24 & Imm24Mask));
825
+ }
826
+
827
+
828
+ void Assembler::blx(int branch_offset) { // v5 and above
829
+ WriteRecordedPositions();
830
+ ASSERT((branch_offset & 1) == 0);
831
+ int h = ((branch_offset & 2) >> 1)*B24;
832
+ int imm24 = branch_offset >> 2;
833
+ ASSERT(is_int24(imm24));
834
+ emit(15 << 28 | B27 | B25 | h | (imm24 & Imm24Mask));
835
+ }
836
+
837
+
838
+ void Assembler::blx(Register target, Condition cond) { // v5 and above
839
+ WriteRecordedPositions();
840
+ ASSERT(!target.is(pc));
841
+ emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | 3*B4 | target.code());
842
+ }
843
+
844
+
845
+ void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t
846
+ WriteRecordedPositions();
847
+ ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged
848
+ emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | B4 | target.code());
849
+ }
850
+
851
+
852
+ // Data-processing instructions
853
+ void Assembler::and_(Register dst, Register src1, const Operand& src2,
854
+ SBit s, Condition cond) {
855
+ addrmod1(cond | 0*B21 | s, src1, dst, src2);
856
+ }
857
+
858
+
859
+ void Assembler::eor(Register dst, Register src1, const Operand& src2,
860
+ SBit s, Condition cond) {
861
+ addrmod1(cond | 1*B21 | s, src1, dst, src2);
862
+ }
863
+
864
+
865
+ void Assembler::sub(Register dst, Register src1, const Operand& src2,
866
+ SBit s, Condition cond) {
867
+ addrmod1(cond | 2*B21 | s, src1, dst, src2);
868
+ }
869
+
870
+
871
+ void Assembler::rsb(Register dst, Register src1, const Operand& src2,
872
+ SBit s, Condition cond) {
873
+ addrmod1(cond | 3*B21 | s, src1, dst, src2);
874
+ }
875
+
876
+
877
+ void Assembler::add(Register dst, Register src1, const Operand& src2,
878
+ SBit s, Condition cond) {
879
+ addrmod1(cond | 4*B21 | s, src1, dst, src2);
880
+
881
+ // Eliminate pattern: push(r), pop()
882
+ // str(src, MemOperand(sp, 4, NegPreIndex), al);
883
+ // add(sp, sp, Operand(kPointerSize));
884
+ // Both instructions can be eliminated.
885
+ int pattern_size = 2 * kInstrSize;
886
+ if (FLAG_push_pop_elimination &&
887
+ last_bound_pos_ <= (pc_offset() - pattern_size) &&
888
+ reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
889
+ // pattern
890
+ instr_at(pc_ - 1 * kInstrSize) == kPopInstruction &&
891
+ (instr_at(pc_ - 2 * kInstrSize) & ~RdMask) == kPushRegPattern) {
892
+ pc_ -= 2 * kInstrSize;
893
+ if (FLAG_print_push_pop_elimination) {
894
+ PrintF("%x push(reg)/pop() eliminated\n", pc_offset());
895
+ }
896
+ }
897
+ }
898
+
899
+
900
+ void Assembler::adc(Register dst, Register src1, const Operand& src2,
901
+ SBit s, Condition cond) {
902
+ addrmod1(cond | 5*B21 | s, src1, dst, src2);
903
+ }
904
+
905
+
906
+ void Assembler::sbc(Register dst, Register src1, const Operand& src2,
907
+ SBit s, Condition cond) {
908
+ addrmod1(cond | 6*B21 | s, src1, dst, src2);
909
+ }
910
+
911
+
912
+ void Assembler::rsc(Register dst, Register src1, const Operand& src2,
913
+ SBit s, Condition cond) {
914
+ addrmod1(cond | 7*B21 | s, src1, dst, src2);
915
+ }
916
+
917
+
918
+ void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
919
+ addrmod1(cond | 8*B21 | S, src1, r0, src2);
920
+ }
921
+
922
+
923
+ void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
924
+ addrmod1(cond | 9*B21 | S, src1, r0, src2);
925
+ }
926
+
927
+
928
+ void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
929
+ addrmod1(cond | 10*B21 | S, src1, r0, src2);
930
+ }
931
+
932
+
933
+ void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
934
+ addrmod1(cond | 11*B21 | S, src1, r0, src2);
935
+ }
936
+
937
+
938
+ void Assembler::orr(Register dst, Register src1, const Operand& src2,
939
+ SBit s, Condition cond) {
940
+ addrmod1(cond | 12*B21 | s, src1, dst, src2);
941
+ }
942
+
943
+
944
+ void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
945
+ if (dst.is(pc)) {
946
+ WriteRecordedPositions();
947
+ }
948
+ addrmod1(cond | 13*B21 | s, r0, dst, src);
949
+ }
950
+
951
+
952
+ void Assembler::bic(Register dst, Register src1, const Operand& src2,
953
+ SBit s, Condition cond) {
954
+ addrmod1(cond | 14*B21 | s, src1, dst, src2);
955
+ }
956
+
957
+
958
+ void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
959
+ addrmod1(cond | 15*B21 | s, r0, dst, src);
960
+ }
961
+
962
+
963
+ // Multiply instructions
964
+ void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
965
+ SBit s, Condition cond) {
966
+ ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
967
+ emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 |
968
+ src2.code()*B8 | B7 | B4 | src1.code());
969
+ }
970
+
971
+
972
+ void Assembler::mul(Register dst, Register src1, Register src2,
973
+ SBit s, Condition cond) {
974
+ ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
975
+ // dst goes in bits 16-19 for this instruction!
976
+ emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
977
+ }
978
+
979
+
980
+ void Assembler::smlal(Register dstL,
981
+ Register dstH,
982
+ Register src1,
983
+ Register src2,
984
+ SBit s,
985
+ Condition cond) {
986
+ ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
987
+ ASSERT(!dstL.is(dstH));
988
+ emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 |
989
+ src2.code()*B8 | B7 | B4 | src1.code());
990
+ }
991
+
992
+
993
+ void Assembler::smull(Register dstL,
994
+ Register dstH,
995
+ Register src1,
996
+ Register src2,
997
+ SBit s,
998
+ Condition cond) {
999
+ ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1000
+ ASSERT(!dstL.is(dstH));
1001
+ emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 |
1002
+ src2.code()*B8 | B7 | B4 | src1.code());
1003
+ }
1004
+
1005
+
1006
+ void Assembler::umlal(Register dstL,
1007
+ Register dstH,
1008
+ Register src1,
1009
+ Register src2,
1010
+ SBit s,
1011
+ Condition cond) {
1012
+ ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1013
+ ASSERT(!dstL.is(dstH));
1014
+ emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 |
1015
+ src2.code()*B8 | B7 | B4 | src1.code());
1016
+ }
1017
+
1018
+
1019
+ void Assembler::umull(Register dstL,
1020
+ Register dstH,
1021
+ Register src1,
1022
+ Register src2,
1023
+ SBit s,
1024
+ Condition cond) {
1025
+ ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1026
+ ASSERT(!dstL.is(dstH));
1027
+ emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 |
1028
+ src2.code()*B8 | B7 | B4 | src1.code());
1029
+ }
1030
+
1031
+
1032
+ // Miscellaneous arithmetic instructions
1033
+ void Assembler::clz(Register dst, Register src, Condition cond) {
1034
+ // v5 and above.
1035
+ ASSERT(!dst.is(pc) && !src.is(pc));
1036
+ emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 |
1037
+ 15*B8 | B4 | src.code());
1038
+ }
1039
+
1040
+
1041
+ // Status register access instructions
1042
+ void Assembler::mrs(Register dst, SRegister s, Condition cond) {
1043
+ ASSERT(!dst.is(pc));
1044
+ emit(cond | B24 | s | 15*B16 | dst.code()*B12);
1045
+ }
1046
+
1047
+
1048
+ void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
1049
+ Condition cond) {
1050
+ ASSERT(fields >= B16 && fields < B20); // at least one field set
1051
+ Instr instr;
1052
+ if (!src.rm_.is_valid()) {
1053
+ // immediate
1054
+ uint32_t rotate_imm;
1055
+ uint32_t immed_8;
1056
+ if (MustUseIp(src.rmode_) ||
1057
+ !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) {
1058
+ // immediate operand cannot be encoded, load it first to register ip
1059
+ RecordRelocInfo(src.rmode_, src.imm32_);
1060
+ ldr(ip, MemOperand(pc, 0), cond);
1061
+ msr(fields, Operand(ip), cond);
1062
+ return;
1063
+ }
1064
+ instr = I | rotate_imm*B8 | immed_8;
1065
+ } else {
1066
+ ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed
1067
+ instr = src.rm_.code();
1068
+ }
1069
+ emit(cond | instr | B24 | B21 | fields | 15*B12);
1070
+ }
1071
+
1072
+
1073
+ // Load/Store instructions
1074
+ void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
1075
+ if (dst.is(pc)) {
1076
+ WriteRecordedPositions();
1077
+ }
1078
+ addrmod2(cond | B26 | L, dst, src);
1079
+
1080
+ // Eliminate pattern: push(r), pop(r)
1081
+ // str(r, MemOperand(sp, 4, NegPreIndex), al)
1082
+ // ldr(r, MemOperand(sp, 4, PostIndex), al)
1083
+ // Both instructions can be eliminated.
1084
+ int pattern_size = 2 * kInstrSize;
1085
+ if (FLAG_push_pop_elimination &&
1086
+ last_bound_pos_ <= (pc_offset() - pattern_size) &&
1087
+ reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
1088
+ // pattern
1089
+ instr_at(pc_ - 1 * kInstrSize) == (kPopRegPattern | dst.code() * B12) &&
1090
+ instr_at(pc_ - 2 * kInstrSize) == (kPushRegPattern | dst.code() * B12)) {
1091
+ pc_ -= 2 * kInstrSize;
1092
+ if (FLAG_print_push_pop_elimination) {
1093
+ PrintF("%x push/pop (same reg) eliminated\n", pc_offset());
1094
+ }
1095
+ }
1096
+ }
1097
+
1098
+
1099
+ void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
1100
+ addrmod2(cond | B26, src, dst);
1101
+
1102
+ // Eliminate pattern: pop(), push(r)
1103
+ // add sp, sp, #4 LeaveCC, al; str r, [sp, #-4], al
1104
+ // -> str r, [sp, 0], al
1105
+ int pattern_size = 2 * kInstrSize;
1106
+ if (FLAG_push_pop_elimination &&
1107
+ last_bound_pos_ <= (pc_offset() - pattern_size) &&
1108
+ reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
1109
+ instr_at(pc_ - 1 * kInstrSize) == (kPushRegPattern | src.code() * B12) &&
1110
+ instr_at(pc_ - 2 * kInstrSize) == kPopInstruction) {
1111
+ pc_ -= 2 * kInstrSize;
1112
+ emit(al | B26 | 0 | Offset | sp.code() * B16 | src.code() * B12);
1113
+ if (FLAG_print_push_pop_elimination) {
1114
+ PrintF("%x pop()/push(reg) eliminated\n", pc_offset());
1115
+ }
1116
+ }
1117
+ }
1118
+
1119
+
1120
+ void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
1121
+ addrmod2(cond | B26 | B | L, dst, src);
1122
+ }
1123
+
1124
+
1125
+ void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
1126
+ addrmod2(cond | B26 | B, src, dst);
1127
+ }
1128
+
1129
+
1130
+ void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
1131
+ addrmod3(cond | L | B7 | H | B4, dst, src);
1132
+ }
1133
+
1134
+
1135
+ void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
1136
+ addrmod3(cond | B7 | H | B4, src, dst);
1137
+ }
1138
+
1139
+
1140
+ void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
1141
+ addrmod3(cond | L | B7 | S6 | B4, dst, src);
1142
+ }
1143
+
1144
+
1145
+ void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
1146
+ addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
1147
+ }
1148
+
1149
+
1150
+ // Load/Store multiple instructions
1151
+ void Assembler::ldm(BlockAddrMode am,
1152
+ Register base,
1153
+ RegList dst,
1154
+ Condition cond) {
1155
+ // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable
1156
+ ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
1157
+
1158
+ addrmod4(cond | B27 | am | L, base, dst);
1159
+
1160
+ // emit the constant pool after a function return implemented by ldm ..{..pc}
1161
+ if (cond == al && (dst & pc.bit()) != 0) {
1162
+ // There is a slight chance that the ldm instruction was actually a call,
1163
+ // in which case it would be wrong to return into the constant pool; we
1164
+ // recognize this case by checking if the emission of the pool was blocked
1165
+ // at the pc of the ldm instruction by a mov lr, pc instruction; if this is
1166
+ // the case, we emit a jump over the pool.
1167
+ CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize);
1168
+ }
1169
+ }
1170
+
1171
+
1172
+ void Assembler::stm(BlockAddrMode am,
1173
+ Register base,
1174
+ RegList src,
1175
+ Condition cond) {
1176
+ addrmod4(cond | B27 | am, base, src);
1177
+ }
1178
+
1179
+
1180
+ // Semaphore instructions
1181
+ void Assembler::swp(Register dst, Register src, Register base, Condition cond) {
1182
+ ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
1183
+ ASSERT(!dst.is(base) && !src.is(base));
1184
+ emit(cond | P | base.code()*B16 | dst.code()*B12 |
1185
+ B7 | B4 | src.code());
1186
+ }
1187
+
1188
+
1189
+ void Assembler::swpb(Register dst,
1190
+ Register src,
1191
+ Register base,
1192
+ Condition cond) {
1193
+ ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
1194
+ ASSERT(!dst.is(base) && !src.is(base));
1195
+ emit(cond | P | B | base.code()*B16 | dst.code()*B12 |
1196
+ B7 | B4 | src.code());
1197
+ }
1198
+
1199
+
1200
+ // Exception-generating instructions and debugging support
1201
+ void Assembler::stop(const char* msg) {
1202
+ #if !defined(__arm__)
1203
+ // The simulator handles these special instructions and stops execution.
1204
+ emit(15 << 28 | ((intptr_t) msg));
1205
+ #else
1206
+ // Just issue a simple break instruction for now. Alternatively we could use
1207
+ // the swi(0x9f0001) instruction on Linux.
1208
+ bkpt(0);
1209
+ #endif
1210
+ }
1211
+
1212
+
1213
+ void Assembler::bkpt(uint32_t imm16) { // v5 and above
1214
+ ASSERT(is_uint16(imm16));
1215
+ emit(al | B24 | B21 | (imm16 >> 4)*B8 | 7*B4 | (imm16 & 0xf));
1216
+ }
1217
+
1218
+
1219
+ void Assembler::swi(uint32_t imm24, Condition cond) {
1220
+ ASSERT(is_uint24(imm24));
1221
+ emit(cond | 15*B24 | imm24);
1222
+ }
1223
+
1224
+
1225
+ // Coprocessor instructions
1226
+ void Assembler::cdp(Coprocessor coproc,
1227
+ int opcode_1,
1228
+ CRegister crd,
1229
+ CRegister crn,
1230
+ CRegister crm,
1231
+ int opcode_2,
1232
+ Condition cond) {
1233
+ ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2));
1234
+ emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 |
1235
+ crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code());
1236
+ }
1237
+
1238
+
1239
+ void Assembler::cdp2(Coprocessor coproc,
1240
+ int opcode_1,
1241
+ CRegister crd,
1242
+ CRegister crn,
1243
+ CRegister crm,
1244
+ int opcode_2) { // v5 and above
1245
+ cdp(coproc, opcode_1, crd, crn, crm, opcode_2, static_cast<Condition>(nv));
1246
+ }
1247
+
1248
+
1249
+ void Assembler::mcr(Coprocessor coproc,
1250
+ int opcode_1,
1251
+ Register rd,
1252
+ CRegister crn,
1253
+ CRegister crm,
1254
+ int opcode_2,
1255
+ Condition cond) {
1256
+ ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2));
1257
+ emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 |
1258
+ rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
1259
+ }
1260
+
1261
+
1262
+ void Assembler::mcr2(Coprocessor coproc,
1263
+ int opcode_1,
1264
+ Register rd,
1265
+ CRegister crn,
1266
+ CRegister crm,
1267
+ int opcode_2) { // v5 and above
1268
+ mcr(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv));
1269
+ }
1270
+
1271
+
1272
+ void Assembler::mrc(Coprocessor coproc,
1273
+ int opcode_1,
1274
+ Register rd,
1275
+ CRegister crn,
1276
+ CRegister crm,
1277
+ int opcode_2,
1278
+ Condition cond) {
1279
+ ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2));
1280
+ emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 |
1281
+ rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
1282
+ }
1283
+
1284
+
1285
+ void Assembler::mrc2(Coprocessor coproc,
1286
+ int opcode_1,
1287
+ Register rd,
1288
+ CRegister crn,
1289
+ CRegister crm,
1290
+ int opcode_2) { // v5 and above
1291
+ mrc(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv));
1292
+ }
1293
+
1294
+
1295
+ void Assembler::ldc(Coprocessor coproc,
1296
+ CRegister crd,
1297
+ const MemOperand& src,
1298
+ LFlag l,
1299
+ Condition cond) {
1300
+ addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src);
1301
+ }
1302
+
1303
+
1304
+ void Assembler::ldc(Coprocessor coproc,
1305
+ CRegister crd,
1306
+ Register rn,
1307
+ int option,
1308
+ LFlag l,
1309
+ Condition cond) {
1310
+ // unindexed addressing
1311
+ ASSERT(is_uint8(option));
1312
+ emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 |
1313
+ coproc*B8 | (option & 255));
1314
+ }
1315
+
1316
+
1317
+ void Assembler::ldc2(Coprocessor coproc,
1318
+ CRegister crd,
1319
+ const MemOperand& src,
1320
+ LFlag l) { // v5 and above
1321
+ ldc(coproc, crd, src, l, static_cast<Condition>(nv));
1322
+ }
1323
+
1324
+
1325
+ void Assembler::ldc2(Coprocessor coproc,
1326
+ CRegister crd,
1327
+ Register rn,
1328
+ int option,
1329
+ LFlag l) { // v5 and above
1330
+ ldc(coproc, crd, rn, option, l, static_cast<Condition>(nv));
1331
+ }
1332
+
1333
+
1334
+ void Assembler::stc(Coprocessor coproc,
1335
+ CRegister crd,
1336
+ const MemOperand& dst,
1337
+ LFlag l,
1338
+ Condition cond) {
1339
+ addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst);
1340
+ }
1341
+
1342
+
1343
+ void Assembler::stc(Coprocessor coproc,
1344
+ CRegister crd,
1345
+ Register rn,
1346
+ int option,
1347
+ LFlag l,
1348
+ Condition cond) {
1349
+ // unindexed addressing
1350
+ ASSERT(is_uint8(option));
1351
+ emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 |
1352
+ coproc*B8 | (option & 255));
1353
+ }
1354
+
1355
+
1356
+ void Assembler::stc2(Coprocessor
1357
+ coproc, CRegister crd,
1358
+ const MemOperand& dst,
1359
+ LFlag l) { // v5 and above
1360
+ stc(coproc, crd, dst, l, static_cast<Condition>(nv));
1361
+ }
1362
+
1363
+
1364
+ void Assembler::stc2(Coprocessor coproc,
1365
+ CRegister crd,
1366
+ Register rn,
1367
+ int option,
1368
+ LFlag l) { // v5 and above
1369
+ stc(coproc, crd, rn, option, l, static_cast<Condition>(nv));
1370
+ }
1371
+
1372
+
1373
+ // Support for VFP.
1374
+ void Assembler::vmov(const DwVfpRegister dst,
1375
+ const Register src1,
1376
+ const Register src2,
1377
+ const Condition cond) {
1378
+ // Dm = <Rt,Rt2>.
1379
+ // Instruction details available in ARM DDI 0406A, A8-646.
1380
+ // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) |
1381
+ // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
1382
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1383
+ ASSERT(!src1.is(pc) && !src2.is(pc));
1384
+ emit(cond | 0xC*B24 | B22 | src2.code()*B16 |
1385
+ src1.code()*B12 | 0xB*B8 | B4 | dst.code());
1386
+ }
1387
+
1388
+
1389
+ void Assembler::vmov(const Register dst1,
1390
+ const Register dst2,
1391
+ const DwVfpRegister src,
1392
+ const Condition cond) {
1393
+ // <Rt,Rt2> = Dm.
1394
+ // Instruction details available in ARM DDI 0406A, A8-646.
1395
+ // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) |
1396
+ // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
1397
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1398
+ ASSERT(!dst1.is(pc) && !dst2.is(pc));
1399
+ emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 |
1400
+ dst1.code()*B12 | 0xB*B8 | B4 | src.code());
1401
+ }
1402
+
1403
+
1404
+ void Assembler::vmov(const SwVfpRegister dst,
1405
+ const Register src,
1406
+ const Condition cond) {
1407
+ // Sn = Rt.
1408
+ // Instruction details available in ARM DDI 0406A, A8-642.
1409
+ // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) |
1410
+ // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
1411
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1412
+ ASSERT(!src.is(pc));
1413
+ emit(cond | 0xE*B24 | (dst.code() >> 1)*B16 |
1414
+ src.code()*B12 | 0xA*B8 | (0x1 & dst.code())*B7 | B4);
1415
+ }
1416
+
1417
+
1418
+ void Assembler::vmov(const Register dst,
1419
+ const SwVfpRegister src,
1420
+ const Condition cond) {
1421
+ // Rt = Sn.
1422
+ // Instruction details available in ARM DDI 0406A, A8-642.
1423
+ // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) |
1424
+ // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
1425
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1426
+ ASSERT(!dst.is(pc));
1427
+ emit(cond | 0xE*B24 | B20 | (src.code() >> 1)*B16 |
1428
+ dst.code()*B12 | 0xA*B8 | (0x1 & src.code())*B7 | B4);
1429
+ }
1430
+
1431
+
1432
+ void Assembler::vcvt(const DwVfpRegister dst,
1433
+ const SwVfpRegister src,
1434
+ const Condition cond) {
1435
+ // Dd = Sm (integer in Sm converted to IEEE 64-bit doubles in Dd).
1436
+ // Instruction details available in ARM DDI 0406A, A8-576.
1437
+ // cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) |opc2=000(18-16) |
1438
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | op(7)=1 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
1439
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1440
+ emit(cond | 0xE*B24 | B23 | 0x3*B20 | B19 |
1441
+ dst.code()*B12 | 0x5*B9 | B8 | B7 | B6 |
1442
+ (0x1 & src.code())*B5 | (src.code() >> 1));
1443
+ }
1444
+
1445
+
1446
+ void Assembler::vcvt(const SwVfpRegister dst,
1447
+ const DwVfpRegister src,
1448
+ const Condition cond) {
1449
+ // Sd = Dm (IEEE 64-bit doubles in Dm converted to 32 bit integer in Sd).
1450
+ // Instruction details available in ARM DDI 0406A, A8-576.
1451
+ // cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) | opc2=101(18-16)|
1452
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | op(7)=? | 1(6) | M=?(5) | 0(4) | Vm(3-0)
1453
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1454
+ emit(cond | 0xE*B24 | B23 |(0x1 & dst.code())*B22 |
1455
+ 0x3*B20 | B19 | 0x5*B16 | (dst.code() >> 1)*B12 |
1456
+ 0x5*B9 | B8 | B7 | B6 | src.code());
1457
+ }
1458
+
1459
+
1460
+ void Assembler::vadd(const DwVfpRegister dst,
1461
+ const DwVfpRegister src1,
1462
+ const DwVfpRegister src2,
1463
+ const Condition cond) {
1464
+ // Dd = vadd(Dn, Dm) double precision floating point addition.
1465
+ // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1466
+ // Instruction details available in ARM DDI 0406A, A8-536.
1467
+ // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
1468
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
1469
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1470
+ emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1471
+ dst.code()*B12 | 0x5*B9 | B8 | src2.code());
1472
+ }
1473
+
1474
+
1475
+ void Assembler::vsub(const DwVfpRegister dst,
1476
+ const DwVfpRegister src1,
1477
+ const DwVfpRegister src2,
1478
+ const Condition cond) {
1479
+ // Dd = vsub(Dn, Dm) double precision floating point subtraction.
1480
+ // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1481
+ // Instruction details available in ARM DDI 0406A, A8-784.
1482
+ // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
1483
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
1484
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1485
+ emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1486
+ dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
1487
+ }
1488
+
1489
+
1490
+ void Assembler::vmul(const DwVfpRegister dst,
1491
+ const DwVfpRegister src1,
1492
+ const DwVfpRegister src2,
1493
+ const Condition cond) {
1494
+ // Dd = vmul(Dn, Dm) double precision floating point multiplication.
1495
+ // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1496
+ // Instruction details available in ARM DDI 0406A, A8-784.
1497
+ // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) |
1498
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
1499
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1500
+ emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
1501
+ dst.code()*B12 | 0x5*B9 | B8 | src2.code());
1502
+ }
1503
+
1504
+
1505
+ void Assembler::vdiv(const DwVfpRegister dst,
1506
+ const DwVfpRegister src1,
1507
+ const DwVfpRegister src2,
1508
+ const Condition cond) {
1509
+ // Dd = vdiv(Dn, Dm) double precision floating point division.
1510
+ // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1511
+ // Instruction details available in ARM DDI 0406A, A8-584.
1512
+ // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) |
1513
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0)
1514
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1515
+ emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
1516
+ dst.code()*B12 | 0x5*B9 | B8 | src2.code());
1517
+ }
1518
+
1519
+
1520
+ void Assembler::vcmp(const DwVfpRegister src1,
1521
+ const DwVfpRegister src2,
1522
+ const SBit s,
1523
+ const Condition cond) {
1524
+ // vcmp(Dd, Dm) double precision floating point comparison.
1525
+ // Instruction details available in ARM DDI 0406A, A8-570.
1526
+ // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
1527
+ // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | Vm(3-0)
1528
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1529
+ emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
1530
+ src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
1531
+ }
1532
+
1533
+
1534
+ void Assembler::vmrs(Register dst, Condition cond) {
1535
+ // Instruction details available in ARM DDI 0406A, A8-652.
1536
+ // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) |
1537
+ // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
1538
+ ASSERT(CpuFeatures::IsEnabled(VFP3));
1539
+ emit(cond | 0xE*B24 | 0xF*B20 | B16 |
1540
+ dst.code()*B12 | 0xA*B8 | B4);
1541
+ }
1542
+
1543
+
1544
+ // Pseudo instructions
1545
+ void Assembler::lea(Register dst,
1546
+ const MemOperand& x,
1547
+ SBit s,
1548
+ Condition cond) {
1549
+ int am = x.am_;
1550
+ if (!x.rm_.is_valid()) {
1551
+ // immediate offset
1552
+ if ((am & P) == 0) // post indexing
1553
+ mov(dst, Operand(x.rn_), s, cond);
1554
+ else if ((am & U) == 0) // negative indexing
1555
+ sub(dst, x.rn_, Operand(x.offset_), s, cond);
1556
+ else
1557
+ add(dst, x.rn_, Operand(x.offset_), s, cond);
1558
+ } else {
1559
+ // Register offset (shift_imm_ and shift_op_ are 0) or scaled
1560
+ // register offset the constructors make sure than both shift_imm_
1561
+ // and shift_op_ are initialized.
1562
+ ASSERT(!x.rm_.is(pc));
1563
+ if ((am & P) == 0) // post indexing
1564
+ mov(dst, Operand(x.rn_), s, cond);
1565
+ else if ((am & U) == 0) // negative indexing
1566
+ sub(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
1567
+ else
1568
+ add(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
1569
+ }
1570
+ }
1571
+
1572
+
1573
+ bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
1574
+ uint32_t dummy1;
1575
+ uint32_t dummy2;
1576
+ return fits_shifter(imm32, &dummy1, &dummy2, NULL);
1577
+ }
1578
+
1579
+
1580
+ void Assembler::BlockConstPoolFor(int instructions) {
1581
+ BlockConstPoolBefore(pc_offset() + instructions * kInstrSize);
1582
+ }
1583
+
1584
+
1585
+ // Debugging
1586
+ void Assembler::RecordJSReturn() {
1587
+ WriteRecordedPositions();
1588
+ CheckBuffer();
1589
+ RecordRelocInfo(RelocInfo::JS_RETURN);
1590
+ }
1591
+
1592
+
1593
+ void Assembler::RecordComment(const char* msg) {
1594
+ if (FLAG_debug_code) {
1595
+ CheckBuffer();
1596
+ RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
1597
+ }
1598
+ }
1599
+
1600
+
1601
+ void Assembler::RecordPosition(int pos) {
1602
+ if (pos == RelocInfo::kNoPosition) return;
1603
+ ASSERT(pos >= 0);
1604
+ current_position_ = pos;
1605
+ }
1606
+
1607
+
1608
+ void Assembler::RecordStatementPosition(int pos) {
1609
+ if (pos == RelocInfo::kNoPosition) return;
1610
+ ASSERT(pos >= 0);
1611
+ current_statement_position_ = pos;
1612
+ }
1613
+
1614
+
1615
+ void Assembler::WriteRecordedPositions() {
1616
+ // Write the statement position if it is different from what was written last
1617
+ // time.
1618
+ if (current_statement_position_ != written_statement_position_) {
1619
+ CheckBuffer();
1620
+ RecordRelocInfo(RelocInfo::STATEMENT_POSITION, current_statement_position_);
1621
+ written_statement_position_ = current_statement_position_;
1622
+ }
1623
+
1624
+ // Write the position if it is different from what was written last time and
1625
+ // also different from the written statement position.
1626
+ if (current_position_ != written_position_ &&
1627
+ current_position_ != written_statement_position_) {
1628
+ CheckBuffer();
1629
+ RecordRelocInfo(RelocInfo::POSITION, current_position_);
1630
+ written_position_ = current_position_;
1631
+ }
1632
+ }
1633
+
1634
+
1635
+ void Assembler::GrowBuffer() {
1636
+ if (!own_buffer_) FATAL("external code buffer is too small");
1637
+
1638
+ // compute new buffer size
1639
+ CodeDesc desc; // the new buffer
1640
+ if (buffer_size_ < 4*KB) {
1641
+ desc.buffer_size = 4*KB;
1642
+ } else if (buffer_size_ < 1*MB) {
1643
+ desc.buffer_size = 2*buffer_size_;
1644
+ } else {
1645
+ desc.buffer_size = buffer_size_ + 1*MB;
1646
+ }
1647
+ CHECK_GT(desc.buffer_size, 0); // no overflow
1648
+
1649
+ // setup new buffer
1650
+ desc.buffer = NewArray<byte>(desc.buffer_size);
1651
+
1652
+ desc.instr_size = pc_offset();
1653
+ desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
1654
+
1655
+ // copy the data
1656
+ int pc_delta = desc.buffer - buffer_;
1657
+ int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
1658
+ memmove(desc.buffer, buffer_, desc.instr_size);
1659
+ memmove(reloc_info_writer.pos() + rc_delta,
1660
+ reloc_info_writer.pos(), desc.reloc_size);
1661
+
1662
+ // switch buffers
1663
+ DeleteArray(buffer_);
1664
+ buffer_ = desc.buffer;
1665
+ buffer_size_ = desc.buffer_size;
1666
+ pc_ += pc_delta;
1667
+ reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
1668
+ reloc_info_writer.last_pc() + pc_delta);
1669
+
1670
+ // none of our relocation types are pc relative pointing outside the code
1671
+ // buffer nor pc absolute pointing inside the code buffer, so there is no need
1672
+ // to relocate any emitted relocation entries
1673
+
1674
+ // relocate pending relocation entries
1675
+ for (int i = 0; i < num_prinfo_; i++) {
1676
+ RelocInfo& rinfo = prinfo_[i];
1677
+ ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
1678
+ rinfo.rmode() != RelocInfo::POSITION);
1679
+ if (rinfo.rmode() != RelocInfo::JS_RETURN) {
1680
+ rinfo.set_pc(rinfo.pc() + pc_delta);
1681
+ }
1682
+ }
1683
+ }
1684
+
1685
+
1686
+ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
1687
+ RelocInfo rinfo(pc_, rmode, data); // we do not try to reuse pool constants
1688
+ if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::STATEMENT_POSITION) {
1689
+ // Adjust code for new modes
1690
+ ASSERT(RelocInfo::IsJSReturn(rmode)
1691
+ || RelocInfo::IsComment(rmode)
1692
+ || RelocInfo::IsPosition(rmode));
1693
+ // these modes do not need an entry in the constant pool
1694
+ } else {
1695
+ ASSERT(num_prinfo_ < kMaxNumPRInfo);
1696
+ prinfo_[num_prinfo_++] = rinfo;
1697
+ // Make sure the constant pool is not emitted in place of the next
1698
+ // instruction for which we just recorded relocation info
1699
+ BlockConstPoolBefore(pc_offset() + kInstrSize);
1700
+ }
1701
+ if (rinfo.rmode() != RelocInfo::NONE) {
1702
+ // Don't record external references unless the heap will be serialized.
1703
+ if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
1704
+ #ifdef DEBUG
1705
+ if (!Serializer::enabled()) {
1706
+ Serializer::TooLateToEnableNow();
1707
+ }
1708
+ #endif
1709
+ if (!Serializer::enabled() && !FLAG_debug_code) {
1710
+ return;
1711
+ }
1712
+ }
1713
+ ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here
1714
+ reloc_info_writer.Write(&rinfo);
1715
+ }
1716
+ }
1717
+
1718
+
1719
+ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
1720
+ // Calculate the offset of the next check. It will be overwritten
1721
+ // when a const pool is generated or when const pools are being
1722
+ // blocked for a specific range.
1723
+ next_buffer_check_ = pc_offset() + kCheckConstInterval;
1724
+
1725
+ // There is nothing to do if there are no pending relocation info entries
1726
+ if (num_prinfo_ == 0) return;
1727
+
1728
+ // We emit a constant pool at regular intervals of about kDistBetweenPools
1729
+ // or when requested by parameter force_emit (e.g. after each function).
1730
+ // We prefer not to emit a jump unless the max distance is reached or if we
1731
+ // are running low on slots, which can happen if a lot of constants are being
1732
+ // emitted (e.g. --debug-code and many static references).
1733
+ int dist = pc_offset() - last_const_pool_end_;
1734
+ if (!force_emit && dist < kMaxDistBetweenPools &&
1735
+ (require_jump || dist < kDistBetweenPools) &&
1736
+ // TODO(1236125): Cleanup the "magic" number below. We know that
1737
+ // the code generation will test every kCheckConstIntervalInst.
1738
+ // Thus we are safe as long as we generate less than 7 constant
1739
+ // entries per instruction.
1740
+ (num_prinfo_ < (kMaxNumPRInfo - (7 * kCheckConstIntervalInst)))) {
1741
+ return;
1742
+ }
1743
+
1744
+ // If we did not return by now, we need to emit the constant pool soon.
1745
+
1746
+ // However, some small sequences of instructions must not be broken up by the
1747
+ // insertion of a constant pool; such sequences are protected by setting
1748
+ // no_const_pool_before_, which is checked here. Also, recursive calls to
1749
+ // CheckConstPool are blocked by no_const_pool_before_.
1750
+ if (pc_offset() < no_const_pool_before_) {
1751
+ // Emission is currently blocked; make sure we try again as soon as possible
1752
+ next_buffer_check_ = no_const_pool_before_;
1753
+
1754
+ // Something is wrong if emission is forced and blocked at the same time
1755
+ ASSERT(!force_emit);
1756
+ return;
1757
+ }
1758
+
1759
+ int jump_instr = require_jump ? kInstrSize : 0;
1760
+
1761
+ // Check that the code buffer is large enough before emitting the constant
1762
+ // pool and relocation information (include the jump over the pool and the
1763
+ // constant pool marker).
1764
+ int max_needed_space =
1765
+ jump_instr + kInstrSize + num_prinfo_*(kInstrSize + kMaxRelocSize);
1766
+ while (buffer_space() <= (max_needed_space + kGap)) GrowBuffer();
1767
+
1768
+ // Block recursive calls to CheckConstPool
1769
+ BlockConstPoolBefore(pc_offset() + jump_instr + kInstrSize +
1770
+ num_prinfo_*kInstrSize);
1771
+ // Don't bother to check for the emit calls below.
1772
+ next_buffer_check_ = no_const_pool_before_;
1773
+
1774
+ // Emit jump over constant pool if necessary
1775
+ Label after_pool;
1776
+ if (require_jump) b(&after_pool);
1777
+
1778
+ RecordComment("[ Constant Pool");
1779
+
1780
+ // Put down constant pool marker
1781
+ // "Undefined instruction" as specified by A3.1 Instruction set encoding
1782
+ emit(0x03000000 | num_prinfo_);
1783
+
1784
+ // Emit constant pool entries
1785
+ for (int i = 0; i < num_prinfo_; i++) {
1786
+ RelocInfo& rinfo = prinfo_[i];
1787
+ ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
1788
+ rinfo.rmode() != RelocInfo::POSITION &&
1789
+ rinfo.rmode() != RelocInfo::STATEMENT_POSITION);
1790
+ Instr instr = instr_at(rinfo.pc());
1791
+
1792
+ // Instruction to patch must be a ldr/str [pc, #offset]
1793
+ // P and U set, B and W clear, Rn == pc, offset12 still 0
1794
+ ASSERT((instr & (7*B25 | P | U | B | W | 15*B16 | Off12Mask)) ==
1795
+ (2*B25 | P | U | pc.code()*B16));
1796
+ int delta = pc_ - rinfo.pc() - 8;
1797
+ ASSERT(delta >= -4); // instr could be ldr pc, [pc, #-4] followed by targ32
1798
+ if (delta < 0) {
1799
+ instr &= ~U;
1800
+ delta = -delta;
1801
+ }
1802
+ ASSERT(is_uint12(delta));
1803
+ instr_at_put(rinfo.pc(), instr + delta);
1804
+ emit(rinfo.data());
1805
+ }
1806
+ num_prinfo_ = 0;
1807
+ last_const_pool_end_ = pc_offset();
1808
+
1809
+ RecordComment("]");
1810
+
1811
+ if (after_pool.is_linked()) {
1812
+ bind(&after_pool);
1813
+ }
1814
+
1815
+ // Since a constant pool was just emitted, move the check offset forward by
1816
+ // the standard interval.
1817
+ next_buffer_check_ = pc_offset() + kCheckConstInterval;
1818
+ }
1819
+
1820
+
1821
+ } } // namespace v8::internal