therubyracer-heroku 0.8.1.pre2
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- data/.gitignore +13 -0
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- data/.rspec +1 -0
- data/Changelog.md +165 -0
- data/Gemfile +1 -0
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- data/ext/v8/upstream/scons/engine/SCons/Tool/g++.py +90 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/g77.py +73 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/gas.py +53 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/gcc.py +80 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/gfortran.py +64 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/gnulink.py +63 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/gs.py +81 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/hpc++.py +85 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/hpcc.py +53 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/hplink.py +77 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/icc.py +59 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/icl.py +52 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/ifl.py +72 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/ifort.py +90 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/ilink.py +59 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/ilink32.py +60 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/install.py +229 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/intelc.py +490 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/ipkg.py +71 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/jar.py +110 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/javac.py +234 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/javah.py +138 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/latex.py +79 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/lex.py +99 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/link.py +121 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/linkloc.py +112 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/m4.py +63 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/masm.py +77 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/midl.py +90 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/mingw.py +159 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/mslib.py +64 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/mslink.py +266 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/mssdk.py +50 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/msvc.py +269 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/msvs.py +1439 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/mwcc.py +208 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/mwld.py +107 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/nasm.py +72 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/__init__.py +314 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/ipk.py +185 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/msi.py +526 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/rpm.py +367 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/src_tarbz2.py +43 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/src_targz.py +43 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/src_zip.py +43 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/tarbz2.py +44 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/targz.py +44 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/packaging/zip.py +44 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/pdf.py +78 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/pdflatex.py +83 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/pdftex.py +108 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/qt.py +336 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/rmic.py +121 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/rpcgen.py +70 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/rpm.py +132 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sgiar.py +68 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sgic++.py +58 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sgicc.py +53 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sgilink.py +63 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sunar.py +67 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sunc++.py +142 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/suncc.py +58 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sunf77.py +63 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sunf90.py +64 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sunf95.py +64 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/sunlink.py +77 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/swig.py +186 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/tar.py +73 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/tex.py +805 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/textfile.py +175 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/tlib.py +53 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/wix.py +100 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/yacc.py +131 -0
- data/ext/v8/upstream/scons/engine/SCons/Tool/zip.py +100 -0
- data/ext/v8/upstream/scons/engine/SCons/Util.py +1645 -0
- data/ext/v8/upstream/scons/engine/SCons/Variables/BoolVariable.py +91 -0
- data/ext/v8/upstream/scons/engine/SCons/Variables/EnumVariable.py +107 -0
- data/ext/v8/upstream/scons/engine/SCons/Variables/ListVariable.py +139 -0
- data/ext/v8/upstream/scons/engine/SCons/Variables/PackageVariable.py +109 -0
- data/ext/v8/upstream/scons/engine/SCons/Variables/PathVariable.py +147 -0
- data/ext/v8/upstream/scons/engine/SCons/Variables/__init__.py +317 -0
- data/ext/v8/upstream/scons/engine/SCons/Warnings.py +228 -0
- data/ext/v8/upstream/scons/engine/SCons/__init__.py +49 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/__init__.py +302 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_UserString.py +98 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_hashlib.py +91 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_itertools.py +124 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_optparse.py +1725 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_sets.py +583 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_sets15.py +176 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_shlex.py +325 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_subprocess.py +1296 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/_scons_textwrap.py +382 -0
- data/ext/v8/upstream/scons/engine/SCons/compat/builtins.py +187 -0
- data/ext/v8/upstream/scons/engine/SCons/cpp.py +598 -0
- data/ext/v8/upstream/scons/engine/SCons/dblite.py +248 -0
- data/ext/v8/upstream/scons/engine/SCons/exitfuncs.py +77 -0
- data/ext/v8/upstream/scons/os_spawnv_fix.diff +83 -0
- data/ext/v8/upstream/scons/scons-time.1 +1017 -0
- data/ext/v8/upstream/scons/scons.1 +15179 -0
- data/ext/v8/upstream/scons/sconsign.1 +208 -0
- data/ext/v8/upstream/scons/script/scons +184 -0
- data/ext/v8/upstream/scons/script/scons-time +1529 -0
- data/ext/v8/upstream/scons/script/scons.bat +31 -0
- data/ext/v8/upstream/scons/script/sconsign +508 -0
- data/ext/v8/upstream/scons/setup.cfg +6 -0
- data/ext/v8/upstream/scons/setup.py +427 -0
- data/ext/v8/v8.cpp +41 -0
- data/ext/v8/v8_array.cpp +50 -0
- data/ext/v8/v8_array.h +8 -0
- data/ext/v8/v8_callbacks.cpp +121 -0
- data/ext/v8/v8_callbacks.h +8 -0
- data/ext/v8/v8_cxt.cpp +92 -0
- data/ext/v8/v8_cxt.h +6 -0
- data/ext/v8/v8_date.cpp +35 -0
- data/ext/v8/v8_date.h +6 -0
- data/ext/v8/v8_exception.cpp +128 -0
- data/ext/v8/v8_exception.h +11 -0
- data/ext/v8/v8_external.cpp +57 -0
- data/ext/v8/v8_external.h +9 -0
- data/ext/v8/v8_func.cpp +66 -0
- data/ext/v8/v8_func.h +12 -0
- data/ext/v8/v8_locker.cpp +41 -0
- data/ext/v8/v8_locker.h +6 -0
- data/ext/v8/v8_msg.cpp +68 -0
- data/ext/v8/v8_msg.h +10 -0
- data/ext/v8/v8_obj.cpp +96 -0
- data/ext/v8/v8_obj.h +11 -0
- data/ext/v8/v8_ref.cpp +37 -0
- data/ext/v8/v8_ref.h +28 -0
- data/ext/v8/v8_script.cpp +36 -0
- data/ext/v8/v8_script.h +8 -0
- data/ext/v8/v8_str.cpp +52 -0
- data/ext/v8/v8_str.h +9 -0
- data/ext/v8/v8_template.cpp +329 -0
- data/ext/v8/v8_template.h +8 -0
- data/ext/v8/v8_try_catch.cpp +99 -0
- data/ext/v8/v8_try_catch.h +5 -0
- data/ext/v8/v8_value.cpp +167 -0
- data/ext/v8/v8_value.h +10 -0
- data/lib/v8.rb +16 -0
- data/lib/v8/access.rb +87 -0
- data/lib/v8/array.rb +17 -0
- data/lib/v8/cli.rb +131 -0
- data/lib/v8/context.rb +88 -0
- data/lib/v8/error.rb +129 -0
- data/lib/v8/function.rb +28 -0
- data/lib/v8/object.rb +69 -0
- data/lib/v8/portal.rb +327 -0
- data/lib/v8/portal/functions.rb +45 -0
- data/lib/v8/tap.rb +9 -0
- data/lib/v8/version.rb +3 -0
- data/spec/ext/cxt_spec.rb +12 -0
- data/spec/ext/func_spec.rb +49 -0
- data/spec/ext/try_catch_spec.rb +32 -0
- data/spec/redjs_helper.rb +3 -0
- data/spec/spec_helper.rb +8 -0
- data/spec/v8/error_spec.rb +131 -0
- data/therubyracer-heroku.gemspec +24 -0
- metadata +2061 -0
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// Copyright 2010 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <stdlib.h>
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#include <math.h>
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#include <cstdarg>
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#include "v8.h"
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#if defined(V8_TARGET_ARCH_ARM)
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#include "disasm.h"
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#include "assembler.h"
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#include "arm/constants-arm.h"
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#include "arm/simulator-arm.h"
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#if !defined(__arm__)
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// Only build the simulator if not compiling for real ARM hardware.
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namespace assembler {
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namespace arm {
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using ::v8::internal::Object;
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using ::v8::internal::PrintF;
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using ::v8::internal::OS;
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using ::v8::internal::ReadLine;
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using ::v8::internal::DeleteArray;
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// This macro provides a platform independent use of sscanf. The reason for
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// SScanF not being implemented in a platform independent way through
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// ::v8::internal::OS in the same way as SNPrintF is that the
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// Windows C Run-Time Library does not provide vsscanf.
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#define SScanF sscanf // NOLINT
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// The Debugger class is used by the simulator while debugging simulated ARM
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// code.
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class Debugger {
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public:
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explicit Debugger(Simulator* sim);
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~Debugger();
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void Stop(Instr* instr);
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void Debug();
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private:
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static const instr_t kBreakpointInstr =
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((AL << 28) | (7 << 25) | (1 << 24) | break_point);
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static const instr_t kNopInstr =
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((AL << 28) | (13 << 21));
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Simulator* sim_;
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int32_t GetRegisterValue(int regnum);
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bool GetValue(const char* desc, int32_t* value);
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bool GetVFPSingleValue(const char* desc, float* value);
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bool GetVFPDoubleValue(const char* desc, double* value);
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// Set or delete a breakpoint. Returns true if successful.
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bool SetBreakpoint(Instr* breakpc);
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bool DeleteBreakpoint(Instr* breakpc);
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// Undo and redo all breakpoints. This is needed to bracket disassembly and
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// execution to skip past breakpoints when run from the debugger.
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void UndoBreakpoints();
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void RedoBreakpoints();
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};
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Debugger::Debugger(Simulator* sim) {
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sim_ = sim;
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}
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Debugger::~Debugger() {
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}
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static FILE* coverage_log = NULL;
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static void InitializeCoverage() {
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char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
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if (file_name != NULL) {
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coverage_log = fopen(file_name, "aw+");
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}
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}
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void Debugger::Stop(Instr* instr) {
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char* str = reinterpret_cast<char*>(instr->InstructionBits() & 0x0fffffff);
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if (strlen(str) > 0) {
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if (coverage_log != NULL) {
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fprintf(coverage_log, "%s\n", str);
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fflush(coverage_log);
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}
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instr->SetInstructionBits(0xe1a00000); // Overwrite with nop.
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}
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sim_->set_pc(sim_->get_pc() + Instr::kInstrSize);
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}
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#else // ndef GENERATED_CODE_COVERAGE
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static void InitializeCoverage() {
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}
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void Debugger::Stop(Instr* instr) {
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const char* str = (const char*)(instr->InstructionBits() & 0x0fffffff);
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PrintF("Simulator hit %s\n", str);
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sim_->set_pc(sim_->get_pc() + Instr::kInstrSize);
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Debug();
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}
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#endif
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int32_t Debugger::GetRegisterValue(int regnum) {
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if (regnum == kPCRegister) {
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return sim_->get_pc();
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} else {
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return sim_->get_register(regnum);
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}
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}
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bool Debugger::GetValue(const char* desc, int32_t* value) {
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int regnum = Registers::Number(desc);
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if (regnum != kNoRegister) {
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*value = GetRegisterValue(regnum);
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return true;
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} else {
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if (strncmp(desc, "0x", 2) == 0) {
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return SScanF(desc + 2, "%x", reinterpret_cast<uint32_t*>(value)) == 1;
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} else {
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return SScanF(desc, "%u", reinterpret_cast<uint32_t*>(value)) == 1;
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}
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}
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return false;
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}
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bool Debugger::GetVFPSingleValue(const char* desc, float* value) {
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bool is_double;
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int regnum = VFPRegisters::Number(desc, &is_double);
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if (regnum != kNoRegister && !is_double) {
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*value = sim_->get_float_from_s_register(regnum);
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return true;
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}
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return false;
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}
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bool Debugger::GetVFPDoubleValue(const char* desc, double* value) {
|
178
|
+
bool is_double;
|
179
|
+
int regnum = VFPRegisters::Number(desc, &is_double);
|
180
|
+
if (regnum != kNoRegister && is_double) {
|
181
|
+
*value = sim_->get_double_from_d_register(regnum);
|
182
|
+
return true;
|
183
|
+
}
|
184
|
+
return false;
|
185
|
+
}
|
186
|
+
|
187
|
+
|
188
|
+
bool Debugger::SetBreakpoint(Instr* breakpc) {
|
189
|
+
// Check if a breakpoint can be set. If not return without any side-effects.
|
190
|
+
if (sim_->break_pc_ != NULL) {
|
191
|
+
return false;
|
192
|
+
}
|
193
|
+
|
194
|
+
// Set the breakpoint.
|
195
|
+
sim_->break_pc_ = breakpc;
|
196
|
+
sim_->break_instr_ = breakpc->InstructionBits();
|
197
|
+
// Not setting the breakpoint instruction in the code itself. It will be set
|
198
|
+
// when the debugger shell continues.
|
199
|
+
return true;
|
200
|
+
}
|
201
|
+
|
202
|
+
|
203
|
+
bool Debugger::DeleteBreakpoint(Instr* breakpc) {
|
204
|
+
if (sim_->break_pc_ != NULL) {
|
205
|
+
sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
|
206
|
+
}
|
207
|
+
|
208
|
+
sim_->break_pc_ = NULL;
|
209
|
+
sim_->break_instr_ = 0;
|
210
|
+
return true;
|
211
|
+
}
|
212
|
+
|
213
|
+
|
214
|
+
void Debugger::UndoBreakpoints() {
|
215
|
+
if (sim_->break_pc_ != NULL) {
|
216
|
+
sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
|
217
|
+
}
|
218
|
+
}
|
219
|
+
|
220
|
+
|
221
|
+
void Debugger::RedoBreakpoints() {
|
222
|
+
if (sim_->break_pc_ != NULL) {
|
223
|
+
sim_->break_pc_->SetInstructionBits(kBreakpointInstr);
|
224
|
+
}
|
225
|
+
}
|
226
|
+
|
227
|
+
|
228
|
+
void Debugger::Debug() {
|
229
|
+
intptr_t last_pc = -1;
|
230
|
+
bool done = false;
|
231
|
+
|
232
|
+
#define COMMAND_SIZE 63
|
233
|
+
#define ARG_SIZE 255
|
234
|
+
|
235
|
+
#define STR(a) #a
|
236
|
+
#define XSTR(a) STR(a)
|
237
|
+
|
238
|
+
char cmd[COMMAND_SIZE + 1];
|
239
|
+
char arg1[ARG_SIZE + 1];
|
240
|
+
char arg2[ARG_SIZE + 1];
|
241
|
+
char* argv[3] = { cmd, arg1, arg2 };
|
242
|
+
|
243
|
+
// make sure to have a proper terminating character if reaching the limit
|
244
|
+
cmd[COMMAND_SIZE] = 0;
|
245
|
+
arg1[ARG_SIZE] = 0;
|
246
|
+
arg2[ARG_SIZE] = 0;
|
247
|
+
|
248
|
+
// Undo all set breakpoints while running in the debugger shell. This will
|
249
|
+
// make them invisible to all commands.
|
250
|
+
UndoBreakpoints();
|
251
|
+
|
252
|
+
while (!done) {
|
253
|
+
if (last_pc != sim_->get_pc()) {
|
254
|
+
disasm::NameConverter converter;
|
255
|
+
disasm::Disassembler dasm(converter);
|
256
|
+
// use a reasonably large buffer
|
257
|
+
v8::internal::EmbeddedVector<char, 256> buffer;
|
258
|
+
dasm.InstructionDecode(buffer,
|
259
|
+
reinterpret_cast<byte*>(sim_->get_pc()));
|
260
|
+
PrintF(" 0x%08x %s\n", sim_->get_pc(), buffer.start());
|
261
|
+
last_pc = sim_->get_pc();
|
262
|
+
}
|
263
|
+
char* line = ReadLine("sim> ");
|
264
|
+
if (line == NULL) {
|
265
|
+
break;
|
266
|
+
} else {
|
267
|
+
// Use sscanf to parse the individual parts of the command line. At the
|
268
|
+
// moment no command expects more than two parameters.
|
269
|
+
int argc = SScanF(line,
|
270
|
+
"%" XSTR(COMMAND_SIZE) "s "
|
271
|
+
"%" XSTR(ARG_SIZE) "s "
|
272
|
+
"%" XSTR(ARG_SIZE) "s",
|
273
|
+
cmd, arg1, arg2);
|
274
|
+
if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
|
275
|
+
sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
|
276
|
+
} else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
|
277
|
+
// Execute the one instruction we broke at with breakpoints disabled.
|
278
|
+
sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
|
279
|
+
// Leave the debugger shell.
|
280
|
+
done = true;
|
281
|
+
} else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
|
282
|
+
if (argc == 2) {
|
283
|
+
int32_t value;
|
284
|
+
float svalue;
|
285
|
+
double dvalue;
|
286
|
+
if (strcmp(arg1, "all") == 0) {
|
287
|
+
for (int i = 0; i < kNumRegisters; i++) {
|
288
|
+
value = GetRegisterValue(i);
|
289
|
+
PrintF("%3s: 0x%08x %10d\n", Registers::Name(i), value, value);
|
290
|
+
}
|
291
|
+
} else {
|
292
|
+
if (GetValue(arg1, &value)) {
|
293
|
+
PrintF("%s: 0x%08x %d \n", arg1, value, value);
|
294
|
+
} else if (GetVFPSingleValue(arg1, &svalue)) {
|
295
|
+
PrintF("%s: %f \n", arg1, svalue);
|
296
|
+
} else if (GetVFPDoubleValue(arg1, &dvalue)) {
|
297
|
+
PrintF("%s: %lf \n", arg1, dvalue);
|
298
|
+
} else {
|
299
|
+
PrintF("%s unrecognized\n", arg1);
|
300
|
+
}
|
301
|
+
}
|
302
|
+
} else {
|
303
|
+
PrintF("print <register>\n");
|
304
|
+
}
|
305
|
+
} else if ((strcmp(cmd, "po") == 0)
|
306
|
+
|| (strcmp(cmd, "printobject") == 0)) {
|
307
|
+
if (argc == 2) {
|
308
|
+
int32_t value;
|
309
|
+
if (GetValue(arg1, &value)) {
|
310
|
+
Object* obj = reinterpret_cast<Object*>(value);
|
311
|
+
PrintF("%s: \n", arg1);
|
312
|
+
#ifdef DEBUG
|
313
|
+
obj->PrintLn();
|
314
|
+
#else
|
315
|
+
obj->ShortPrint();
|
316
|
+
PrintF("\n");
|
317
|
+
#endif
|
318
|
+
} else {
|
319
|
+
PrintF("%s unrecognized\n", arg1);
|
320
|
+
}
|
321
|
+
} else {
|
322
|
+
PrintF("printobject <value>\n");
|
323
|
+
}
|
324
|
+
} else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
|
325
|
+
int32_t* cur = NULL;
|
326
|
+
int32_t* end = NULL;
|
327
|
+
int next_arg = 1;
|
328
|
+
|
329
|
+
if (strcmp(cmd, "stack") == 0) {
|
330
|
+
cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp));
|
331
|
+
} else { // "mem"
|
332
|
+
int32_t value;
|
333
|
+
if (!GetValue(arg1, &value)) {
|
334
|
+
PrintF("%s unrecognized\n", arg1);
|
335
|
+
continue;
|
336
|
+
}
|
337
|
+
cur = reinterpret_cast<int32_t*>(value);
|
338
|
+
next_arg++;
|
339
|
+
}
|
340
|
+
|
341
|
+
int32_t words;
|
342
|
+
if (argc == next_arg) {
|
343
|
+
words = 10;
|
344
|
+
} else if (argc == next_arg + 1) {
|
345
|
+
if (!GetValue(argv[next_arg], &words)) {
|
346
|
+
words = 10;
|
347
|
+
}
|
348
|
+
}
|
349
|
+
end = cur + words;
|
350
|
+
|
351
|
+
while (cur < end) {
|
352
|
+
PrintF(" 0x%08x: 0x%08x %10d\n", cur, *cur, *cur);
|
353
|
+
cur++;
|
354
|
+
}
|
355
|
+
} else if (strcmp(cmd, "disasm") == 0) {
|
356
|
+
disasm::NameConverter converter;
|
357
|
+
disasm::Disassembler dasm(converter);
|
358
|
+
// use a reasonably large buffer
|
359
|
+
v8::internal::EmbeddedVector<char, 256> buffer;
|
360
|
+
|
361
|
+
byte* cur = NULL;
|
362
|
+
byte* end = NULL;
|
363
|
+
|
364
|
+
if (argc == 1) {
|
365
|
+
cur = reinterpret_cast<byte*>(sim_->get_pc());
|
366
|
+
end = cur + (10 * Instr::kInstrSize);
|
367
|
+
} else if (argc == 2) {
|
368
|
+
int32_t value;
|
369
|
+
if (GetValue(arg1, &value)) {
|
370
|
+
cur = reinterpret_cast<byte*>(value);
|
371
|
+
// no length parameter passed, assume 10 instructions
|
372
|
+
end = cur + (10 * Instr::kInstrSize);
|
373
|
+
}
|
374
|
+
} else {
|
375
|
+
int32_t value1;
|
376
|
+
int32_t value2;
|
377
|
+
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
|
378
|
+
cur = reinterpret_cast<byte*>(value1);
|
379
|
+
end = cur + (value2 * Instr::kInstrSize);
|
380
|
+
}
|
381
|
+
}
|
382
|
+
|
383
|
+
while (cur < end) {
|
384
|
+
dasm.InstructionDecode(buffer, cur);
|
385
|
+
PrintF(" 0x%08x %s\n", cur, buffer.start());
|
386
|
+
cur += Instr::kInstrSize;
|
387
|
+
}
|
388
|
+
} else if (strcmp(cmd, "gdb") == 0) {
|
389
|
+
PrintF("relinquishing control to gdb\n");
|
390
|
+
v8::internal::OS::DebugBreak();
|
391
|
+
PrintF("regaining control from gdb\n");
|
392
|
+
} else if (strcmp(cmd, "break") == 0) {
|
393
|
+
if (argc == 2) {
|
394
|
+
int32_t value;
|
395
|
+
if (GetValue(arg1, &value)) {
|
396
|
+
if (!SetBreakpoint(reinterpret_cast<Instr*>(value))) {
|
397
|
+
PrintF("setting breakpoint failed\n");
|
398
|
+
}
|
399
|
+
} else {
|
400
|
+
PrintF("%s unrecognized\n", arg1);
|
401
|
+
}
|
402
|
+
} else {
|
403
|
+
PrintF("break <address>\n");
|
404
|
+
}
|
405
|
+
} else if (strcmp(cmd, "del") == 0) {
|
406
|
+
if (!DeleteBreakpoint(NULL)) {
|
407
|
+
PrintF("deleting breakpoint failed\n");
|
408
|
+
}
|
409
|
+
} else if (strcmp(cmd, "flags") == 0) {
|
410
|
+
PrintF("N flag: %d; ", sim_->n_flag_);
|
411
|
+
PrintF("Z flag: %d; ", sim_->z_flag_);
|
412
|
+
PrintF("C flag: %d; ", sim_->c_flag_);
|
413
|
+
PrintF("V flag: %d\n", sim_->v_flag_);
|
414
|
+
PrintF("INVALID OP flag: %d; ", sim_->inv_op_vfp_flag_);
|
415
|
+
PrintF("DIV BY ZERO flag: %d; ", sim_->div_zero_vfp_flag_);
|
416
|
+
PrintF("OVERFLOW flag: %d; ", sim_->overflow_vfp_flag_);
|
417
|
+
PrintF("UNDERFLOW flag: %d; ", sim_->underflow_vfp_flag_);
|
418
|
+
PrintF("INEXACT flag: %d; ", sim_->inexact_vfp_flag_);
|
419
|
+
} else if (strcmp(cmd, "unstop") == 0) {
|
420
|
+
intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize;
|
421
|
+
Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc);
|
422
|
+
if (stop_instr->ConditionField() == special_condition) {
|
423
|
+
stop_instr->SetInstructionBits(kNopInstr);
|
424
|
+
} else {
|
425
|
+
PrintF("Not at debugger stop.");
|
426
|
+
}
|
427
|
+
} else if ((strcmp(cmd, "t") == 0) || strcmp(cmd, "trace") == 0) {
|
428
|
+
::v8::internal::FLAG_trace_sim = !::v8::internal::FLAG_trace_sim;
|
429
|
+
PrintF("Trace of executed instructions is %s\n",
|
430
|
+
::v8::internal::FLAG_trace_sim ? "on" : "off");
|
431
|
+
} else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
|
432
|
+
PrintF("cont\n");
|
433
|
+
PrintF(" continue execution (alias 'c')\n");
|
434
|
+
PrintF("stepi\n");
|
435
|
+
PrintF(" step one instruction (alias 'si')\n");
|
436
|
+
PrintF("print <register>\n");
|
437
|
+
PrintF(" print register content (alias 'p')\n");
|
438
|
+
PrintF(" use register name 'all' to print all registers\n");
|
439
|
+
PrintF("printobject <register>\n");
|
440
|
+
PrintF(" print an object from a register (alias 'po')\n");
|
441
|
+
PrintF("flags\n");
|
442
|
+
PrintF(" print flags\n");
|
443
|
+
PrintF("stack [<words>]\n");
|
444
|
+
PrintF(" dump stack content, default dump 10 words)\n");
|
445
|
+
PrintF("mem <address> [<words>]\n");
|
446
|
+
PrintF(" dump memory content, default dump 10 words)\n");
|
447
|
+
PrintF("disasm [<instructions>]\n");
|
448
|
+
PrintF("disasm [[<address>] <instructions>]\n");
|
449
|
+
PrintF(" disassemble code, default is 10 instructions from pc\n");
|
450
|
+
PrintF("gdb\n");
|
451
|
+
PrintF(" enter gdb\n");
|
452
|
+
PrintF("break <address>\n");
|
453
|
+
PrintF(" set a break point on the address\n");
|
454
|
+
PrintF("del\n");
|
455
|
+
PrintF(" delete the breakpoint\n");
|
456
|
+
PrintF("unstop\n");
|
457
|
+
PrintF(" ignore the stop instruction at the current location");
|
458
|
+
PrintF(" from now on\n");
|
459
|
+
PrintF("trace (alias 't')\n");
|
460
|
+
PrintF(" toogle the tracing of all executed statements\n");
|
461
|
+
} else {
|
462
|
+
PrintF("Unknown command: %s\n", cmd);
|
463
|
+
}
|
464
|
+
}
|
465
|
+
DeleteArray(line);
|
466
|
+
}
|
467
|
+
|
468
|
+
// Add all the breakpoints back to stop execution and enter the debugger
|
469
|
+
// shell when hit.
|
470
|
+
RedoBreakpoints();
|
471
|
+
|
472
|
+
#undef COMMAND_SIZE
|
473
|
+
#undef ARG_SIZE
|
474
|
+
|
475
|
+
#undef STR
|
476
|
+
#undef XSTR
|
477
|
+
}
|
478
|
+
|
479
|
+
|
480
|
+
static bool ICacheMatch(void* one, void* two) {
|
481
|
+
ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
|
482
|
+
ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
|
483
|
+
return one == two;
|
484
|
+
}
|
485
|
+
|
486
|
+
|
487
|
+
static uint32_t ICacheHash(void* key) {
|
488
|
+
return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
|
489
|
+
}
|
490
|
+
|
491
|
+
|
492
|
+
static bool AllOnOnePage(uintptr_t start, int size) {
|
493
|
+
intptr_t start_page = (start & ~CachePage::kPageMask);
|
494
|
+
intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
|
495
|
+
return start_page == end_page;
|
496
|
+
}
|
497
|
+
|
498
|
+
|
499
|
+
void Simulator::FlushICache(void* start_addr, size_t size) {
|
500
|
+
intptr_t start = reinterpret_cast<intptr_t>(start_addr);
|
501
|
+
int intra_line = (start & CachePage::kLineMask);
|
502
|
+
start -= intra_line;
|
503
|
+
size += intra_line;
|
504
|
+
size = ((size - 1) | CachePage::kLineMask) + 1;
|
505
|
+
int offset = (start & CachePage::kPageMask);
|
506
|
+
while (!AllOnOnePage(start, size - 1)) {
|
507
|
+
int bytes_to_flush = CachePage::kPageSize - offset;
|
508
|
+
FlushOnePage(start, bytes_to_flush);
|
509
|
+
start += bytes_to_flush;
|
510
|
+
size -= bytes_to_flush;
|
511
|
+
ASSERT_EQ(0, start & CachePage::kPageMask);
|
512
|
+
offset = 0;
|
513
|
+
}
|
514
|
+
if (size != 0) {
|
515
|
+
FlushOnePage(start, size);
|
516
|
+
}
|
517
|
+
}
|
518
|
+
|
519
|
+
|
520
|
+
CachePage* Simulator::GetCachePage(void* page) {
|
521
|
+
v8::internal::HashMap::Entry* entry = i_cache_->Lookup(page,
|
522
|
+
ICacheHash(page),
|
523
|
+
true);
|
524
|
+
if (entry->value == NULL) {
|
525
|
+
CachePage* new_page = new CachePage();
|
526
|
+
entry->value = new_page;
|
527
|
+
}
|
528
|
+
return reinterpret_cast<CachePage*>(entry->value);
|
529
|
+
}
|
530
|
+
|
531
|
+
|
532
|
+
// Flush from start up to and not including start + size.
|
533
|
+
void Simulator::FlushOnePage(intptr_t start, int size) {
|
534
|
+
ASSERT(size <= CachePage::kPageSize);
|
535
|
+
ASSERT(AllOnOnePage(start, size - 1));
|
536
|
+
ASSERT((start & CachePage::kLineMask) == 0);
|
537
|
+
ASSERT((size & CachePage::kLineMask) == 0);
|
538
|
+
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
|
539
|
+
int offset = (start & CachePage::kPageMask);
|
540
|
+
CachePage* cache_page = GetCachePage(page);
|
541
|
+
char* valid_bytemap = cache_page->ValidityByte(offset);
|
542
|
+
memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
|
543
|
+
}
|
544
|
+
|
545
|
+
|
546
|
+
void Simulator::CheckICache(Instr* instr) {
|
547
|
+
intptr_t address = reinterpret_cast<intptr_t>(instr);
|
548
|
+
void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
|
549
|
+
void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
|
550
|
+
int offset = (address & CachePage::kPageMask);
|
551
|
+
CachePage* cache_page = GetCachePage(page);
|
552
|
+
char* cache_valid_byte = cache_page->ValidityByte(offset);
|
553
|
+
bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
|
554
|
+
char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
|
555
|
+
if (cache_hit) {
|
556
|
+
// Check that the data in memory matches the contents of the I-cache.
|
557
|
+
CHECK(memcmp(reinterpret_cast<void*>(instr),
|
558
|
+
cache_page->CachedData(offset),
|
559
|
+
Instr::kInstrSize) == 0);
|
560
|
+
} else {
|
561
|
+
// Cache miss. Load memory into the cache.
|
562
|
+
memcpy(cached_line, line, CachePage::kLineLength);
|
563
|
+
*cache_valid_byte = CachePage::LINE_VALID;
|
564
|
+
}
|
565
|
+
}
|
566
|
+
|
567
|
+
|
568
|
+
// Create one simulator per thread and keep it in thread local storage.
|
569
|
+
static v8::internal::Thread::LocalStorageKey simulator_key;
|
570
|
+
|
571
|
+
|
572
|
+
bool Simulator::initialized_ = false;
|
573
|
+
|
574
|
+
|
575
|
+
void Simulator::Initialize() {
|
576
|
+
if (initialized_) return;
|
577
|
+
simulator_key = v8::internal::Thread::CreateThreadLocalKey();
|
578
|
+
initialized_ = true;
|
579
|
+
::v8::internal::ExternalReference::set_redirector(&RedirectExternalReference);
|
580
|
+
}
|
581
|
+
|
582
|
+
|
583
|
+
v8::internal::HashMap* Simulator::i_cache_ = NULL;
|
584
|
+
|
585
|
+
|
586
|
+
Simulator::Simulator() {
|
587
|
+
if (i_cache_ == NULL) {
|
588
|
+
i_cache_ = new v8::internal::HashMap(&ICacheMatch);
|
589
|
+
}
|
590
|
+
Initialize();
|
591
|
+
// Setup simulator support first. Some of this information is needed to
|
592
|
+
// setup the architecture state.
|
593
|
+
size_t stack_size = 1 * 1024*1024; // allocate 1MB for stack
|
594
|
+
stack_ = reinterpret_cast<char*>(malloc(stack_size));
|
595
|
+
pc_modified_ = false;
|
596
|
+
icount_ = 0;
|
597
|
+
break_pc_ = NULL;
|
598
|
+
break_instr_ = 0;
|
599
|
+
|
600
|
+
// Setup architecture state.
|
601
|
+
// All registers are initialized to zero to start with.
|
602
|
+
for (int i = 0; i < num_registers; i++) {
|
603
|
+
registers_[i] = 0;
|
604
|
+
}
|
605
|
+
n_flag_ = false;
|
606
|
+
z_flag_ = false;
|
607
|
+
c_flag_ = false;
|
608
|
+
v_flag_ = false;
|
609
|
+
|
610
|
+
// Initializing VFP registers.
|
611
|
+
// All registers are initialized to zero to start with
|
612
|
+
// even though s_registers_ & d_registers_ share the same
|
613
|
+
// physical registers in the target.
|
614
|
+
for (int i = 0; i < num_s_registers; i++) {
|
615
|
+
vfp_register[i] = 0;
|
616
|
+
}
|
617
|
+
n_flag_FPSCR_ = false;
|
618
|
+
z_flag_FPSCR_ = false;
|
619
|
+
c_flag_FPSCR_ = false;
|
620
|
+
v_flag_FPSCR_ = false;
|
621
|
+
|
622
|
+
inv_op_vfp_flag_ = false;
|
623
|
+
div_zero_vfp_flag_ = false;
|
624
|
+
overflow_vfp_flag_ = false;
|
625
|
+
underflow_vfp_flag_ = false;
|
626
|
+
inexact_vfp_flag_ = false;
|
627
|
+
|
628
|
+
// The sp is initialized to point to the bottom (high address) of the
|
629
|
+
// allocated stack area. To be safe in potential stack underflows we leave
|
630
|
+
// some buffer below.
|
631
|
+
registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size - 64;
|
632
|
+
// The lr and pc are initialized to a known bad value that will cause an
|
633
|
+
// access violation if the simulator ever tries to execute it.
|
634
|
+
registers_[pc] = bad_lr;
|
635
|
+
registers_[lr] = bad_lr;
|
636
|
+
InitializeCoverage();
|
637
|
+
}
|
638
|
+
|
639
|
+
|
640
|
+
// When the generated code calls an external reference we need to catch that in
|
641
|
+
// the simulator. The external reference will be a function compiled for the
|
642
|
+
// host architecture. We need to call that function instead of trying to
|
643
|
+
// execute it with the simulator. We do that by redirecting the external
|
644
|
+
// reference to a swi (software-interrupt) instruction that is handled by
|
645
|
+
// the simulator. We write the original destination of the jump just at a known
|
646
|
+
// offset from the swi instruction so the simulator knows what to call.
|
647
|
+
class Redirection {
|
648
|
+
public:
|
649
|
+
Redirection(void* external_function, bool fp_return)
|
650
|
+
: external_function_(external_function),
|
651
|
+
swi_instruction_((AL << 28) | (0xf << 24) | call_rt_redirected),
|
652
|
+
fp_return_(fp_return),
|
653
|
+
next_(list_) {
|
654
|
+
Simulator::current()->
|
655
|
+
FlushICache(reinterpret_cast<void*>(&swi_instruction_),
|
656
|
+
Instr::kInstrSize);
|
657
|
+
list_ = this;
|
658
|
+
}
|
659
|
+
|
660
|
+
void* address_of_swi_instruction() {
|
661
|
+
return reinterpret_cast<void*>(&swi_instruction_);
|
662
|
+
}
|
663
|
+
|
664
|
+
void* external_function() { return external_function_; }
|
665
|
+
bool fp_return() { return fp_return_; }
|
666
|
+
|
667
|
+
static Redirection* Get(void* external_function, bool fp_return) {
|
668
|
+
Redirection* current;
|
669
|
+
for (current = list_; current != NULL; current = current->next_) {
|
670
|
+
if (current->external_function_ == external_function) return current;
|
671
|
+
}
|
672
|
+
return new Redirection(external_function, fp_return);
|
673
|
+
}
|
674
|
+
|
675
|
+
static Redirection* FromSwiInstruction(Instr* swi_instruction) {
|
676
|
+
char* addr_of_swi = reinterpret_cast<char*>(swi_instruction);
|
677
|
+
char* addr_of_redirection =
|
678
|
+
addr_of_swi - OFFSET_OF(Redirection, swi_instruction_);
|
679
|
+
return reinterpret_cast<Redirection*>(addr_of_redirection);
|
680
|
+
}
|
681
|
+
|
682
|
+
private:
|
683
|
+
void* external_function_;
|
684
|
+
uint32_t swi_instruction_;
|
685
|
+
bool fp_return_;
|
686
|
+
Redirection* next_;
|
687
|
+
static Redirection* list_;
|
688
|
+
};
|
689
|
+
|
690
|
+
|
691
|
+
Redirection* Redirection::list_ = NULL;
|
692
|
+
|
693
|
+
|
694
|
+
void* Simulator::RedirectExternalReference(void* external_function,
|
695
|
+
bool fp_return) {
|
696
|
+
Redirection* redirection = Redirection::Get(external_function, fp_return);
|
697
|
+
return redirection->address_of_swi_instruction();
|
698
|
+
}
|
699
|
+
|
700
|
+
|
701
|
+
// Get the active Simulator for the current thread.
|
702
|
+
Simulator* Simulator::current() {
|
703
|
+
Initialize();
|
704
|
+
Simulator* sim = reinterpret_cast<Simulator*>(
|
705
|
+
v8::internal::Thread::GetThreadLocal(simulator_key));
|
706
|
+
if (sim == NULL) {
|
707
|
+
// TODO(146): delete the simulator object when a thread goes away.
|
708
|
+
sim = new Simulator();
|
709
|
+
v8::internal::Thread::SetThreadLocal(simulator_key, sim);
|
710
|
+
}
|
711
|
+
return sim;
|
712
|
+
}
|
713
|
+
|
714
|
+
|
715
|
+
// Sets the register in the architecture state. It will also deal with updating
|
716
|
+
// Simulator internal state for special registers such as PC.
|
717
|
+
void Simulator::set_register(int reg, int32_t value) {
|
718
|
+
ASSERT((reg >= 0) && (reg < num_registers));
|
719
|
+
if (reg == pc) {
|
720
|
+
pc_modified_ = true;
|
721
|
+
}
|
722
|
+
registers_[reg] = value;
|
723
|
+
}
|
724
|
+
|
725
|
+
|
726
|
+
// Get the register from the architecture state. This function does handle
|
727
|
+
// the special case of accessing the PC register.
|
728
|
+
int32_t Simulator::get_register(int reg) const {
|
729
|
+
ASSERT((reg >= 0) && (reg < num_registers));
|
730
|
+
return registers_[reg] + ((reg == pc) ? Instr::kPCReadOffset : 0);
|
731
|
+
}
|
732
|
+
|
733
|
+
|
734
|
+
void Simulator::set_dw_register(int dreg, const int* dbl) {
|
735
|
+
ASSERT((dreg >= 0) && (dreg < num_d_registers));
|
736
|
+
registers_[dreg] = dbl[0];
|
737
|
+
registers_[dreg + 1] = dbl[1];
|
738
|
+
}
|
739
|
+
|
740
|
+
|
741
|
+
// Raw access to the PC register.
|
742
|
+
void Simulator::set_pc(int32_t value) {
|
743
|
+
pc_modified_ = true;
|
744
|
+
registers_[pc] = value;
|
745
|
+
}
|
746
|
+
|
747
|
+
|
748
|
+
// Raw access to the PC register without the special adjustment when reading.
|
749
|
+
int32_t Simulator::get_pc() const {
|
750
|
+
return registers_[pc];
|
751
|
+
}
|
752
|
+
|
753
|
+
|
754
|
+
// Getting from and setting into VFP registers.
|
755
|
+
void Simulator::set_s_register(int sreg, unsigned int value) {
|
756
|
+
ASSERT((sreg >= 0) && (sreg < num_s_registers));
|
757
|
+
vfp_register[sreg] = value;
|
758
|
+
}
|
759
|
+
|
760
|
+
|
761
|
+
unsigned int Simulator::get_s_register(int sreg) const {
|
762
|
+
ASSERT((sreg >= 0) && (sreg < num_s_registers));
|
763
|
+
return vfp_register[sreg];
|
764
|
+
}
|
765
|
+
|
766
|
+
|
767
|
+
void Simulator::set_s_register_from_float(int sreg, const float flt) {
|
768
|
+
ASSERT((sreg >= 0) && (sreg < num_s_registers));
|
769
|
+
// Read the bits from the single precision floating point value
|
770
|
+
// into the unsigned integer element of vfp_register[] given by index=sreg.
|
771
|
+
char buffer[sizeof(vfp_register[0])];
|
772
|
+
memcpy(buffer, &flt, sizeof(vfp_register[0]));
|
773
|
+
memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0]));
|
774
|
+
}
|
775
|
+
|
776
|
+
|
777
|
+
void Simulator::set_s_register_from_sinteger(int sreg, const int sint) {
|
778
|
+
ASSERT((sreg >= 0) && (sreg < num_s_registers));
|
779
|
+
// Read the bits from the integer value into the unsigned integer element of
|
780
|
+
// vfp_register[] given by index=sreg.
|
781
|
+
char buffer[sizeof(vfp_register[0])];
|
782
|
+
memcpy(buffer, &sint, sizeof(vfp_register[0]));
|
783
|
+
memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0]));
|
784
|
+
}
|
785
|
+
|
786
|
+
|
787
|
+
void Simulator::set_d_register_from_double(int dreg, const double& dbl) {
|
788
|
+
ASSERT((dreg >= 0) && (dreg < num_d_registers));
|
789
|
+
// Read the bits from the double precision floating point value into the two
|
790
|
+
// consecutive unsigned integer elements of vfp_register[] given by index
|
791
|
+
// 2*sreg and 2*sreg+1.
|
792
|
+
char buffer[2 * sizeof(vfp_register[0])];
|
793
|
+
memcpy(buffer, &dbl, 2 * sizeof(vfp_register[0]));
|
794
|
+
#ifndef BIG_ENDIAN_FLOATING_POINT
|
795
|
+
memcpy(&vfp_register[dreg * 2], buffer, 2 * sizeof(vfp_register[0]));
|
796
|
+
#else
|
797
|
+
memcpy(&vfp_register[dreg * 2], &buffer[4], sizeof(vfp_register[0]));
|
798
|
+
memcpy(&vfp_register[dreg * 2 + 1], &buffer[0], sizeof(vfp_register[0]));
|
799
|
+
#endif
|
800
|
+
}
|
801
|
+
|
802
|
+
|
803
|
+
float Simulator::get_float_from_s_register(int sreg) {
|
804
|
+
ASSERT((sreg >= 0) && (sreg < num_s_registers));
|
805
|
+
|
806
|
+
float sm_val = 0.0;
|
807
|
+
// Read the bits from the unsigned integer vfp_register[] array
|
808
|
+
// into the single precision floating point value and return it.
|
809
|
+
char buffer[sizeof(vfp_register[0])];
|
810
|
+
memcpy(buffer, &vfp_register[sreg], sizeof(vfp_register[0]));
|
811
|
+
memcpy(&sm_val, buffer, sizeof(vfp_register[0]));
|
812
|
+
return(sm_val);
|
813
|
+
}
|
814
|
+
|
815
|
+
|
816
|
+
int Simulator::get_sinteger_from_s_register(int sreg) {
|
817
|
+
ASSERT((sreg >= 0) && (sreg < num_s_registers));
|
818
|
+
|
819
|
+
int sm_val = 0;
|
820
|
+
// Read the bits from the unsigned integer vfp_register[] array
|
821
|
+
// into the single precision floating point value and return it.
|
822
|
+
char buffer[sizeof(vfp_register[0])];
|
823
|
+
memcpy(buffer, &vfp_register[sreg], sizeof(vfp_register[0]));
|
824
|
+
memcpy(&sm_val, buffer, sizeof(vfp_register[0]));
|
825
|
+
return(sm_val);
|
826
|
+
}
|
827
|
+
|
828
|
+
|
829
|
+
double Simulator::get_double_from_d_register(int dreg) {
|
830
|
+
ASSERT((dreg >= 0) && (dreg < num_d_registers));
|
831
|
+
|
832
|
+
double dm_val = 0.0;
|
833
|
+
// Read the bits from the unsigned integer vfp_register[] array
|
834
|
+
// into the double precision floating point value and return it.
|
835
|
+
char buffer[2 * sizeof(vfp_register[0])];
|
836
|
+
#ifdef BIG_ENDIAN_FLOATING_POINT
|
837
|
+
memcpy(&buffer[0], &vfp_register[2 * dreg + 1], sizeof(vfp_register[0]));
|
838
|
+
memcpy(&buffer[4], &vfp_register[2 * dreg], sizeof(vfp_register[0]));
|
839
|
+
#else
|
840
|
+
memcpy(buffer, &vfp_register[2 * dreg], 2 * sizeof(vfp_register[0]));
|
841
|
+
#endif
|
842
|
+
memcpy(&dm_val, buffer, 2 * sizeof(vfp_register[0]));
|
843
|
+
return(dm_val);
|
844
|
+
}
|
845
|
+
|
846
|
+
|
847
|
+
// For use in calls that take two double values, constructed from r0, r1, r2
|
848
|
+
// and r3.
|
849
|
+
void Simulator::GetFpArgs(double* x, double* y) {
|
850
|
+
// We use a char buffer to get around the strict-aliasing rules which
|
851
|
+
// otherwise allow the compiler to optimize away the copy.
|
852
|
+
char buffer[2 * sizeof(registers_[0])];
|
853
|
+
// Registers 0 and 1 -> x.
|
854
|
+
memcpy(buffer, registers_, sizeof(buffer));
|
855
|
+
memcpy(x, buffer, sizeof(buffer));
|
856
|
+
// Registers 2 and 3 -> y.
|
857
|
+
memcpy(buffer, registers_ + 2, sizeof(buffer));
|
858
|
+
memcpy(y, buffer, sizeof(buffer));
|
859
|
+
}
|
860
|
+
|
861
|
+
|
862
|
+
void Simulator::SetFpResult(const double& result) {
|
863
|
+
char buffer[2 * sizeof(registers_[0])];
|
864
|
+
memcpy(buffer, &result, sizeof(buffer));
|
865
|
+
// result -> registers 0 and 1.
|
866
|
+
memcpy(registers_, buffer, sizeof(buffer));
|
867
|
+
}
|
868
|
+
|
869
|
+
|
870
|
+
void Simulator::TrashCallerSaveRegisters() {
|
871
|
+
// We don't trash the registers with the return value.
|
872
|
+
registers_[2] = 0x50Bad4U;
|
873
|
+
registers_[3] = 0x50Bad4U;
|
874
|
+
registers_[12] = 0x50Bad4U;
|
875
|
+
}
|
876
|
+
|
877
|
+
// Some Operating Systems allow unaligned access on ARMv7 targets. We
|
878
|
+
// assume that unaligned accesses are not allowed unless the v8 build system
|
879
|
+
// defines the CAN_USE_UNALIGNED_ACCESSES macro to be non-zero.
|
880
|
+
// The following statements below describes the behavior of the ARM CPUs
|
881
|
+
// that don't support unaligned access.
|
882
|
+
// Some ARM platforms raise an interrupt on detecting unaligned access.
|
883
|
+
// On others it does a funky rotation thing. For now we
|
884
|
+
// simply disallow unaligned reads. Note that simulator runs have the runtime
|
885
|
+
// system running directly on the host system and only generated code is
|
886
|
+
// executed in the simulator. Since the host is typically IA32 we will not
|
887
|
+
// get the correct ARM-like behaviour on unaligned accesses for those ARM
|
888
|
+
// targets that don't support unaligned loads and stores.
|
889
|
+
|
890
|
+
|
891
|
+
int Simulator::ReadW(int32_t addr, Instr* instr) {
|
892
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
893
|
+
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
894
|
+
return *ptr;
|
895
|
+
#else
|
896
|
+
if ((addr & 3) == 0) {
|
897
|
+
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
898
|
+
return *ptr;
|
899
|
+
}
|
900
|
+
PrintF("Unaligned read at 0x%08x, pc=%p\n", addr, instr);
|
901
|
+
UNIMPLEMENTED();
|
902
|
+
return 0;
|
903
|
+
#endif
|
904
|
+
}
|
905
|
+
|
906
|
+
|
907
|
+
void Simulator::WriteW(int32_t addr, int value, Instr* instr) {
|
908
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
909
|
+
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
910
|
+
*ptr = value;
|
911
|
+
return;
|
912
|
+
#else
|
913
|
+
if ((addr & 3) == 0) {
|
914
|
+
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
915
|
+
*ptr = value;
|
916
|
+
return;
|
917
|
+
}
|
918
|
+
PrintF("Unaligned write at 0x%08x, pc=%p\n", addr, instr);
|
919
|
+
UNIMPLEMENTED();
|
920
|
+
#endif
|
921
|
+
}
|
922
|
+
|
923
|
+
|
924
|
+
uint16_t Simulator::ReadHU(int32_t addr, Instr* instr) {
|
925
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
926
|
+
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
927
|
+
return *ptr;
|
928
|
+
#else
|
929
|
+
if ((addr & 1) == 0) {
|
930
|
+
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
931
|
+
return *ptr;
|
932
|
+
}
|
933
|
+
PrintF("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr, instr);
|
934
|
+
UNIMPLEMENTED();
|
935
|
+
return 0;
|
936
|
+
#endif
|
937
|
+
}
|
938
|
+
|
939
|
+
|
940
|
+
int16_t Simulator::ReadH(int32_t addr, Instr* instr) {
|
941
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
942
|
+
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
943
|
+
return *ptr;
|
944
|
+
#else
|
945
|
+
if ((addr & 1) == 0) {
|
946
|
+
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
947
|
+
return *ptr;
|
948
|
+
}
|
949
|
+
PrintF("Unaligned signed halfword read at 0x%08x\n", addr);
|
950
|
+
UNIMPLEMENTED();
|
951
|
+
return 0;
|
952
|
+
#endif
|
953
|
+
}
|
954
|
+
|
955
|
+
|
956
|
+
void Simulator::WriteH(int32_t addr, uint16_t value, Instr* instr) {
|
957
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
958
|
+
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
959
|
+
*ptr = value;
|
960
|
+
return;
|
961
|
+
#else
|
962
|
+
if ((addr & 1) == 0) {
|
963
|
+
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
964
|
+
*ptr = value;
|
965
|
+
return;
|
966
|
+
}
|
967
|
+
PrintF("Unaligned unsigned halfword write at 0x%08x, pc=%p\n", addr, instr);
|
968
|
+
UNIMPLEMENTED();
|
969
|
+
#endif
|
970
|
+
}
|
971
|
+
|
972
|
+
|
973
|
+
void Simulator::WriteH(int32_t addr, int16_t value, Instr* instr) {
|
974
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
975
|
+
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
976
|
+
*ptr = value;
|
977
|
+
return;
|
978
|
+
#else
|
979
|
+
if ((addr & 1) == 0) {
|
980
|
+
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
981
|
+
*ptr = value;
|
982
|
+
return;
|
983
|
+
}
|
984
|
+
PrintF("Unaligned halfword write at 0x%08x, pc=%p\n", addr, instr);
|
985
|
+
UNIMPLEMENTED();
|
986
|
+
#endif
|
987
|
+
}
|
988
|
+
|
989
|
+
|
990
|
+
uint8_t Simulator::ReadBU(int32_t addr) {
|
991
|
+
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
|
992
|
+
return *ptr;
|
993
|
+
}
|
994
|
+
|
995
|
+
|
996
|
+
int8_t Simulator::ReadB(int32_t addr) {
|
997
|
+
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
|
998
|
+
return *ptr;
|
999
|
+
}
|
1000
|
+
|
1001
|
+
|
1002
|
+
void Simulator::WriteB(int32_t addr, uint8_t value) {
|
1003
|
+
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
|
1004
|
+
*ptr = value;
|
1005
|
+
}
|
1006
|
+
|
1007
|
+
|
1008
|
+
void Simulator::WriteB(int32_t addr, int8_t value) {
|
1009
|
+
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
|
1010
|
+
*ptr = value;
|
1011
|
+
}
|
1012
|
+
|
1013
|
+
|
1014
|
+
int32_t* Simulator::ReadDW(int32_t addr) {
|
1015
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
1016
|
+
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
|
1017
|
+
return ptr;
|
1018
|
+
#else
|
1019
|
+
if ((addr & 3) == 0) {
|
1020
|
+
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
|
1021
|
+
return ptr;
|
1022
|
+
}
|
1023
|
+
PrintF("Unaligned read at 0x%08x\n", addr);
|
1024
|
+
UNIMPLEMENTED();
|
1025
|
+
return 0;
|
1026
|
+
#endif
|
1027
|
+
}
|
1028
|
+
|
1029
|
+
|
1030
|
+
void Simulator::WriteDW(int32_t addr, int32_t value1, int32_t value2) {
|
1031
|
+
#if V8_TARGET_CAN_READ_UNALIGNED
|
1032
|
+
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
|
1033
|
+
*ptr++ = value1;
|
1034
|
+
*ptr = value2;
|
1035
|
+
return;
|
1036
|
+
#else
|
1037
|
+
if ((addr & 3) == 0) {
|
1038
|
+
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
|
1039
|
+
*ptr++ = value1;
|
1040
|
+
*ptr = value2;
|
1041
|
+
return;
|
1042
|
+
}
|
1043
|
+
PrintF("Unaligned write at 0x%08x\n", addr);
|
1044
|
+
UNIMPLEMENTED();
|
1045
|
+
#endif
|
1046
|
+
}
|
1047
|
+
|
1048
|
+
|
1049
|
+
// Returns the limit of the stack area to enable checking for stack overflows.
|
1050
|
+
uintptr_t Simulator::StackLimit() const {
|
1051
|
+
// Leave a safety margin of 256 bytes to prevent overrunning the stack when
|
1052
|
+
// pushing values.
|
1053
|
+
return reinterpret_cast<uintptr_t>(stack_) + 256;
|
1054
|
+
}
|
1055
|
+
|
1056
|
+
|
1057
|
+
// Unsupported instructions use Format to print an error and stop execution.
|
1058
|
+
void Simulator::Format(Instr* instr, const char* format) {
|
1059
|
+
PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n",
|
1060
|
+
instr, format);
|
1061
|
+
UNIMPLEMENTED();
|
1062
|
+
}
|
1063
|
+
|
1064
|
+
|
1065
|
+
// Checks if the current instruction should be executed based on its
|
1066
|
+
// condition bits.
|
1067
|
+
bool Simulator::ConditionallyExecute(Instr* instr) {
|
1068
|
+
switch (instr->ConditionField()) {
|
1069
|
+
case EQ: return z_flag_;
|
1070
|
+
case NE: return !z_flag_;
|
1071
|
+
case CS: return c_flag_;
|
1072
|
+
case CC: return !c_flag_;
|
1073
|
+
case MI: return n_flag_;
|
1074
|
+
case PL: return !n_flag_;
|
1075
|
+
case VS: return v_flag_;
|
1076
|
+
case VC: return !v_flag_;
|
1077
|
+
case HI: return c_flag_ && !z_flag_;
|
1078
|
+
case LS: return !c_flag_ || z_flag_;
|
1079
|
+
case GE: return n_flag_ == v_flag_;
|
1080
|
+
case LT: return n_flag_ != v_flag_;
|
1081
|
+
case GT: return !z_flag_ && (n_flag_ == v_flag_);
|
1082
|
+
case LE: return z_flag_ || (n_flag_ != v_flag_);
|
1083
|
+
case AL: return true;
|
1084
|
+
default: UNREACHABLE();
|
1085
|
+
}
|
1086
|
+
return false;
|
1087
|
+
}
|
1088
|
+
|
1089
|
+
|
1090
|
+
// Calculate and set the Negative and Zero flags.
|
1091
|
+
void Simulator::SetNZFlags(int32_t val) {
|
1092
|
+
n_flag_ = (val < 0);
|
1093
|
+
z_flag_ = (val == 0);
|
1094
|
+
}
|
1095
|
+
|
1096
|
+
|
1097
|
+
// Set the Carry flag.
|
1098
|
+
void Simulator::SetCFlag(bool val) {
|
1099
|
+
c_flag_ = val;
|
1100
|
+
}
|
1101
|
+
|
1102
|
+
|
1103
|
+
// Set the oVerflow flag.
|
1104
|
+
void Simulator::SetVFlag(bool val) {
|
1105
|
+
v_flag_ = val;
|
1106
|
+
}
|
1107
|
+
|
1108
|
+
|
1109
|
+
// Calculate C flag value for additions.
|
1110
|
+
bool Simulator::CarryFrom(int32_t left, int32_t right) {
|
1111
|
+
uint32_t uleft = static_cast<uint32_t>(left);
|
1112
|
+
uint32_t uright = static_cast<uint32_t>(right);
|
1113
|
+
uint32_t urest = 0xffffffffU - uleft;
|
1114
|
+
|
1115
|
+
return (uright > urest);
|
1116
|
+
}
|
1117
|
+
|
1118
|
+
|
1119
|
+
// Calculate C flag value for subtractions.
|
1120
|
+
bool Simulator::BorrowFrom(int32_t left, int32_t right) {
|
1121
|
+
uint32_t uleft = static_cast<uint32_t>(left);
|
1122
|
+
uint32_t uright = static_cast<uint32_t>(right);
|
1123
|
+
|
1124
|
+
return (uright > uleft);
|
1125
|
+
}
|
1126
|
+
|
1127
|
+
|
1128
|
+
// Calculate V flag value for additions and subtractions.
|
1129
|
+
bool Simulator::OverflowFrom(int32_t alu_out,
|
1130
|
+
int32_t left, int32_t right, bool addition) {
|
1131
|
+
bool overflow;
|
1132
|
+
if (addition) {
|
1133
|
+
// operands have the same sign
|
1134
|
+
overflow = ((left >= 0 && right >= 0) || (left < 0 && right < 0))
|
1135
|
+
// and operands and result have different sign
|
1136
|
+
&& ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
|
1137
|
+
} else {
|
1138
|
+
// operands have different signs
|
1139
|
+
overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0))
|
1140
|
+
// and first operand and result have different signs
|
1141
|
+
&& ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
|
1142
|
+
}
|
1143
|
+
return overflow;
|
1144
|
+
}
|
1145
|
+
|
1146
|
+
|
1147
|
+
// Support for VFP comparisons.
|
1148
|
+
void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
|
1149
|
+
if (isnan(val1) || isnan(val2)) {
|
1150
|
+
n_flag_FPSCR_ = false;
|
1151
|
+
z_flag_FPSCR_ = false;
|
1152
|
+
c_flag_FPSCR_ = true;
|
1153
|
+
v_flag_FPSCR_ = true;
|
1154
|
+
// All non-NaN cases.
|
1155
|
+
} else if (val1 == val2) {
|
1156
|
+
n_flag_FPSCR_ = false;
|
1157
|
+
z_flag_FPSCR_ = true;
|
1158
|
+
c_flag_FPSCR_ = true;
|
1159
|
+
v_flag_FPSCR_ = false;
|
1160
|
+
} else if (val1 < val2) {
|
1161
|
+
n_flag_FPSCR_ = true;
|
1162
|
+
z_flag_FPSCR_ = false;
|
1163
|
+
c_flag_FPSCR_ = false;
|
1164
|
+
v_flag_FPSCR_ = false;
|
1165
|
+
} else {
|
1166
|
+
// Case when (val1 > val2).
|
1167
|
+
n_flag_FPSCR_ = false;
|
1168
|
+
z_flag_FPSCR_ = false;
|
1169
|
+
c_flag_FPSCR_ = true;
|
1170
|
+
v_flag_FPSCR_ = false;
|
1171
|
+
}
|
1172
|
+
}
|
1173
|
+
|
1174
|
+
|
1175
|
+
void Simulator::Copy_FPSCR_to_APSR() {
|
1176
|
+
n_flag_ = n_flag_FPSCR_;
|
1177
|
+
z_flag_ = z_flag_FPSCR_;
|
1178
|
+
c_flag_ = c_flag_FPSCR_;
|
1179
|
+
v_flag_ = v_flag_FPSCR_;
|
1180
|
+
}
|
1181
|
+
|
1182
|
+
|
1183
|
+
// Addressing Mode 1 - Data-processing operands:
|
1184
|
+
// Get the value based on the shifter_operand with register.
|
1185
|
+
int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
|
1186
|
+
Shift shift = instr->ShiftField();
|
1187
|
+
int shift_amount = instr->ShiftAmountField();
|
1188
|
+
int32_t result = get_register(instr->RmField());
|
1189
|
+
if (instr->Bit(4) == 0) {
|
1190
|
+
// by immediate
|
1191
|
+
if ((shift == ROR) && (shift_amount == 0)) {
|
1192
|
+
UNIMPLEMENTED();
|
1193
|
+
return result;
|
1194
|
+
} else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
|
1195
|
+
shift_amount = 32;
|
1196
|
+
}
|
1197
|
+
switch (shift) {
|
1198
|
+
case ASR: {
|
1199
|
+
if (shift_amount == 0) {
|
1200
|
+
if (result < 0) {
|
1201
|
+
result = 0xffffffff;
|
1202
|
+
*carry_out = true;
|
1203
|
+
} else {
|
1204
|
+
result = 0;
|
1205
|
+
*carry_out = false;
|
1206
|
+
}
|
1207
|
+
} else {
|
1208
|
+
result >>= (shift_amount - 1);
|
1209
|
+
*carry_out = (result & 1) == 1;
|
1210
|
+
result >>= 1;
|
1211
|
+
}
|
1212
|
+
break;
|
1213
|
+
}
|
1214
|
+
|
1215
|
+
case LSL: {
|
1216
|
+
if (shift_amount == 0) {
|
1217
|
+
*carry_out = c_flag_;
|
1218
|
+
} else {
|
1219
|
+
result <<= (shift_amount - 1);
|
1220
|
+
*carry_out = (result < 0);
|
1221
|
+
result <<= 1;
|
1222
|
+
}
|
1223
|
+
break;
|
1224
|
+
}
|
1225
|
+
|
1226
|
+
case LSR: {
|
1227
|
+
if (shift_amount == 0) {
|
1228
|
+
result = 0;
|
1229
|
+
*carry_out = c_flag_;
|
1230
|
+
} else {
|
1231
|
+
uint32_t uresult = static_cast<uint32_t>(result);
|
1232
|
+
uresult >>= (shift_amount - 1);
|
1233
|
+
*carry_out = (uresult & 1) == 1;
|
1234
|
+
uresult >>= 1;
|
1235
|
+
result = static_cast<int32_t>(uresult);
|
1236
|
+
}
|
1237
|
+
break;
|
1238
|
+
}
|
1239
|
+
|
1240
|
+
case ROR: {
|
1241
|
+
UNIMPLEMENTED();
|
1242
|
+
break;
|
1243
|
+
}
|
1244
|
+
|
1245
|
+
default: {
|
1246
|
+
UNREACHABLE();
|
1247
|
+
break;
|
1248
|
+
}
|
1249
|
+
}
|
1250
|
+
} else {
|
1251
|
+
// by register
|
1252
|
+
int rs = instr->RsField();
|
1253
|
+
shift_amount = get_register(rs) &0xff;
|
1254
|
+
switch (shift) {
|
1255
|
+
case ASR: {
|
1256
|
+
if (shift_amount == 0) {
|
1257
|
+
*carry_out = c_flag_;
|
1258
|
+
} else if (shift_amount < 32) {
|
1259
|
+
result >>= (shift_amount - 1);
|
1260
|
+
*carry_out = (result & 1) == 1;
|
1261
|
+
result >>= 1;
|
1262
|
+
} else {
|
1263
|
+
ASSERT(shift_amount >= 32);
|
1264
|
+
if (result < 0) {
|
1265
|
+
*carry_out = true;
|
1266
|
+
result = 0xffffffff;
|
1267
|
+
} else {
|
1268
|
+
*carry_out = false;
|
1269
|
+
result = 0;
|
1270
|
+
}
|
1271
|
+
}
|
1272
|
+
break;
|
1273
|
+
}
|
1274
|
+
|
1275
|
+
case LSL: {
|
1276
|
+
if (shift_amount == 0) {
|
1277
|
+
*carry_out = c_flag_;
|
1278
|
+
} else if (shift_amount < 32) {
|
1279
|
+
result <<= (shift_amount - 1);
|
1280
|
+
*carry_out = (result < 0);
|
1281
|
+
result <<= 1;
|
1282
|
+
} else if (shift_amount == 32) {
|
1283
|
+
*carry_out = (result & 1) == 1;
|
1284
|
+
result = 0;
|
1285
|
+
} else {
|
1286
|
+
ASSERT(shift_amount > 32);
|
1287
|
+
*carry_out = false;
|
1288
|
+
result = 0;
|
1289
|
+
}
|
1290
|
+
break;
|
1291
|
+
}
|
1292
|
+
|
1293
|
+
case LSR: {
|
1294
|
+
if (shift_amount == 0) {
|
1295
|
+
*carry_out = c_flag_;
|
1296
|
+
} else if (shift_amount < 32) {
|
1297
|
+
uint32_t uresult = static_cast<uint32_t>(result);
|
1298
|
+
uresult >>= (shift_amount - 1);
|
1299
|
+
*carry_out = (uresult & 1) == 1;
|
1300
|
+
uresult >>= 1;
|
1301
|
+
result = static_cast<int32_t>(uresult);
|
1302
|
+
} else if (shift_amount == 32) {
|
1303
|
+
*carry_out = (result < 0);
|
1304
|
+
result = 0;
|
1305
|
+
} else {
|
1306
|
+
*carry_out = false;
|
1307
|
+
result = 0;
|
1308
|
+
}
|
1309
|
+
break;
|
1310
|
+
}
|
1311
|
+
|
1312
|
+
case ROR: {
|
1313
|
+
UNIMPLEMENTED();
|
1314
|
+
break;
|
1315
|
+
}
|
1316
|
+
|
1317
|
+
default: {
|
1318
|
+
UNREACHABLE();
|
1319
|
+
break;
|
1320
|
+
}
|
1321
|
+
}
|
1322
|
+
}
|
1323
|
+
return result;
|
1324
|
+
}
|
1325
|
+
|
1326
|
+
|
1327
|
+
// Addressing Mode 1 - Data-processing operands:
|
1328
|
+
// Get the value based on the shifter_operand with immediate.
|
1329
|
+
int32_t Simulator::GetImm(Instr* instr, bool* carry_out) {
|
1330
|
+
int rotate = instr->RotateField() * 2;
|
1331
|
+
int immed8 = instr->Immed8Field();
|
1332
|
+
int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
|
1333
|
+
*carry_out = (rotate == 0) ? c_flag_ : (imm < 0);
|
1334
|
+
return imm;
|
1335
|
+
}
|
1336
|
+
|
1337
|
+
|
1338
|
+
static int count_bits(int bit_vector) {
|
1339
|
+
int count = 0;
|
1340
|
+
while (bit_vector != 0) {
|
1341
|
+
if ((bit_vector & 1) != 0) {
|
1342
|
+
count++;
|
1343
|
+
}
|
1344
|
+
bit_vector >>= 1;
|
1345
|
+
}
|
1346
|
+
return count;
|
1347
|
+
}
|
1348
|
+
|
1349
|
+
|
1350
|
+
// Addressing Mode 4 - Load and Store Multiple
|
1351
|
+
void Simulator::HandleRList(Instr* instr, bool load) {
|
1352
|
+
int rn = instr->RnField();
|
1353
|
+
int32_t rn_val = get_register(rn);
|
1354
|
+
int rlist = instr->RlistField();
|
1355
|
+
int num_regs = count_bits(rlist);
|
1356
|
+
|
1357
|
+
intptr_t start_address = 0;
|
1358
|
+
intptr_t end_address = 0;
|
1359
|
+
switch (instr->PUField()) {
|
1360
|
+
case 0: {
|
1361
|
+
// Print("da");
|
1362
|
+
UNIMPLEMENTED();
|
1363
|
+
break;
|
1364
|
+
}
|
1365
|
+
case 1: {
|
1366
|
+
// Print("ia");
|
1367
|
+
start_address = rn_val;
|
1368
|
+
end_address = rn_val + (num_regs * 4) - 4;
|
1369
|
+
rn_val = rn_val + (num_regs * 4);
|
1370
|
+
break;
|
1371
|
+
}
|
1372
|
+
case 2: {
|
1373
|
+
// Print("db");
|
1374
|
+
start_address = rn_val - (num_regs * 4);
|
1375
|
+
end_address = rn_val - 4;
|
1376
|
+
rn_val = start_address;
|
1377
|
+
break;
|
1378
|
+
}
|
1379
|
+
case 3: {
|
1380
|
+
// Print("ib");
|
1381
|
+
UNIMPLEMENTED();
|
1382
|
+
break;
|
1383
|
+
}
|
1384
|
+
default: {
|
1385
|
+
UNREACHABLE();
|
1386
|
+
break;
|
1387
|
+
}
|
1388
|
+
}
|
1389
|
+
if (instr->HasW()) {
|
1390
|
+
set_register(rn, rn_val);
|
1391
|
+
}
|
1392
|
+
intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
|
1393
|
+
int reg = 0;
|
1394
|
+
while (rlist != 0) {
|
1395
|
+
if ((rlist & 1) != 0) {
|
1396
|
+
if (load) {
|
1397
|
+
set_register(reg, *address);
|
1398
|
+
} else {
|
1399
|
+
*address = get_register(reg);
|
1400
|
+
}
|
1401
|
+
address += 1;
|
1402
|
+
}
|
1403
|
+
reg++;
|
1404
|
+
rlist >>= 1;
|
1405
|
+
}
|
1406
|
+
ASSERT(end_address == ((intptr_t)address) - 4);
|
1407
|
+
}
|
1408
|
+
|
1409
|
+
|
1410
|
+
// Calls into the V8 runtime are based on this very simple interface.
|
1411
|
+
// Note: To be able to return two values from some calls the code in runtime.cc
|
1412
|
+
// uses the ObjectPair which is essentially two 32-bit values stuffed into a
|
1413
|
+
// 64-bit value. With the code below we assume that all runtime calls return
|
1414
|
+
// 64 bits of result. If they don't, the r1 result register contains a bogus
|
1415
|
+
// value, which is fine because it is caller-saved.
|
1416
|
+
typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0,
|
1417
|
+
int32_t arg1,
|
1418
|
+
int32_t arg2,
|
1419
|
+
int32_t arg3);
|
1420
|
+
typedef double (*SimulatorRuntimeFPCall)(int32_t arg0,
|
1421
|
+
int32_t arg1,
|
1422
|
+
int32_t arg2,
|
1423
|
+
int32_t arg3);
|
1424
|
+
|
1425
|
+
|
1426
|
+
// Software interrupt instructions are used by the simulator to call into the
|
1427
|
+
// C-based V8 runtime.
|
1428
|
+
void Simulator::SoftwareInterrupt(Instr* instr) {
|
1429
|
+
int swi = instr->SwiField();
|
1430
|
+
switch (swi) {
|
1431
|
+
case call_rt_redirected: {
|
1432
|
+
// Check if stack is aligned. Error if not aligned is reported below to
|
1433
|
+
// include information on the function called.
|
1434
|
+
bool stack_aligned =
|
1435
|
+
(get_register(sp)
|
1436
|
+
& (::v8::internal::FLAG_sim_stack_alignment - 1)) == 0;
|
1437
|
+
Redirection* redirection = Redirection::FromSwiInstruction(instr);
|
1438
|
+
int32_t arg0 = get_register(r0);
|
1439
|
+
int32_t arg1 = get_register(r1);
|
1440
|
+
int32_t arg2 = get_register(r2);
|
1441
|
+
int32_t arg3 = get_register(r3);
|
1442
|
+
// This is dodgy but it works because the C entry stubs are never moved.
|
1443
|
+
// See comment in codegen-arm.cc and bug 1242173.
|
1444
|
+
int32_t saved_lr = get_register(lr);
|
1445
|
+
if (redirection->fp_return()) {
|
1446
|
+
intptr_t external =
|
1447
|
+
reinterpret_cast<intptr_t>(redirection->external_function());
|
1448
|
+
SimulatorRuntimeFPCall target =
|
1449
|
+
reinterpret_cast<SimulatorRuntimeFPCall>(external);
|
1450
|
+
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
|
1451
|
+
double x, y;
|
1452
|
+
GetFpArgs(&x, &y);
|
1453
|
+
PrintF("Call to host function at %p with args %f, %f",
|
1454
|
+
FUNCTION_ADDR(target), x, y);
|
1455
|
+
if (!stack_aligned) {
|
1456
|
+
PrintF(" with unaligned stack %08x\n", get_register(sp));
|
1457
|
+
}
|
1458
|
+
PrintF("\n");
|
1459
|
+
}
|
1460
|
+
CHECK(stack_aligned);
|
1461
|
+
double result = target(arg0, arg1, arg2, arg3);
|
1462
|
+
SetFpResult(result);
|
1463
|
+
} else {
|
1464
|
+
intptr_t external =
|
1465
|
+
reinterpret_cast<int32_t>(redirection->external_function());
|
1466
|
+
SimulatorRuntimeCall target =
|
1467
|
+
reinterpret_cast<SimulatorRuntimeCall>(external);
|
1468
|
+
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
|
1469
|
+
PrintF(
|
1470
|
+
"Call to host function at %p with args %08x, %08x, %08x, %08x",
|
1471
|
+
FUNCTION_ADDR(target),
|
1472
|
+
arg0,
|
1473
|
+
arg1,
|
1474
|
+
arg2,
|
1475
|
+
arg3);
|
1476
|
+
if (!stack_aligned) {
|
1477
|
+
PrintF(" with unaligned stack %08x\n", get_register(sp));
|
1478
|
+
}
|
1479
|
+
PrintF("\n");
|
1480
|
+
}
|
1481
|
+
CHECK(stack_aligned);
|
1482
|
+
int64_t result = target(arg0, arg1, arg2, arg3);
|
1483
|
+
int32_t lo_res = static_cast<int32_t>(result);
|
1484
|
+
int32_t hi_res = static_cast<int32_t>(result >> 32);
|
1485
|
+
if (::v8::internal::FLAG_trace_sim) {
|
1486
|
+
PrintF("Returned %08x\n", lo_res);
|
1487
|
+
}
|
1488
|
+
set_register(r0, lo_res);
|
1489
|
+
set_register(r1, hi_res);
|
1490
|
+
}
|
1491
|
+
set_register(lr, saved_lr);
|
1492
|
+
set_pc(get_register(lr));
|
1493
|
+
break;
|
1494
|
+
}
|
1495
|
+
case break_point: {
|
1496
|
+
Debugger dbg(this);
|
1497
|
+
dbg.Debug();
|
1498
|
+
break;
|
1499
|
+
}
|
1500
|
+
default: {
|
1501
|
+
UNREACHABLE();
|
1502
|
+
break;
|
1503
|
+
}
|
1504
|
+
}
|
1505
|
+
}
|
1506
|
+
|
1507
|
+
|
1508
|
+
// Handle execution based on instruction types.
|
1509
|
+
|
1510
|
+
// Instruction types 0 and 1 are both rolled into one function because they
|
1511
|
+
// only differ in the handling of the shifter_operand.
|
1512
|
+
void Simulator::DecodeType01(Instr* instr) {
|
1513
|
+
int type = instr->TypeField();
|
1514
|
+
if ((type == 0) && instr->IsSpecialType0()) {
|
1515
|
+
// multiply instruction or extra loads and stores
|
1516
|
+
if (instr->Bits(7, 4) == 9) {
|
1517
|
+
if (instr->Bit(24) == 0) {
|
1518
|
+
// Raw field decoding here. Multiply instructions have their Rd in
|
1519
|
+
// funny places.
|
1520
|
+
int rn = instr->RnField();
|
1521
|
+
int rm = instr->RmField();
|
1522
|
+
int rs = instr->RsField();
|
1523
|
+
int32_t rs_val = get_register(rs);
|
1524
|
+
int32_t rm_val = get_register(rm);
|
1525
|
+
if (instr->Bit(23) == 0) {
|
1526
|
+
if (instr->Bit(21) == 0) {
|
1527
|
+
// The MUL instruction description (A 4.1.33) refers to Rd as being
|
1528
|
+
// the destination for the operation, but it confusingly uses the
|
1529
|
+
// Rn field to encode it.
|
1530
|
+
// Format(instr, "mul'cond's 'rn, 'rm, 'rs");
|
1531
|
+
int rd = rn; // Remap the rn field to the Rd register.
|
1532
|
+
int32_t alu_out = rm_val * rs_val;
|
1533
|
+
set_register(rd, alu_out);
|
1534
|
+
if (instr->HasS()) {
|
1535
|
+
SetNZFlags(alu_out);
|
1536
|
+
}
|
1537
|
+
} else {
|
1538
|
+
// The MLA instruction description (A 4.1.28) refers to the order
|
1539
|
+
// of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
|
1540
|
+
// Rn field to encode the Rd register and the Rd field to encode
|
1541
|
+
// the Rn register.
|
1542
|
+
Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
|
1543
|
+
}
|
1544
|
+
} else {
|
1545
|
+
// The signed/long multiply instructions use the terms RdHi and RdLo
|
1546
|
+
// when referring to the target registers. They are mapped to the Rn
|
1547
|
+
// and Rd fields as follows:
|
1548
|
+
// RdLo == Rd
|
1549
|
+
// RdHi == Rn (This is confusingly stored in variable rd here
|
1550
|
+
// because the mul instruction from above uses the
|
1551
|
+
// Rn field to encode the Rd register. Good luck figuring
|
1552
|
+
// this out without reading the ARM instruction manual
|
1553
|
+
// at a very detailed level.)
|
1554
|
+
// Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
|
1555
|
+
int rd_hi = rn; // Remap the rn field to the RdHi register.
|
1556
|
+
int rd_lo = instr->RdField();
|
1557
|
+
int32_t hi_res = 0;
|
1558
|
+
int32_t lo_res = 0;
|
1559
|
+
if (instr->Bit(22) == 1) {
|
1560
|
+
int64_t left_op = static_cast<int32_t>(rm_val);
|
1561
|
+
int64_t right_op = static_cast<int32_t>(rs_val);
|
1562
|
+
uint64_t result = left_op * right_op;
|
1563
|
+
hi_res = static_cast<int32_t>(result >> 32);
|
1564
|
+
lo_res = static_cast<int32_t>(result & 0xffffffff);
|
1565
|
+
} else {
|
1566
|
+
// unsigned multiply
|
1567
|
+
uint64_t left_op = static_cast<uint32_t>(rm_val);
|
1568
|
+
uint64_t right_op = static_cast<uint32_t>(rs_val);
|
1569
|
+
uint64_t result = left_op * right_op;
|
1570
|
+
hi_res = static_cast<int32_t>(result >> 32);
|
1571
|
+
lo_res = static_cast<int32_t>(result & 0xffffffff);
|
1572
|
+
}
|
1573
|
+
set_register(rd_lo, lo_res);
|
1574
|
+
set_register(rd_hi, hi_res);
|
1575
|
+
if (instr->HasS()) {
|
1576
|
+
UNIMPLEMENTED();
|
1577
|
+
}
|
1578
|
+
}
|
1579
|
+
} else {
|
1580
|
+
UNIMPLEMENTED(); // Not used by V8.
|
1581
|
+
}
|
1582
|
+
} else {
|
1583
|
+
// extra load/store instructions
|
1584
|
+
int rd = instr->RdField();
|
1585
|
+
int rn = instr->RnField();
|
1586
|
+
int32_t rn_val = get_register(rn);
|
1587
|
+
int32_t addr = 0;
|
1588
|
+
if (instr->Bit(22) == 0) {
|
1589
|
+
int rm = instr->RmField();
|
1590
|
+
int32_t rm_val = get_register(rm);
|
1591
|
+
switch (instr->PUField()) {
|
1592
|
+
case 0: {
|
1593
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
|
1594
|
+
ASSERT(!instr->HasW());
|
1595
|
+
addr = rn_val;
|
1596
|
+
rn_val -= rm_val;
|
1597
|
+
set_register(rn, rn_val);
|
1598
|
+
break;
|
1599
|
+
}
|
1600
|
+
case 1: {
|
1601
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
|
1602
|
+
ASSERT(!instr->HasW());
|
1603
|
+
addr = rn_val;
|
1604
|
+
rn_val += rm_val;
|
1605
|
+
set_register(rn, rn_val);
|
1606
|
+
break;
|
1607
|
+
}
|
1608
|
+
case 2: {
|
1609
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
|
1610
|
+
rn_val -= rm_val;
|
1611
|
+
addr = rn_val;
|
1612
|
+
if (instr->HasW()) {
|
1613
|
+
set_register(rn, rn_val);
|
1614
|
+
}
|
1615
|
+
break;
|
1616
|
+
}
|
1617
|
+
case 3: {
|
1618
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
|
1619
|
+
rn_val += rm_val;
|
1620
|
+
addr = rn_val;
|
1621
|
+
if (instr->HasW()) {
|
1622
|
+
set_register(rn, rn_val);
|
1623
|
+
}
|
1624
|
+
break;
|
1625
|
+
}
|
1626
|
+
default: {
|
1627
|
+
// The PU field is a 2-bit field.
|
1628
|
+
UNREACHABLE();
|
1629
|
+
break;
|
1630
|
+
}
|
1631
|
+
}
|
1632
|
+
} else {
|
1633
|
+
int32_t imm_val = (instr->ImmedHField() << 4) | instr->ImmedLField();
|
1634
|
+
switch (instr->PUField()) {
|
1635
|
+
case 0: {
|
1636
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
|
1637
|
+
ASSERT(!instr->HasW());
|
1638
|
+
addr = rn_val;
|
1639
|
+
rn_val -= imm_val;
|
1640
|
+
set_register(rn, rn_val);
|
1641
|
+
break;
|
1642
|
+
}
|
1643
|
+
case 1: {
|
1644
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
|
1645
|
+
ASSERT(!instr->HasW());
|
1646
|
+
addr = rn_val;
|
1647
|
+
rn_val += imm_val;
|
1648
|
+
set_register(rn, rn_val);
|
1649
|
+
break;
|
1650
|
+
}
|
1651
|
+
case 2: {
|
1652
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
|
1653
|
+
rn_val -= imm_val;
|
1654
|
+
addr = rn_val;
|
1655
|
+
if (instr->HasW()) {
|
1656
|
+
set_register(rn, rn_val);
|
1657
|
+
}
|
1658
|
+
break;
|
1659
|
+
}
|
1660
|
+
case 3: {
|
1661
|
+
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
|
1662
|
+
rn_val += imm_val;
|
1663
|
+
addr = rn_val;
|
1664
|
+
if (instr->HasW()) {
|
1665
|
+
set_register(rn, rn_val);
|
1666
|
+
}
|
1667
|
+
break;
|
1668
|
+
}
|
1669
|
+
default: {
|
1670
|
+
// The PU field is a 2-bit field.
|
1671
|
+
UNREACHABLE();
|
1672
|
+
break;
|
1673
|
+
}
|
1674
|
+
}
|
1675
|
+
}
|
1676
|
+
if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
|
1677
|
+
ASSERT((rd % 2) == 0);
|
1678
|
+
if (instr->HasH()) {
|
1679
|
+
// The strd instruction.
|
1680
|
+
int32_t value1 = get_register(rd);
|
1681
|
+
int32_t value2 = get_register(rd+1);
|
1682
|
+
WriteDW(addr, value1, value2);
|
1683
|
+
} else {
|
1684
|
+
// The ldrd instruction.
|
1685
|
+
int* rn_data = ReadDW(addr);
|
1686
|
+
set_dw_register(rd, rn_data);
|
1687
|
+
}
|
1688
|
+
} else if (instr->HasH()) {
|
1689
|
+
if (instr->HasSign()) {
|
1690
|
+
if (instr->HasL()) {
|
1691
|
+
int16_t val = ReadH(addr, instr);
|
1692
|
+
set_register(rd, val);
|
1693
|
+
} else {
|
1694
|
+
int16_t val = get_register(rd);
|
1695
|
+
WriteH(addr, val, instr);
|
1696
|
+
}
|
1697
|
+
} else {
|
1698
|
+
if (instr->HasL()) {
|
1699
|
+
uint16_t val = ReadHU(addr, instr);
|
1700
|
+
set_register(rd, val);
|
1701
|
+
} else {
|
1702
|
+
uint16_t val = get_register(rd);
|
1703
|
+
WriteH(addr, val, instr);
|
1704
|
+
}
|
1705
|
+
}
|
1706
|
+
} else {
|
1707
|
+
// signed byte loads
|
1708
|
+
ASSERT(instr->HasSign());
|
1709
|
+
ASSERT(instr->HasL());
|
1710
|
+
int8_t val = ReadB(addr);
|
1711
|
+
set_register(rd, val);
|
1712
|
+
}
|
1713
|
+
return;
|
1714
|
+
}
|
1715
|
+
} else if ((type == 0) && instr->IsMiscType0()) {
|
1716
|
+
if (instr->Bits(22, 21) == 1) {
|
1717
|
+
int rm = instr->RmField();
|
1718
|
+
switch (instr->Bits(7, 4)) {
|
1719
|
+
case BX:
|
1720
|
+
set_pc(get_register(rm));
|
1721
|
+
break;
|
1722
|
+
case BLX: {
|
1723
|
+
uint32_t old_pc = get_pc();
|
1724
|
+
set_pc(get_register(rm));
|
1725
|
+
set_register(lr, old_pc + Instr::kInstrSize);
|
1726
|
+
break;
|
1727
|
+
}
|
1728
|
+
case BKPT:
|
1729
|
+
v8::internal::OS::DebugBreak();
|
1730
|
+
break;
|
1731
|
+
default:
|
1732
|
+
UNIMPLEMENTED();
|
1733
|
+
}
|
1734
|
+
} else if (instr->Bits(22, 21) == 3) {
|
1735
|
+
int rm = instr->RmField();
|
1736
|
+
int rd = instr->RdField();
|
1737
|
+
switch (instr->Bits(7, 4)) {
|
1738
|
+
case CLZ: {
|
1739
|
+
uint32_t bits = get_register(rm);
|
1740
|
+
int leading_zeros = 0;
|
1741
|
+
if (bits == 0) {
|
1742
|
+
leading_zeros = 32;
|
1743
|
+
} else {
|
1744
|
+
while ((bits & 0x80000000u) == 0) {
|
1745
|
+
bits <<= 1;
|
1746
|
+
leading_zeros++;
|
1747
|
+
}
|
1748
|
+
}
|
1749
|
+
set_register(rd, leading_zeros);
|
1750
|
+
break;
|
1751
|
+
}
|
1752
|
+
default:
|
1753
|
+
UNIMPLEMENTED();
|
1754
|
+
}
|
1755
|
+
} else {
|
1756
|
+
PrintF("%08x\n", instr->InstructionBits());
|
1757
|
+
UNIMPLEMENTED();
|
1758
|
+
}
|
1759
|
+
} else {
|
1760
|
+
int rd = instr->RdField();
|
1761
|
+
int rn = instr->RnField();
|
1762
|
+
int32_t rn_val = get_register(rn);
|
1763
|
+
int32_t shifter_operand = 0;
|
1764
|
+
bool shifter_carry_out = 0;
|
1765
|
+
if (type == 0) {
|
1766
|
+
shifter_operand = GetShiftRm(instr, &shifter_carry_out);
|
1767
|
+
} else {
|
1768
|
+
ASSERT(instr->TypeField() == 1);
|
1769
|
+
shifter_operand = GetImm(instr, &shifter_carry_out);
|
1770
|
+
}
|
1771
|
+
int32_t alu_out;
|
1772
|
+
|
1773
|
+
switch (instr->OpcodeField()) {
|
1774
|
+
case AND: {
|
1775
|
+
// Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
|
1776
|
+
// Format(instr, "and'cond's 'rd, 'rn, 'imm");
|
1777
|
+
alu_out = rn_val & shifter_operand;
|
1778
|
+
set_register(rd, alu_out);
|
1779
|
+
if (instr->HasS()) {
|
1780
|
+
SetNZFlags(alu_out);
|
1781
|
+
SetCFlag(shifter_carry_out);
|
1782
|
+
}
|
1783
|
+
break;
|
1784
|
+
}
|
1785
|
+
|
1786
|
+
case EOR: {
|
1787
|
+
// Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
|
1788
|
+
// Format(instr, "eor'cond's 'rd, 'rn, 'imm");
|
1789
|
+
alu_out = rn_val ^ shifter_operand;
|
1790
|
+
set_register(rd, alu_out);
|
1791
|
+
if (instr->HasS()) {
|
1792
|
+
SetNZFlags(alu_out);
|
1793
|
+
SetCFlag(shifter_carry_out);
|
1794
|
+
}
|
1795
|
+
break;
|
1796
|
+
}
|
1797
|
+
|
1798
|
+
case SUB: {
|
1799
|
+
// Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
|
1800
|
+
// Format(instr, "sub'cond's 'rd, 'rn, 'imm");
|
1801
|
+
alu_out = rn_val - shifter_operand;
|
1802
|
+
set_register(rd, alu_out);
|
1803
|
+
if (instr->HasS()) {
|
1804
|
+
SetNZFlags(alu_out);
|
1805
|
+
SetCFlag(!BorrowFrom(rn_val, shifter_operand));
|
1806
|
+
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
|
1807
|
+
}
|
1808
|
+
break;
|
1809
|
+
}
|
1810
|
+
|
1811
|
+
case RSB: {
|
1812
|
+
// Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
|
1813
|
+
// Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
|
1814
|
+
alu_out = shifter_operand - rn_val;
|
1815
|
+
set_register(rd, alu_out);
|
1816
|
+
if (instr->HasS()) {
|
1817
|
+
SetNZFlags(alu_out);
|
1818
|
+
SetCFlag(!BorrowFrom(shifter_operand, rn_val));
|
1819
|
+
SetVFlag(OverflowFrom(alu_out, shifter_operand, rn_val, false));
|
1820
|
+
}
|
1821
|
+
break;
|
1822
|
+
}
|
1823
|
+
|
1824
|
+
case ADD: {
|
1825
|
+
// Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
|
1826
|
+
// Format(instr, "add'cond's 'rd, 'rn, 'imm");
|
1827
|
+
alu_out = rn_val + shifter_operand;
|
1828
|
+
set_register(rd, alu_out);
|
1829
|
+
if (instr->HasS()) {
|
1830
|
+
SetNZFlags(alu_out);
|
1831
|
+
SetCFlag(CarryFrom(rn_val, shifter_operand));
|
1832
|
+
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
|
1833
|
+
}
|
1834
|
+
break;
|
1835
|
+
}
|
1836
|
+
|
1837
|
+
case ADC: {
|
1838
|
+
Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
|
1839
|
+
Format(instr, "adc'cond's 'rd, 'rn, 'imm");
|
1840
|
+
break;
|
1841
|
+
}
|
1842
|
+
|
1843
|
+
case SBC: {
|
1844
|
+
Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
|
1845
|
+
Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
|
1846
|
+
break;
|
1847
|
+
}
|
1848
|
+
|
1849
|
+
case RSC: {
|
1850
|
+
Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
|
1851
|
+
Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
|
1852
|
+
break;
|
1853
|
+
}
|
1854
|
+
|
1855
|
+
case TST: {
|
1856
|
+
if (instr->HasS()) {
|
1857
|
+
// Format(instr, "tst'cond 'rn, 'shift_rm");
|
1858
|
+
// Format(instr, "tst'cond 'rn, 'imm");
|
1859
|
+
alu_out = rn_val & shifter_operand;
|
1860
|
+
SetNZFlags(alu_out);
|
1861
|
+
SetCFlag(shifter_carry_out);
|
1862
|
+
} else {
|
1863
|
+
// Format(instr, "movw'cond 'rd, 'imm").
|
1864
|
+
alu_out = instr->ImmedMovwMovtField();
|
1865
|
+
set_register(rd, alu_out);
|
1866
|
+
}
|
1867
|
+
break;
|
1868
|
+
}
|
1869
|
+
|
1870
|
+
case TEQ: {
|
1871
|
+
if (instr->HasS()) {
|
1872
|
+
// Format(instr, "teq'cond 'rn, 'shift_rm");
|
1873
|
+
// Format(instr, "teq'cond 'rn, 'imm");
|
1874
|
+
alu_out = rn_val ^ shifter_operand;
|
1875
|
+
SetNZFlags(alu_out);
|
1876
|
+
SetCFlag(shifter_carry_out);
|
1877
|
+
} else {
|
1878
|
+
// Other instructions matching this pattern are handled in the
|
1879
|
+
// miscellaneous instructions part above.
|
1880
|
+
UNREACHABLE();
|
1881
|
+
}
|
1882
|
+
break;
|
1883
|
+
}
|
1884
|
+
|
1885
|
+
case CMP: {
|
1886
|
+
if (instr->HasS()) {
|
1887
|
+
// Format(instr, "cmp'cond 'rn, 'shift_rm");
|
1888
|
+
// Format(instr, "cmp'cond 'rn, 'imm");
|
1889
|
+
alu_out = rn_val - shifter_operand;
|
1890
|
+
SetNZFlags(alu_out);
|
1891
|
+
SetCFlag(!BorrowFrom(rn_val, shifter_operand));
|
1892
|
+
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
|
1893
|
+
} else {
|
1894
|
+
// Format(instr, "movt'cond 'rd, 'imm").
|
1895
|
+
alu_out = (get_register(rd) & 0xffff) |
|
1896
|
+
(instr->ImmedMovwMovtField() << 16);
|
1897
|
+
set_register(rd, alu_out);
|
1898
|
+
}
|
1899
|
+
break;
|
1900
|
+
}
|
1901
|
+
|
1902
|
+
case CMN: {
|
1903
|
+
if (instr->HasS()) {
|
1904
|
+
// Format(instr, "cmn'cond 'rn, 'shift_rm");
|
1905
|
+
// Format(instr, "cmn'cond 'rn, 'imm");
|
1906
|
+
alu_out = rn_val + shifter_operand;
|
1907
|
+
SetNZFlags(alu_out);
|
1908
|
+
SetCFlag(!CarryFrom(rn_val, shifter_operand));
|
1909
|
+
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
|
1910
|
+
} else {
|
1911
|
+
// Other instructions matching this pattern are handled in the
|
1912
|
+
// miscellaneous instructions part above.
|
1913
|
+
UNREACHABLE();
|
1914
|
+
}
|
1915
|
+
break;
|
1916
|
+
}
|
1917
|
+
|
1918
|
+
case ORR: {
|
1919
|
+
// Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
|
1920
|
+
// Format(instr, "orr'cond's 'rd, 'rn, 'imm");
|
1921
|
+
alu_out = rn_val | shifter_operand;
|
1922
|
+
set_register(rd, alu_out);
|
1923
|
+
if (instr->HasS()) {
|
1924
|
+
SetNZFlags(alu_out);
|
1925
|
+
SetCFlag(shifter_carry_out);
|
1926
|
+
}
|
1927
|
+
break;
|
1928
|
+
}
|
1929
|
+
|
1930
|
+
case MOV: {
|
1931
|
+
// Format(instr, "mov'cond's 'rd, 'shift_rm");
|
1932
|
+
// Format(instr, "mov'cond's 'rd, 'imm");
|
1933
|
+
alu_out = shifter_operand;
|
1934
|
+
set_register(rd, alu_out);
|
1935
|
+
if (instr->HasS()) {
|
1936
|
+
SetNZFlags(alu_out);
|
1937
|
+
SetCFlag(shifter_carry_out);
|
1938
|
+
}
|
1939
|
+
break;
|
1940
|
+
}
|
1941
|
+
|
1942
|
+
case BIC: {
|
1943
|
+
// Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
|
1944
|
+
// Format(instr, "bic'cond's 'rd, 'rn, 'imm");
|
1945
|
+
alu_out = rn_val & ~shifter_operand;
|
1946
|
+
set_register(rd, alu_out);
|
1947
|
+
if (instr->HasS()) {
|
1948
|
+
SetNZFlags(alu_out);
|
1949
|
+
SetCFlag(shifter_carry_out);
|
1950
|
+
}
|
1951
|
+
break;
|
1952
|
+
}
|
1953
|
+
|
1954
|
+
case MVN: {
|
1955
|
+
// Format(instr, "mvn'cond's 'rd, 'shift_rm");
|
1956
|
+
// Format(instr, "mvn'cond's 'rd, 'imm");
|
1957
|
+
alu_out = ~shifter_operand;
|
1958
|
+
set_register(rd, alu_out);
|
1959
|
+
if (instr->HasS()) {
|
1960
|
+
SetNZFlags(alu_out);
|
1961
|
+
SetCFlag(shifter_carry_out);
|
1962
|
+
}
|
1963
|
+
break;
|
1964
|
+
}
|
1965
|
+
|
1966
|
+
default: {
|
1967
|
+
UNREACHABLE();
|
1968
|
+
break;
|
1969
|
+
}
|
1970
|
+
}
|
1971
|
+
}
|
1972
|
+
}
|
1973
|
+
|
1974
|
+
|
1975
|
+
void Simulator::DecodeType2(Instr* instr) {
|
1976
|
+
int rd = instr->RdField();
|
1977
|
+
int rn = instr->RnField();
|
1978
|
+
int32_t rn_val = get_register(rn);
|
1979
|
+
int32_t im_val = instr->Offset12Field();
|
1980
|
+
int32_t addr = 0;
|
1981
|
+
switch (instr->PUField()) {
|
1982
|
+
case 0: {
|
1983
|
+
// Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
|
1984
|
+
ASSERT(!instr->HasW());
|
1985
|
+
addr = rn_val;
|
1986
|
+
rn_val -= im_val;
|
1987
|
+
set_register(rn, rn_val);
|
1988
|
+
break;
|
1989
|
+
}
|
1990
|
+
case 1: {
|
1991
|
+
// Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
|
1992
|
+
ASSERT(!instr->HasW());
|
1993
|
+
addr = rn_val;
|
1994
|
+
rn_val += im_val;
|
1995
|
+
set_register(rn, rn_val);
|
1996
|
+
break;
|
1997
|
+
}
|
1998
|
+
case 2: {
|
1999
|
+
// Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
|
2000
|
+
rn_val -= im_val;
|
2001
|
+
addr = rn_val;
|
2002
|
+
if (instr->HasW()) {
|
2003
|
+
set_register(rn, rn_val);
|
2004
|
+
}
|
2005
|
+
break;
|
2006
|
+
}
|
2007
|
+
case 3: {
|
2008
|
+
// Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
|
2009
|
+
rn_val += im_val;
|
2010
|
+
addr = rn_val;
|
2011
|
+
if (instr->HasW()) {
|
2012
|
+
set_register(rn, rn_val);
|
2013
|
+
}
|
2014
|
+
break;
|
2015
|
+
}
|
2016
|
+
default: {
|
2017
|
+
UNREACHABLE();
|
2018
|
+
break;
|
2019
|
+
}
|
2020
|
+
}
|
2021
|
+
if (instr->HasB()) {
|
2022
|
+
if (instr->HasL()) {
|
2023
|
+
byte val = ReadBU(addr);
|
2024
|
+
set_register(rd, val);
|
2025
|
+
} else {
|
2026
|
+
byte val = get_register(rd);
|
2027
|
+
WriteB(addr, val);
|
2028
|
+
}
|
2029
|
+
} else {
|
2030
|
+
if (instr->HasL()) {
|
2031
|
+
set_register(rd, ReadW(addr, instr));
|
2032
|
+
} else {
|
2033
|
+
WriteW(addr, get_register(rd), instr);
|
2034
|
+
}
|
2035
|
+
}
|
2036
|
+
}
|
2037
|
+
|
2038
|
+
|
2039
|
+
void Simulator::DecodeType3(Instr* instr) {
|
2040
|
+
int rd = instr->RdField();
|
2041
|
+
int rn = instr->RnField();
|
2042
|
+
int32_t rn_val = get_register(rn);
|
2043
|
+
bool shifter_carry_out = 0;
|
2044
|
+
int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
|
2045
|
+
int32_t addr = 0;
|
2046
|
+
switch (instr->PUField()) {
|
2047
|
+
case 0: {
|
2048
|
+
ASSERT(!instr->HasW());
|
2049
|
+
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
|
2050
|
+
UNIMPLEMENTED();
|
2051
|
+
break;
|
2052
|
+
}
|
2053
|
+
case 1: {
|
2054
|
+
if (instr->HasW()) {
|
2055
|
+
ASSERT(instr->Bits(5, 4) == 0x1);
|
2056
|
+
|
2057
|
+
if (instr->Bit(22) == 0x1) { // USAT.
|
2058
|
+
int32_t sat_pos = instr->Bits(20, 16);
|
2059
|
+
int32_t sat_val = (1 << sat_pos) - 1;
|
2060
|
+
int32_t shift = instr->Bits(11, 7);
|
2061
|
+
int32_t shift_type = instr->Bit(6);
|
2062
|
+
int32_t rm_val = get_register(instr->RmField());
|
2063
|
+
if (shift_type == 0) { // LSL
|
2064
|
+
rm_val <<= shift;
|
2065
|
+
} else { // ASR
|
2066
|
+
rm_val >>= shift;
|
2067
|
+
}
|
2068
|
+
// If saturation occurs, the Q flag should be set in the CPSR.
|
2069
|
+
// There is no Q flag yet, and no instruction (MRS) to read the
|
2070
|
+
// CPSR directly.
|
2071
|
+
if (rm_val > sat_val) {
|
2072
|
+
rm_val = sat_val;
|
2073
|
+
} else if (rm_val < 0) {
|
2074
|
+
rm_val = 0;
|
2075
|
+
}
|
2076
|
+
set_register(rd, rm_val);
|
2077
|
+
} else { // SSAT.
|
2078
|
+
UNIMPLEMENTED();
|
2079
|
+
}
|
2080
|
+
return;
|
2081
|
+
} else {
|
2082
|
+
Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
|
2083
|
+
UNIMPLEMENTED();
|
2084
|
+
}
|
2085
|
+
break;
|
2086
|
+
}
|
2087
|
+
case 2: {
|
2088
|
+
// Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
|
2089
|
+
addr = rn_val - shifter_operand;
|
2090
|
+
if (instr->HasW()) {
|
2091
|
+
set_register(rn, addr);
|
2092
|
+
}
|
2093
|
+
break;
|
2094
|
+
}
|
2095
|
+
case 3: {
|
2096
|
+
if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
|
2097
|
+
uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
|
2098
|
+
uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
|
2099
|
+
uint32_t msbit = widthminus1 + lsbit;
|
2100
|
+
if (msbit <= 31) {
|
2101
|
+
if (instr->Bit(22)) {
|
2102
|
+
// ubfx - unsigned bitfield extract.
|
2103
|
+
uint32_t rm_val =
|
2104
|
+
static_cast<uint32_t>(get_register(instr->RmField()));
|
2105
|
+
uint32_t extr_val = rm_val << (31 - msbit);
|
2106
|
+
extr_val = extr_val >> (31 - widthminus1);
|
2107
|
+
set_register(instr->RdField(), extr_val);
|
2108
|
+
} else {
|
2109
|
+
// sbfx - signed bitfield extract.
|
2110
|
+
int32_t rm_val = get_register(instr->RmField());
|
2111
|
+
int32_t extr_val = rm_val << (31 - msbit);
|
2112
|
+
extr_val = extr_val >> (31 - widthminus1);
|
2113
|
+
set_register(instr->RdField(), extr_val);
|
2114
|
+
}
|
2115
|
+
} else {
|
2116
|
+
UNREACHABLE();
|
2117
|
+
}
|
2118
|
+
return;
|
2119
|
+
} else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
|
2120
|
+
uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
|
2121
|
+
uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
|
2122
|
+
if (msbit >= lsbit) {
|
2123
|
+
// bfc or bfi - bitfield clear/insert.
|
2124
|
+
uint32_t rd_val =
|
2125
|
+
static_cast<uint32_t>(get_register(instr->RdField()));
|
2126
|
+
uint32_t bitcount = msbit - lsbit + 1;
|
2127
|
+
uint32_t mask = (1 << bitcount) - 1;
|
2128
|
+
rd_val &= ~(mask << lsbit);
|
2129
|
+
if (instr->RmField() != 15) {
|
2130
|
+
// bfi - bitfield insert.
|
2131
|
+
uint32_t rm_val =
|
2132
|
+
static_cast<uint32_t>(get_register(instr->RmField()));
|
2133
|
+
rm_val &= mask;
|
2134
|
+
rd_val |= rm_val << lsbit;
|
2135
|
+
}
|
2136
|
+
set_register(instr->RdField(), rd_val);
|
2137
|
+
} else {
|
2138
|
+
UNREACHABLE();
|
2139
|
+
}
|
2140
|
+
return;
|
2141
|
+
} else {
|
2142
|
+
// Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
|
2143
|
+
addr = rn_val + shifter_operand;
|
2144
|
+
if (instr->HasW()) {
|
2145
|
+
set_register(rn, addr);
|
2146
|
+
}
|
2147
|
+
}
|
2148
|
+
break;
|
2149
|
+
}
|
2150
|
+
default: {
|
2151
|
+
UNREACHABLE();
|
2152
|
+
break;
|
2153
|
+
}
|
2154
|
+
}
|
2155
|
+
if (instr->HasB()) {
|
2156
|
+
if (instr->HasL()) {
|
2157
|
+
uint8_t byte = ReadB(addr);
|
2158
|
+
set_register(rd, byte);
|
2159
|
+
} else {
|
2160
|
+
uint8_t byte = get_register(rd);
|
2161
|
+
WriteB(addr, byte);
|
2162
|
+
}
|
2163
|
+
} else {
|
2164
|
+
if (instr->HasL()) {
|
2165
|
+
set_register(rd, ReadW(addr, instr));
|
2166
|
+
} else {
|
2167
|
+
WriteW(addr, get_register(rd), instr);
|
2168
|
+
}
|
2169
|
+
}
|
2170
|
+
}
|
2171
|
+
|
2172
|
+
|
2173
|
+
void Simulator::DecodeType4(Instr* instr) {
|
2174
|
+
ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode
|
2175
|
+
if (instr->HasL()) {
|
2176
|
+
// Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
|
2177
|
+
HandleRList(instr, true);
|
2178
|
+
} else {
|
2179
|
+
// Format(instr, "stm'cond'pu 'rn'w, 'rlist");
|
2180
|
+
HandleRList(instr, false);
|
2181
|
+
}
|
2182
|
+
}
|
2183
|
+
|
2184
|
+
|
2185
|
+
void Simulator::DecodeType5(Instr* instr) {
|
2186
|
+
// Format(instr, "b'l'cond 'target");
|
2187
|
+
int off = (instr->SImmed24Field() << 2);
|
2188
|
+
intptr_t pc_address = get_pc();
|
2189
|
+
if (instr->HasLink()) {
|
2190
|
+
set_register(lr, pc_address + Instr::kInstrSize);
|
2191
|
+
}
|
2192
|
+
int pc_reg = get_register(pc);
|
2193
|
+
set_pc(pc_reg + off);
|
2194
|
+
}
|
2195
|
+
|
2196
|
+
|
2197
|
+
void Simulator::DecodeType6(Instr* instr) {
|
2198
|
+
DecodeType6CoprocessorIns(instr);
|
2199
|
+
}
|
2200
|
+
|
2201
|
+
|
2202
|
+
void Simulator::DecodeType7(Instr* instr) {
|
2203
|
+
if (instr->Bit(24) == 1) {
|
2204
|
+
SoftwareInterrupt(instr);
|
2205
|
+
} else {
|
2206
|
+
DecodeTypeVFP(instr);
|
2207
|
+
}
|
2208
|
+
}
|
2209
|
+
|
2210
|
+
|
2211
|
+
void Simulator::DecodeUnconditional(Instr* instr) {
|
2212
|
+
if (instr->Bits(7, 4) == 0x0B && instr->Bits(27, 25) == 0 && instr->HasL()) {
|
2213
|
+
// Load halfword instruction, either register or immediate offset.
|
2214
|
+
int rd = instr->RdField();
|
2215
|
+
int rn = instr->RnField();
|
2216
|
+
int32_t rn_val = get_register(rn);
|
2217
|
+
int32_t addr = 0;
|
2218
|
+
int32_t offset;
|
2219
|
+
if (instr->Bit(22) == 0) {
|
2220
|
+
// Register offset.
|
2221
|
+
int rm = instr->RmField();
|
2222
|
+
offset = get_register(rm);
|
2223
|
+
} else {
|
2224
|
+
// Immediate offset
|
2225
|
+
offset = instr->Bits(3, 0) + (instr->Bits(11, 8) << 4);
|
2226
|
+
}
|
2227
|
+
switch (instr->PUField()) {
|
2228
|
+
case 0: {
|
2229
|
+
// Post index, negative.
|
2230
|
+
ASSERT(!instr->HasW());
|
2231
|
+
addr = rn_val;
|
2232
|
+
rn_val -= offset;
|
2233
|
+
set_register(rn, rn_val);
|
2234
|
+
break;
|
2235
|
+
}
|
2236
|
+
case 1: {
|
2237
|
+
// Post index, positive.
|
2238
|
+
ASSERT(!instr->HasW());
|
2239
|
+
addr = rn_val;
|
2240
|
+
rn_val += offset;
|
2241
|
+
set_register(rn, rn_val);
|
2242
|
+
break;
|
2243
|
+
}
|
2244
|
+
case 2: {
|
2245
|
+
// Pre index or offset, negative.
|
2246
|
+
rn_val -= offset;
|
2247
|
+
addr = rn_val;
|
2248
|
+
if (instr->HasW()) {
|
2249
|
+
set_register(rn, rn_val);
|
2250
|
+
}
|
2251
|
+
break;
|
2252
|
+
}
|
2253
|
+
case 3: {
|
2254
|
+
// Pre index or offset, positive.
|
2255
|
+
rn_val += offset;
|
2256
|
+
addr = rn_val;
|
2257
|
+
if (instr->HasW()) {
|
2258
|
+
set_register(rn, rn_val);
|
2259
|
+
}
|
2260
|
+
break;
|
2261
|
+
}
|
2262
|
+
default: {
|
2263
|
+
// The PU field is a 2-bit field.
|
2264
|
+
UNREACHABLE();
|
2265
|
+
break;
|
2266
|
+
}
|
2267
|
+
}
|
2268
|
+
// Not sign extending, so load as unsigned.
|
2269
|
+
uint16_t halfword = ReadH(addr, instr);
|
2270
|
+
set_register(rd, halfword);
|
2271
|
+
} else {
|
2272
|
+
Debugger dbg(this);
|
2273
|
+
dbg.Stop(instr);
|
2274
|
+
}
|
2275
|
+
}
|
2276
|
+
|
2277
|
+
|
2278
|
+
// Depending on value of last_bit flag glue register code from vm and m values
|
2279
|
+
// (where m is expected to be a single bit).
|
2280
|
+
static int GlueRegCode(bool last_bit, int vm, int m) {
|
2281
|
+
return last_bit ? ((vm << 1) | m) : ((m << 4) | vm);
|
2282
|
+
}
|
2283
|
+
|
2284
|
+
|
2285
|
+
// void Simulator::DecodeTypeVFP(Instr* instr)
|
2286
|
+
// The Following ARMv7 VFPv instructions are currently supported.
|
2287
|
+
// vmov :Sn = Rt
|
2288
|
+
// vmov :Rt = Sn
|
2289
|
+
// vcvt: Dd = Sm
|
2290
|
+
// vcvt: Sd = Dm
|
2291
|
+
// Dd = vadd(Dn, Dm)
|
2292
|
+
// Dd = vsub(Dn, Dm)
|
2293
|
+
// Dd = vmul(Dn, Dm)
|
2294
|
+
// Dd = vdiv(Dn, Dm)
|
2295
|
+
// vcmp(Dd, Dm)
|
2296
|
+
// vmrs
|
2297
|
+
// Dd = vsqrt(Dm)
|
2298
|
+
void Simulator::DecodeTypeVFP(Instr* instr) {
|
2299
|
+
ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) );
|
2300
|
+
ASSERT(instr->Bits(11, 9) == 0x5);
|
2301
|
+
|
2302
|
+
int vm = instr->VmField();
|
2303
|
+
int vd = instr->VdField();
|
2304
|
+
int vn = instr->VnField();
|
2305
|
+
|
2306
|
+
if (instr->Bit(4) == 0) {
|
2307
|
+
if (instr->Opc1Field() == 0x7) {
|
2308
|
+
// Other data processing instructions
|
2309
|
+
if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) {
|
2310
|
+
// vmov register to register.
|
2311
|
+
if (instr->SzField() == 0x1) {
|
2312
|
+
set_d_register_from_double(vd, get_double_from_d_register(vm));
|
2313
|
+
} else {
|
2314
|
+
set_s_register_from_float(vd, get_float_from_s_register(vm));
|
2315
|
+
}
|
2316
|
+
} else if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
|
2317
|
+
DecodeVCVTBetweenDoubleAndSingle(instr);
|
2318
|
+
} else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) {
|
2319
|
+
DecodeVCVTBetweenFloatingPointAndInteger(instr);
|
2320
|
+
} else if (((instr->Opc2Field() >> 1) == 0x6) &&
|
2321
|
+
(instr->Opc3Field() & 0x1)) {
|
2322
|
+
DecodeVCVTBetweenFloatingPointAndInteger(instr);
|
2323
|
+
} else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
|
2324
|
+
(instr->Opc3Field() & 0x1)) {
|
2325
|
+
DecodeVCMP(instr);
|
2326
|
+
} else if (((instr->Opc2Field() == 0x1)) && (instr->Opc3Field() == 0x3)) {
|
2327
|
+
// vsqrt
|
2328
|
+
double dm_value = get_double_from_d_register(vm);
|
2329
|
+
double dd_value = sqrt(dm_value);
|
2330
|
+
set_d_register_from_double(vd, dd_value);
|
2331
|
+
} else if (instr->Opc3Field() == 0x0) {
|
2332
|
+
// vmov immediate.
|
2333
|
+
if (instr->SzField() == 0x1) {
|
2334
|
+
set_d_register_from_double(vd, instr->DoubleImmedVmov());
|
2335
|
+
} else {
|
2336
|
+
UNREACHABLE(); // Not used by v8.
|
2337
|
+
}
|
2338
|
+
} else {
|
2339
|
+
UNREACHABLE(); // Not used by V8.
|
2340
|
+
}
|
2341
|
+
} else if (instr->Opc1Field() == 0x3) {
|
2342
|
+
if (instr->SzField() != 0x1) {
|
2343
|
+
UNREACHABLE(); // Not used by V8.
|
2344
|
+
}
|
2345
|
+
|
2346
|
+
if (instr->Opc3Field() & 0x1) {
|
2347
|
+
// vsub
|
2348
|
+
double dn_value = get_double_from_d_register(vn);
|
2349
|
+
double dm_value = get_double_from_d_register(vm);
|
2350
|
+
double dd_value = dn_value - dm_value;
|
2351
|
+
set_d_register_from_double(vd, dd_value);
|
2352
|
+
} else {
|
2353
|
+
// vadd
|
2354
|
+
double dn_value = get_double_from_d_register(vn);
|
2355
|
+
double dm_value = get_double_from_d_register(vm);
|
2356
|
+
double dd_value = dn_value + dm_value;
|
2357
|
+
set_d_register_from_double(vd, dd_value);
|
2358
|
+
}
|
2359
|
+
} else if ((instr->Opc1Field() == 0x2) && !(instr->Opc3Field() & 0x1)) {
|
2360
|
+
// vmul
|
2361
|
+
if (instr->SzField() != 0x1) {
|
2362
|
+
UNREACHABLE(); // Not used by V8.
|
2363
|
+
}
|
2364
|
+
|
2365
|
+
double dn_value = get_double_from_d_register(vn);
|
2366
|
+
double dm_value = get_double_from_d_register(vm);
|
2367
|
+
double dd_value = dn_value * dm_value;
|
2368
|
+
set_d_register_from_double(vd, dd_value);
|
2369
|
+
} else if ((instr->Opc1Field() == 0x4) && !(instr->Opc3Field() & 0x1)) {
|
2370
|
+
// vdiv
|
2371
|
+
if (instr->SzField() != 0x1) {
|
2372
|
+
UNREACHABLE(); // Not used by V8.
|
2373
|
+
}
|
2374
|
+
|
2375
|
+
double dn_value = get_double_from_d_register(vn);
|
2376
|
+
double dm_value = get_double_from_d_register(vm);
|
2377
|
+
double dd_value = dn_value / dm_value;
|
2378
|
+
set_d_register_from_double(vd, dd_value);
|
2379
|
+
} else {
|
2380
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2381
|
+
}
|
2382
|
+
} else {
|
2383
|
+
if ((instr->VCField() == 0x0) &&
|
2384
|
+
(instr->VAField() == 0x0)) {
|
2385
|
+
DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
|
2386
|
+
} else if ((instr->VLField() == 0x1) &&
|
2387
|
+
(instr->VCField() == 0x0) &&
|
2388
|
+
(instr->VAField() == 0x7) &&
|
2389
|
+
(instr->Bits(19, 16) == 0x1)) {
|
2390
|
+
// vmrs
|
2391
|
+
if (instr->RtField() == 0xF)
|
2392
|
+
Copy_FPSCR_to_APSR();
|
2393
|
+
else
|
2394
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2395
|
+
} else {
|
2396
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2397
|
+
}
|
2398
|
+
}
|
2399
|
+
}
|
2400
|
+
|
2401
|
+
|
2402
|
+
void Simulator::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) {
|
2403
|
+
ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) &&
|
2404
|
+
(instr->VAField() == 0x0));
|
2405
|
+
|
2406
|
+
int t = instr->RtField();
|
2407
|
+
int n = GlueRegCode(true, instr->VnField(), instr->NField());
|
2408
|
+
bool to_arm_register = (instr->VLField() == 0x1);
|
2409
|
+
|
2410
|
+
if (to_arm_register) {
|
2411
|
+
int32_t int_value = get_sinteger_from_s_register(n);
|
2412
|
+
set_register(t, int_value);
|
2413
|
+
} else {
|
2414
|
+
int32_t rs_val = get_register(t);
|
2415
|
+
set_s_register_from_sinteger(n, rs_val);
|
2416
|
+
}
|
2417
|
+
}
|
2418
|
+
|
2419
|
+
|
2420
|
+
void Simulator::DecodeVCMP(Instr* instr) {
|
2421
|
+
ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
|
2422
|
+
ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
|
2423
|
+
(instr->Opc3Field() & 0x1));
|
2424
|
+
|
2425
|
+
// Comparison.
|
2426
|
+
bool dp_operation = (instr->SzField() == 1);
|
2427
|
+
|
2428
|
+
if (instr->Bit(7) != 0) {
|
2429
|
+
// Raising exceptions for quiet NaNs are not supported.
|
2430
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2431
|
+
}
|
2432
|
+
|
2433
|
+
int d = GlueRegCode(!dp_operation, instr->VdField(), instr->DField());
|
2434
|
+
int m = GlueRegCode(!dp_operation, instr->VmField(), instr->MField());
|
2435
|
+
|
2436
|
+
if (dp_operation) {
|
2437
|
+
double dd_value = get_double_from_d_register(d);
|
2438
|
+
double dm_value = get_double_from_d_register(m);
|
2439
|
+
|
2440
|
+
Compute_FPSCR_Flags(dd_value, dm_value);
|
2441
|
+
} else {
|
2442
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2443
|
+
}
|
2444
|
+
}
|
2445
|
+
|
2446
|
+
|
2447
|
+
void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) {
|
2448
|
+
ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
|
2449
|
+
ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3));
|
2450
|
+
|
2451
|
+
bool double_to_single = (instr->SzField() == 1);
|
2452
|
+
int dst = GlueRegCode(double_to_single, instr->VdField(), instr->DField());
|
2453
|
+
int src = GlueRegCode(!double_to_single, instr->VmField(), instr->MField());
|
2454
|
+
|
2455
|
+
if (double_to_single) {
|
2456
|
+
double val = get_double_from_d_register(src);
|
2457
|
+
set_s_register_from_float(dst, static_cast<float>(val));
|
2458
|
+
} else {
|
2459
|
+
float val = get_float_from_s_register(src);
|
2460
|
+
set_d_register_from_double(dst, static_cast<double>(val));
|
2461
|
+
}
|
2462
|
+
}
|
2463
|
+
|
2464
|
+
|
2465
|
+
void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr) {
|
2466
|
+
ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
|
2467
|
+
ASSERT(((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) ||
|
2468
|
+
(((instr->Opc2Field() >> 1) == 0x6) && (instr->Opc3Field() & 0x1)));
|
2469
|
+
|
2470
|
+
// Conversion between floating-point and integer.
|
2471
|
+
int vd = instr->VdField();
|
2472
|
+
int d = instr->DField();
|
2473
|
+
int vm = instr->VmField();
|
2474
|
+
int m = instr->MField();
|
2475
|
+
|
2476
|
+
bool to_integer = (instr->Bit(18) == 1);
|
2477
|
+
bool dp_operation = (instr->SzField() == 1);
|
2478
|
+
if (to_integer) {
|
2479
|
+
bool unsigned_integer = (instr->Bit(16) == 0);
|
2480
|
+
if (instr->Bit(7) != 1) {
|
2481
|
+
// Only rounding towards zero supported.
|
2482
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2483
|
+
}
|
2484
|
+
|
2485
|
+
int dst = GlueRegCode(true, vd, d);
|
2486
|
+
int src = GlueRegCode(!dp_operation, vm, m);
|
2487
|
+
|
2488
|
+
if (dp_operation) {
|
2489
|
+
double val = get_double_from_d_register(src);
|
2490
|
+
|
2491
|
+
int sint = unsigned_integer ? static_cast<uint32_t>(val) :
|
2492
|
+
static_cast<int32_t>(val);
|
2493
|
+
|
2494
|
+
set_s_register_from_sinteger(dst, sint);
|
2495
|
+
} else {
|
2496
|
+
float val = get_float_from_s_register(src);
|
2497
|
+
|
2498
|
+
int sint = unsigned_integer ? static_cast<uint32_t>(val) :
|
2499
|
+
static_cast<int32_t>(val);
|
2500
|
+
|
2501
|
+
set_s_register_from_sinteger(dst, sint);
|
2502
|
+
}
|
2503
|
+
} else {
|
2504
|
+
bool unsigned_integer = (instr->Bit(7) == 0);
|
2505
|
+
|
2506
|
+
int dst = GlueRegCode(!dp_operation, vd, d);
|
2507
|
+
int src = GlueRegCode(true, vm, m);
|
2508
|
+
|
2509
|
+
int val = get_sinteger_from_s_register(src);
|
2510
|
+
|
2511
|
+
if (dp_operation) {
|
2512
|
+
if (unsigned_integer) {
|
2513
|
+
set_d_register_from_double(dst,
|
2514
|
+
static_cast<double>((uint32_t)val));
|
2515
|
+
} else {
|
2516
|
+
set_d_register_from_double(dst, static_cast<double>(val));
|
2517
|
+
}
|
2518
|
+
} else {
|
2519
|
+
if (unsigned_integer) {
|
2520
|
+
set_s_register_from_float(dst,
|
2521
|
+
static_cast<float>((uint32_t)val));
|
2522
|
+
} else {
|
2523
|
+
set_s_register_from_float(dst, static_cast<float>(val));
|
2524
|
+
}
|
2525
|
+
}
|
2526
|
+
}
|
2527
|
+
}
|
2528
|
+
|
2529
|
+
|
2530
|
+
// void Simulator::DecodeType6CoprocessorIns(Instr* instr)
|
2531
|
+
// Decode Type 6 coprocessor instructions.
|
2532
|
+
// Dm = vmov(Rt, Rt2)
|
2533
|
+
// <Rt, Rt2> = vmov(Dm)
|
2534
|
+
// Ddst = MEM(Rbase + 4*offset).
|
2535
|
+
// MEM(Rbase + 4*offset) = Dsrc.
|
2536
|
+
void Simulator::DecodeType6CoprocessorIns(Instr* instr) {
|
2537
|
+
ASSERT((instr->TypeField() == 6));
|
2538
|
+
|
2539
|
+
if (instr->CoprocessorField() == 0xA) {
|
2540
|
+
switch (instr->OpcodeField()) {
|
2541
|
+
case 0x8:
|
2542
|
+
case 0xC: { // Load and store float to memory.
|
2543
|
+
int rn = instr->RnField();
|
2544
|
+
int vd = instr->VdField();
|
2545
|
+
int offset = instr->Immed8Field();
|
2546
|
+
if (!instr->HasU()) {
|
2547
|
+
offset = -offset;
|
2548
|
+
}
|
2549
|
+
|
2550
|
+
int32_t address = get_register(rn) + 4 * offset;
|
2551
|
+
if (instr->HasL()) {
|
2552
|
+
// Load double from memory: vldr.
|
2553
|
+
set_s_register_from_sinteger(vd, ReadW(address, instr));
|
2554
|
+
} else {
|
2555
|
+
// Store double to memory: vstr.
|
2556
|
+
WriteW(address, get_sinteger_from_s_register(vd), instr);
|
2557
|
+
}
|
2558
|
+
break;
|
2559
|
+
}
|
2560
|
+
default:
|
2561
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2562
|
+
break;
|
2563
|
+
}
|
2564
|
+
} else if (instr->CoprocessorField() == 0xB) {
|
2565
|
+
switch (instr->OpcodeField()) {
|
2566
|
+
case 0x2:
|
2567
|
+
// Load and store double to two GP registers
|
2568
|
+
if (instr->Bits(7, 4) != 0x1) {
|
2569
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2570
|
+
} else {
|
2571
|
+
int rt = instr->RtField();
|
2572
|
+
int rn = instr->RnField();
|
2573
|
+
int vm = instr->VmField();
|
2574
|
+
if (instr->HasL()) {
|
2575
|
+
int32_t rt_int_value = get_sinteger_from_s_register(2*vm);
|
2576
|
+
int32_t rn_int_value = get_sinteger_from_s_register(2*vm+1);
|
2577
|
+
|
2578
|
+
set_register(rt, rt_int_value);
|
2579
|
+
set_register(rn, rn_int_value);
|
2580
|
+
} else {
|
2581
|
+
int32_t rs_val = get_register(rt);
|
2582
|
+
int32_t rn_val = get_register(rn);
|
2583
|
+
|
2584
|
+
set_s_register_from_sinteger(2*vm, rs_val);
|
2585
|
+
set_s_register_from_sinteger((2*vm+1), rn_val);
|
2586
|
+
}
|
2587
|
+
}
|
2588
|
+
break;
|
2589
|
+
case 0x8:
|
2590
|
+
case 0xC: { // Load and store double to memory.
|
2591
|
+
int rn = instr->RnField();
|
2592
|
+
int vd = instr->VdField();
|
2593
|
+
int offset = instr->Immed8Field();
|
2594
|
+
if (!instr->HasU()) {
|
2595
|
+
offset = -offset;
|
2596
|
+
}
|
2597
|
+
int32_t address = get_register(rn) + 4 * offset;
|
2598
|
+
if (instr->HasL()) {
|
2599
|
+
// Load double from memory: vldr.
|
2600
|
+
set_s_register_from_sinteger(2*vd, ReadW(address, instr));
|
2601
|
+
set_s_register_from_sinteger(2*vd + 1, ReadW(address + 4, instr));
|
2602
|
+
} else {
|
2603
|
+
// Store double to memory: vstr.
|
2604
|
+
WriteW(address, get_sinteger_from_s_register(2*vd), instr);
|
2605
|
+
WriteW(address + 4, get_sinteger_from_s_register(2*vd + 1), instr);
|
2606
|
+
}
|
2607
|
+
break;
|
2608
|
+
}
|
2609
|
+
default:
|
2610
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2611
|
+
break;
|
2612
|
+
}
|
2613
|
+
} else {
|
2614
|
+
UNIMPLEMENTED(); // Not used by V8.
|
2615
|
+
}
|
2616
|
+
}
|
2617
|
+
|
2618
|
+
|
2619
|
+
// Executes the current instruction.
|
2620
|
+
void Simulator::InstructionDecode(Instr* instr) {
|
2621
|
+
if (v8::internal::FLAG_check_icache) {
|
2622
|
+
CheckICache(instr);
|
2623
|
+
}
|
2624
|
+
pc_modified_ = false;
|
2625
|
+
if (::v8::internal::FLAG_trace_sim) {
|
2626
|
+
disasm::NameConverter converter;
|
2627
|
+
disasm::Disassembler dasm(converter);
|
2628
|
+
// use a reasonably large buffer
|
2629
|
+
v8::internal::EmbeddedVector<char, 256> buffer;
|
2630
|
+
dasm.InstructionDecode(buffer,
|
2631
|
+
reinterpret_cast<byte*>(instr));
|
2632
|
+
PrintF(" 0x%08x %s\n", instr, buffer.start());
|
2633
|
+
}
|
2634
|
+
if (instr->ConditionField() == special_condition) {
|
2635
|
+
DecodeUnconditional(instr);
|
2636
|
+
} else if (ConditionallyExecute(instr)) {
|
2637
|
+
switch (instr->TypeField()) {
|
2638
|
+
case 0:
|
2639
|
+
case 1: {
|
2640
|
+
DecodeType01(instr);
|
2641
|
+
break;
|
2642
|
+
}
|
2643
|
+
case 2: {
|
2644
|
+
DecodeType2(instr);
|
2645
|
+
break;
|
2646
|
+
}
|
2647
|
+
case 3: {
|
2648
|
+
DecodeType3(instr);
|
2649
|
+
break;
|
2650
|
+
}
|
2651
|
+
case 4: {
|
2652
|
+
DecodeType4(instr);
|
2653
|
+
break;
|
2654
|
+
}
|
2655
|
+
case 5: {
|
2656
|
+
DecodeType5(instr);
|
2657
|
+
break;
|
2658
|
+
}
|
2659
|
+
case 6: {
|
2660
|
+
DecodeType6(instr);
|
2661
|
+
break;
|
2662
|
+
}
|
2663
|
+
case 7: {
|
2664
|
+
DecodeType7(instr);
|
2665
|
+
break;
|
2666
|
+
}
|
2667
|
+
default: {
|
2668
|
+
UNIMPLEMENTED();
|
2669
|
+
break;
|
2670
|
+
}
|
2671
|
+
}
|
2672
|
+
}
|
2673
|
+
if (!pc_modified_) {
|
2674
|
+
set_register(pc, reinterpret_cast<int32_t>(instr) + Instr::kInstrSize);
|
2675
|
+
}
|
2676
|
+
}
|
2677
|
+
|
2678
|
+
|
2679
|
+
void Simulator::Execute() {
|
2680
|
+
// Get the PC to simulate. Cannot use the accessor here as we need the
|
2681
|
+
// raw PC value and not the one used as input to arithmetic instructions.
|
2682
|
+
int program_counter = get_pc();
|
2683
|
+
|
2684
|
+
if (::v8::internal::FLAG_stop_sim_at == 0) {
|
2685
|
+
// Fast version of the dispatch loop without checking whether the simulator
|
2686
|
+
// should be stopping at a particular executed instruction.
|
2687
|
+
while (program_counter != end_sim_pc) {
|
2688
|
+
Instr* instr = reinterpret_cast<Instr*>(program_counter);
|
2689
|
+
icount_++;
|
2690
|
+
InstructionDecode(instr);
|
2691
|
+
program_counter = get_pc();
|
2692
|
+
}
|
2693
|
+
} else {
|
2694
|
+
// FLAG_stop_sim_at is at the non-default value. Stop in the debugger when
|
2695
|
+
// we reach the particular instuction count.
|
2696
|
+
while (program_counter != end_sim_pc) {
|
2697
|
+
Instr* instr = reinterpret_cast<Instr*>(program_counter);
|
2698
|
+
icount_++;
|
2699
|
+
if (icount_ == ::v8::internal::FLAG_stop_sim_at) {
|
2700
|
+
Debugger dbg(this);
|
2701
|
+
dbg.Debug();
|
2702
|
+
} else {
|
2703
|
+
InstructionDecode(instr);
|
2704
|
+
}
|
2705
|
+
program_counter = get_pc();
|
2706
|
+
}
|
2707
|
+
}
|
2708
|
+
}
|
2709
|
+
|
2710
|
+
|
2711
|
+
int32_t Simulator::Call(byte* entry, int argument_count, ...) {
|
2712
|
+
va_list parameters;
|
2713
|
+
va_start(parameters, argument_count);
|
2714
|
+
// Setup arguments
|
2715
|
+
|
2716
|
+
// First four arguments passed in registers.
|
2717
|
+
ASSERT(argument_count >= 4);
|
2718
|
+
set_register(r0, va_arg(parameters, int32_t));
|
2719
|
+
set_register(r1, va_arg(parameters, int32_t));
|
2720
|
+
set_register(r2, va_arg(parameters, int32_t));
|
2721
|
+
set_register(r3, va_arg(parameters, int32_t));
|
2722
|
+
|
2723
|
+
// Remaining arguments passed on stack.
|
2724
|
+
int original_stack = get_register(sp);
|
2725
|
+
// Compute position of stack on entry to generated code.
|
2726
|
+
int entry_stack = (original_stack - (argument_count - 4) * sizeof(int32_t));
|
2727
|
+
if (OS::ActivationFrameAlignment() != 0) {
|
2728
|
+
entry_stack &= -OS::ActivationFrameAlignment();
|
2729
|
+
}
|
2730
|
+
// Store remaining arguments on stack, from low to high memory.
|
2731
|
+
intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack);
|
2732
|
+
for (int i = 4; i < argument_count; i++) {
|
2733
|
+
stack_argument[i - 4] = va_arg(parameters, int32_t);
|
2734
|
+
}
|
2735
|
+
va_end(parameters);
|
2736
|
+
set_register(sp, entry_stack);
|
2737
|
+
|
2738
|
+
// Prepare to execute the code at entry
|
2739
|
+
set_register(pc, reinterpret_cast<int32_t>(entry));
|
2740
|
+
// Put down marker for end of simulation. The simulator will stop simulation
|
2741
|
+
// when the PC reaches this value. By saving the "end simulation" value into
|
2742
|
+
// the LR the simulation stops when returning to this call point.
|
2743
|
+
set_register(lr, end_sim_pc);
|
2744
|
+
|
2745
|
+
// Remember the values of callee-saved registers.
|
2746
|
+
// The code below assumes that r9 is not used as sb (static base) in
|
2747
|
+
// simulator code and therefore is regarded as a callee-saved register.
|
2748
|
+
int32_t r4_val = get_register(r4);
|
2749
|
+
int32_t r5_val = get_register(r5);
|
2750
|
+
int32_t r6_val = get_register(r6);
|
2751
|
+
int32_t r7_val = get_register(r7);
|
2752
|
+
int32_t r8_val = get_register(r8);
|
2753
|
+
int32_t r9_val = get_register(r9);
|
2754
|
+
int32_t r10_val = get_register(r10);
|
2755
|
+
int32_t r11_val = get_register(r11);
|
2756
|
+
|
2757
|
+
// Setup the callee-saved registers with a known value. To be able to check
|
2758
|
+
// that they are preserved properly across JS execution.
|
2759
|
+
int32_t callee_saved_value = icount_;
|
2760
|
+
set_register(r4, callee_saved_value);
|
2761
|
+
set_register(r5, callee_saved_value);
|
2762
|
+
set_register(r6, callee_saved_value);
|
2763
|
+
set_register(r7, callee_saved_value);
|
2764
|
+
set_register(r8, callee_saved_value);
|
2765
|
+
set_register(r9, callee_saved_value);
|
2766
|
+
set_register(r10, callee_saved_value);
|
2767
|
+
set_register(r11, callee_saved_value);
|
2768
|
+
|
2769
|
+
// Start the simulation
|
2770
|
+
Execute();
|
2771
|
+
|
2772
|
+
// Check that the callee-saved registers have been preserved.
|
2773
|
+
CHECK_EQ(callee_saved_value, get_register(r4));
|
2774
|
+
CHECK_EQ(callee_saved_value, get_register(r5));
|
2775
|
+
CHECK_EQ(callee_saved_value, get_register(r6));
|
2776
|
+
CHECK_EQ(callee_saved_value, get_register(r7));
|
2777
|
+
CHECK_EQ(callee_saved_value, get_register(r8));
|
2778
|
+
CHECK_EQ(callee_saved_value, get_register(r9));
|
2779
|
+
CHECK_EQ(callee_saved_value, get_register(r10));
|
2780
|
+
CHECK_EQ(callee_saved_value, get_register(r11));
|
2781
|
+
|
2782
|
+
// Restore callee-saved registers with the original value.
|
2783
|
+
set_register(r4, r4_val);
|
2784
|
+
set_register(r5, r5_val);
|
2785
|
+
set_register(r6, r6_val);
|
2786
|
+
set_register(r7, r7_val);
|
2787
|
+
set_register(r8, r8_val);
|
2788
|
+
set_register(r9, r9_val);
|
2789
|
+
set_register(r10, r10_val);
|
2790
|
+
set_register(r11, r11_val);
|
2791
|
+
|
2792
|
+
// Pop stack passed arguments.
|
2793
|
+
CHECK_EQ(entry_stack, get_register(sp));
|
2794
|
+
set_register(sp, original_stack);
|
2795
|
+
|
2796
|
+
int32_t result = get_register(r0);
|
2797
|
+
return result;
|
2798
|
+
}
|
2799
|
+
|
2800
|
+
|
2801
|
+
uintptr_t Simulator::PushAddress(uintptr_t address) {
|
2802
|
+
int new_sp = get_register(sp) - sizeof(uintptr_t);
|
2803
|
+
uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp);
|
2804
|
+
*stack_slot = address;
|
2805
|
+
set_register(sp, new_sp);
|
2806
|
+
return new_sp;
|
2807
|
+
}
|
2808
|
+
|
2809
|
+
|
2810
|
+
uintptr_t Simulator::PopAddress() {
|
2811
|
+
int current_sp = get_register(sp);
|
2812
|
+
uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
|
2813
|
+
uintptr_t address = *stack_slot;
|
2814
|
+
set_register(sp, current_sp + sizeof(uintptr_t));
|
2815
|
+
return address;
|
2816
|
+
}
|
2817
|
+
|
2818
|
+
} } // namespace assembler::arm
|
2819
|
+
|
2820
|
+
#endif // __arm__
|
2821
|
+
|
2822
|
+
#endif // V8_TARGET_ARCH_ARM
|