rggen 0.12.0 → 0.13.0
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- checksums.yaml +4 -4
- data/README.md +13 -2
- data/lib/rggen.rb +0 -1
- data/lib/rggen/default.rb +7 -0
- data/lib/rggen/default_setup_file.rb +1 -2
- data/lib/rggen/version.rb +1 -3
- metadata +25 -81
- data/lib/rggen/built_in.rb +0 -57
- data/lib/rggen/built_in/bit_field/bit_assignment.rb +0 -114
- data/lib/rggen/built_in/bit_field/comment.rb +0 -18
- data/lib/rggen/built_in/bit_field/initial_value.rb +0 -75
- data/lib/rggen/built_in/bit_field/name.rb +0 -41
- data/lib/rggen/built_in/bit_field/reference.rb +0 -139
- data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +0 -89
- data/lib/rggen/built_in/bit_field/type.rb +0 -245
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +0 -59
- data/lib/rggen/built_in/bit_field/type/reserved.erb +0 -3
- data/lib/rggen/built_in/bit_field/type/reserved.rb +0 -16
- data/lib/rggen/built_in/bit_field/type/ro.erb +0 -6
- data/lib/rggen/built_in/bit_field/type/ro.rb +0 -31
- data/lib/rggen/built_in/bit_field/type/rof.erb +0 -6
- data/lib/rggen/built_in/bit_field/type/rof.rb +0 -17
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +0 -46
- data/lib/rggen/built_in/bit_field/type/rw_wo.erb +0 -9
- data/lib/rggen/built_in/bit_field/type/rw_wo.rb +0 -30
- data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +0 -16
- data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +0 -92
- data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +0 -9
- data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +0 -29
- data/lib/rggen/built_in/global/address_width.rb +0 -34
- data/lib/rggen/built_in/global/array_port_format.rb +0 -19
- data/lib/rggen/built_in/global/bus_width.rb +0 -35
- data/lib/rggen/built_in/global/fold_sv_interface_port.rb +0 -24
- data/lib/rggen/built_in/register/markdown.erb +0 -11
- data/lib/rggen/built_in/register/markdown.rb +0 -26
- data/lib/rggen/built_in/register/name.rb +0 -36
- data/lib/rggen/built_in/register/offset_address.rb +0 -106
- data/lib/rggen/built_in/register/size.rb +0 -95
- data/lib/rggen/built_in/register/sv_rtl_top.rb +0 -82
- data/lib/rggen/built_in/register/type.rb +0 -344
- data/lib/rggen/built_in/register/type/default_sv_ral.erb +0 -8
- data/lib/rggen/built_in/register/type/default_sv_rtl.erb +0 -15
- data/lib/rggen/built_in/register/type/external.erb +0 -11
- data/lib/rggen/built_in/register/type/external.rb +0 -128
- data/lib/rggen/built_in/register/type/indirect.rb +0 -327
- data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +0 -13
- data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +0 -17
- data/lib/rggen/built_in/register_block/byte_size.rb +0 -61
- data/lib/rggen/built_in/register_block/markdown.erb +0 -8
- data/lib/rggen/built_in/register_block/markdown.rb +0 -36
- data/lib/rggen/built_in/register_block/name.rb +0 -38
- data/lib/rggen/built_in/register_block/protocol.rb +0 -100
- data/lib/rggen/built_in/register_block/protocol/apb.erb +0 -10
- data/lib/rggen/built_in/register_block/protocol/apb.rb +0 -89
- data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +0 -11
- data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +0 -125
- data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/built_in/register_block/sv_ral_package.rb +0 -65
- data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +0 -9
- data/lib/rggen/built_in/register_block/sv_rtl_top.rb +0 -86
- data/lib/rggen/built_in/version.rb +0 -7
- data/lib/rggen/setup/default.rb +0 -30
- data/sample/block_0.md +0 -155
- data/sample/block_0.rb +0 -90
- data/sample/block_0.sv +0 -678
- data/sample/block_0.xlsx +0 -0
- data/sample/block_0.yml +0 -99
- data/sample/block_0_ral_pkg.sv +0 -184
- data/sample/block_1.md +0 -39
- data/sample/block_1.rb +0 -22
- data/sample/block_1.sv +0 -136
- data/sample/block_1.xlsx +0 -0
- data/sample/block_1.yml +0 -26
- data/sample/block_1_ral_pkg.sv +0 -68
- data/sample/config.json +0 -5
- data/sample/config.yml +0 -3
data/sample/block_0.xlsx
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data/sample/block_0.yml
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@@ -1,99 +0,0 @@
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register_blocks: [
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{
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name: block_0,
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byte_size: 256,
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registers: [
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6
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{
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7
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name: register_0,
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8
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offset_address: 0x00,
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9
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bit_fields: [
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10
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rw, initial_value: 0 },
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11
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{ name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: rw, initial_value: 0 },
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12
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{ name: bit_field_2, bit_assignment: { lsb: 8 , width: 1 }, type: rw, initial_value: 0 }
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13
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]
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14
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},
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15
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{
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16
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name: register_1,
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17
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offset_address: 0x04,
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18
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bit_fields: [
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19
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: ro },
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20
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{ name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: ro },
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21
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{ name: bit_field_2, bit_assignment: { lsb: 16, width: 8 }, type: rof, initial_value: 0xab },
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22
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{ name: bit_field_3, bit_assignment: { lsb: 24, width: 8 }, type: reserved }
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23
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]
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24
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},
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{
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name: register_2,
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offset_address: 0x04,
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bit_fields: [
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: wo, initial_value: 0 },
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30
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{ name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: w0trg },
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31
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{ name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: w1trg }
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]
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},
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{
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name: register_3,
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offset_address: 0x08,
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bit_fields: [
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rc, initial_value: 0 },
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39
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{ name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: rc, initial_value: 0, reference: register_0.bit_field_0 },
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40
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{ name: bit_field_2, bit_assignment: { lsb: 12, width: 4 }, type: ro, reference: register_3.bit_field_1 },
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{ name: bit_field_3, bit_assignment: { lsb: 16, width: 4 }, type: rs, initial_value: 0 }
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]
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},
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{
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name: register_4,
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offset_address: 0x0C,
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bit_fields: [
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rwc, initial_value: 0 },
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{ name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: rwc, initial_value: 0, reference: register_2.bit_field_1 },
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50
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{ name: bit_field_2, bit_assignment: { lsb: 8 , width: 4 }, type: rwe, initial_value: 0 },
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{ name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
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52
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{ name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: rwl, initial_value: 0 },
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53
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{ name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
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]
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},
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{
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name: register_5,
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offset_address: 0x10,
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bit_fields: [
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: w0c, initial_value: 0 },
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{ name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: w0c, initial_value: 0, reference: register_0.bit_field_0 },
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{ name: bit_field_2, bit_assignment: { lsb: 8 , width: 4 }, type: ro , reference: register_5.bit_field_1 },
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{ name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: w1c, initial_value: 0 },
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{ name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: w1c, initial_value: 0, reference: register_0.bit_field_0 },
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{ name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: ro , reference: register_5.bit_field_4 },
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{ name: bit_field_6, bit_assignment: { lsb: 24, width: 4 }, type: w0s, initial_value: 0 },
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{ name: bit_field_7, bit_assignment: { lsb: 28, width: 4 }, type: w1s, initial_value: 0 },
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]
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},
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{
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name: register_6,
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offset_address: 0x20,
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size: 4,
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bit_fields: [
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# bit assignments: [7:0] [23:16] [39:32] [55:48]
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 },
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# bit assignments: [15:8] [31:24] [47:40] [63:56]
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{ name: bit_field_1, bit_assignment: { lsb: 8 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 }
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]
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},
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{
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name: register_7,
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offset_address: 0x40,
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size: [2, 4],
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type: [indirect, register_0.bit_field_0, register_0.bit_field_1, [register_0.bit_field_2, 1]],
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86
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bit_fields: [
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{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 },
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88
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{ name: bit_field_1, bit_assignment: { lsb: 8 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 }
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89
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]
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},
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{
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name: register_8,
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offset_address: 0x80,
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size: 32,
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type: external
|
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}
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]
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}
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99
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]
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data/sample/block_0_ral_pkg.sv
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package block_0_ral_pkg;
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import uvm_pkg::*;
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import rggen_ral_pkg::*;
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`include "uvm_macros.svh"
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`include "rggen_ral_macros.svh"
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class register_0_reg_model extends rggen_ral_reg;
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rand rggen_ral_field bit_field_0;
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rand rggen_ral_field bit_field_1;
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rand rggen_ral_field bit_field_2;
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function new(string name);
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super.new(name, 32, 0);
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endfunction
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function void build();
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`rggen_ral_create_field_model(bit_field_0, 0, 4, RW, 0, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_1, 4, 4, RW, 0, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_2, 8, 1, RW, 0, 1'h0, 1)
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endfunction
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endclass
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class register_1_reg_model extends rggen_ral_reg;
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rand rggen_ral_field bit_field_0;
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rand rggen_ral_field bit_field_1;
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rand rggen_ral_field bit_field_2;
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rand rggen_ral_field bit_field_3;
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function new(string name);
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super.new(name, 32, 0);
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endfunction
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function void build();
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`rggen_ral_create_field_model(bit_field_0, 0, 4, RO, 1, 4'h0, 0)
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`rggen_ral_create_field_model(bit_field_1, 8, 4, RO, 1, 4'h0, 0)
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`rggen_ral_create_field_model(bit_field_2, 16, 8, RO, 0, 8'hab, 1)
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`rggen_ral_create_field_model(bit_field_3, 24, 8, RO, 0, 8'h00, 0)
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endfunction
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endclass
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class register_2_reg_model extends rggen_ral_reg;
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rand rggen_ral_field bit_field_0;
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rand rggen_ral_w0trg_field bit_field_1;
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rand rggen_ral_w1trg_field bit_field_2;
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function new(string name);
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super.new(name, 32, 0);
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endfunction
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function void build();
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`rggen_ral_create_field_model(bit_field_0, 0, 4, WO, 0, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_1, 8, 4, W0TRG, 0, 4'h0, 0)
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`rggen_ral_create_field_model(bit_field_2, 16, 4, W1TRG, 0, 4'h0, 0)
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endfunction
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endclass
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class register_3_reg_model extends rggen_ral_reg;
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rand rggen_ral_field bit_field_0;
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rand rggen_ral_field bit_field_1;
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rand rggen_ral_field bit_field_2;
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rand rggen_ral_field bit_field_3;
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function new(string name);
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super.new(name, 32, 0);
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endfunction
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function void build();
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`rggen_ral_create_field_model(bit_field_0, 0, 4, RC, 1, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_1, 8, 4, RC, 1, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_2, 12, 4, RO, 1, 4'h0, 0)
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`rggen_ral_create_field_model(bit_field_3, 16, 4, RS, 1, 4'h0, 1)
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endfunction
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endclass
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class register_4_reg_model extends rggen_ral_reg;
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rand rggen_ral_field bit_field_0;
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rand rggen_ral_field bit_field_1;
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rand rggen_ral_rwe_field #("", "") bit_field_2;
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rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_3;
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rand rggen_ral_rwl_field #("", "") bit_field_4;
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rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_5;
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function new(string name);
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super.new(name, 32, 0);
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endfunction
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function void build();
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`rggen_ral_create_field_model(bit_field_0, 0, 4, RW, 1, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_1, 4, 4, RW, 1, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_2, 8, 4, RWE, 1, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_3, 12, 4, RWE, 0, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_4, 16, 4, RWL, 1, 4'h0, 1)
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`rggen_ral_create_field_model(bit_field_5, 20, 4, RWL, 0, 4'h0, 1)
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endfunction
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endclass
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class register_5_reg_model extends rggen_ral_reg;
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rand rggen_ral_field bit_field_0;
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rand rggen_ral_field bit_field_1;
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rand rggen_ral_field bit_field_2;
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rand rggen_ral_field bit_field_3;
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rand rggen_ral_field bit_field_4;
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rand rggen_ral_field bit_field_5;
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rand rggen_ral_field bit_field_6;
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rand rggen_ral_field bit_field_7;
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function new(string name);
|
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super.new(name, 32, 0);
|
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endfunction
|
93
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function void build();
|
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`rggen_ral_create_field_model(bit_field_0, 0, 4, W0C, 1, 4'h0, 1)
|
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`rggen_ral_create_field_model(bit_field_1, 4, 4, W0C, 1, 4'h0, 1)
|
96
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`rggen_ral_create_field_model(bit_field_2, 8, 4, RO, 1, 4'h0, 0)
|
97
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`rggen_ral_create_field_model(bit_field_3, 12, 4, W1C, 1, 4'h0, 1)
|
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`rggen_ral_create_field_model(bit_field_4, 16, 4, W1C, 1, 4'h0, 1)
|
99
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`rggen_ral_create_field_model(bit_field_5, 20, 4, RO, 1, 4'h0, 0)
|
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`rggen_ral_create_field_model(bit_field_6, 24, 4, W0S, 1, 4'h0, 1)
|
101
|
-
`rggen_ral_create_field_model(bit_field_7, 28, 4, W1S, 1, 4'h0, 1)
|
102
|
-
endfunction
|
103
|
-
endclass
|
104
|
-
class register_6_reg_model extends rggen_ral_reg;
|
105
|
-
rand rggen_ral_field bit_field_0[4];
|
106
|
-
rand rggen_ral_field bit_field_1[4];
|
107
|
-
function new(string name);
|
108
|
-
super.new(name, 64, 0);
|
109
|
-
endfunction
|
110
|
-
function void build();
|
111
|
-
`rggen_ral_create_field_model(bit_field_0[0], 0, 8, RW, 0, 8'h00, 1)
|
112
|
-
`rggen_ral_create_field_model(bit_field_0[1], 16, 8, RW, 0, 8'h00, 1)
|
113
|
-
`rggen_ral_create_field_model(bit_field_0[2], 32, 8, RW, 0, 8'h00, 1)
|
114
|
-
`rggen_ral_create_field_model(bit_field_0[3], 48, 8, RW, 0, 8'h00, 1)
|
115
|
-
`rggen_ral_create_field_model(bit_field_1[0], 8, 8, RW, 0, 8'h00, 1)
|
116
|
-
`rggen_ral_create_field_model(bit_field_1[1], 24, 8, RW, 0, 8'h00, 1)
|
117
|
-
`rggen_ral_create_field_model(bit_field_1[2], 40, 8, RW, 0, 8'h00, 1)
|
118
|
-
`rggen_ral_create_field_model(bit_field_1[3], 56, 8, RW, 0, 8'h00, 1)
|
119
|
-
endfunction
|
120
|
-
endclass
|
121
|
-
class register_7_reg_model extends rggen_ral_indirect_reg;
|
122
|
-
rand rggen_ral_field bit_field_0[4];
|
123
|
-
rand rggen_ral_field bit_field_1[4];
|
124
|
-
function new(string name);
|
125
|
-
super.new(name, 64, 0);
|
126
|
-
endfunction
|
127
|
-
function void build();
|
128
|
-
`rggen_ral_create_field_model(bit_field_0[0], 0, 8, RW, 0, 8'h00, 1)
|
129
|
-
`rggen_ral_create_field_model(bit_field_0[1], 16, 8, RW, 0, 8'h00, 1)
|
130
|
-
`rggen_ral_create_field_model(bit_field_0[2], 32, 8, RW, 0, 8'h00, 1)
|
131
|
-
`rggen_ral_create_field_model(bit_field_0[3], 48, 8, RW, 0, 8'h00, 1)
|
132
|
-
`rggen_ral_create_field_model(bit_field_1[0], 8, 8, RW, 0, 8'h00, 1)
|
133
|
-
`rggen_ral_create_field_model(bit_field_1[1], 24, 8, RW, 0, 8'h00, 1)
|
134
|
-
`rggen_ral_create_field_model(bit_field_1[2], 40, 8, RW, 0, 8'h00, 1)
|
135
|
-
`rggen_ral_create_field_model(bit_field_1[3], 56, 8, RW, 0, 8'h00, 1)
|
136
|
-
endfunction
|
137
|
-
function void setup_index_fields();
|
138
|
-
setup_index_field("register_0", "bit_field_0", array_index[0]);
|
139
|
-
setup_index_field("register_0", "bit_field_1", array_index[1]);
|
140
|
-
setup_index_field("register_0", "bit_field_2", 1'h1);
|
141
|
-
endfunction
|
142
|
-
endclass
|
143
|
-
class block_0_block_model #(
|
144
|
-
type REGISTER_8 = rggen_ral_block,
|
145
|
-
bit INTEGRATE_REGISTER_8 = 1
|
146
|
-
) extends rggen_ral_block;
|
147
|
-
rand register_0_reg_model register_0;
|
148
|
-
rand register_1_reg_model register_1;
|
149
|
-
rand register_2_reg_model register_2;
|
150
|
-
rand register_3_reg_model register_3;
|
151
|
-
rand register_4_reg_model register_4;
|
152
|
-
rand register_5_reg_model register_5;
|
153
|
-
rand register_6_reg_model register_6[4];
|
154
|
-
rand register_7_reg_model register_7[2][4];
|
155
|
-
rand REGISTER_8 register_8;
|
156
|
-
function new(string name);
|
157
|
-
super.new(name);
|
158
|
-
endfunction
|
159
|
-
function void build();
|
160
|
-
`rggen_ral_create_reg_model(register_0, '{}, 8'h00, RW, 0, g_register_0.u_register)
|
161
|
-
`rggen_ral_create_reg_model(register_1, '{}, 8'h04, RO, 0, g_register_1.u_register)
|
162
|
-
`rggen_ral_create_reg_model(register_2, '{}, 8'h04, WO, 0, g_register_2.u_register)
|
163
|
-
`rggen_ral_create_reg_model(register_3, '{}, 8'h08, RO, 0, g_register_3.u_register)
|
164
|
-
`rggen_ral_create_reg_model(register_4, '{}, 8'h0c, RW, 0, g_register_4.u_register)
|
165
|
-
`rggen_ral_create_reg_model(register_5, '{}, 8'h10, RW, 0, g_register_5.u_register)
|
166
|
-
`rggen_ral_create_reg_model(register_6[0], '{0}, 8'h20, RW, 0, g_register_6.g[0].u_register)
|
167
|
-
`rggen_ral_create_reg_model(register_6[1], '{1}, 8'h28, RW, 0, g_register_6.g[1].u_register)
|
168
|
-
`rggen_ral_create_reg_model(register_6[2], '{2}, 8'h30, RW, 0, g_register_6.g[2].u_register)
|
169
|
-
`rggen_ral_create_reg_model(register_6[3], '{3}, 8'h38, RW, 0, g_register_6.g[3].u_register)
|
170
|
-
`rggen_ral_create_reg_model(register_7[0][0], '{0, 0}, 8'h40, RW, 1, g_register_7.g[0].g[0].u_register)
|
171
|
-
`rggen_ral_create_reg_model(register_7[0][1], '{0, 1}, 8'h40, RW, 1, g_register_7.g[0].g[1].u_register)
|
172
|
-
`rggen_ral_create_reg_model(register_7[0][2], '{0, 2}, 8'h40, RW, 1, g_register_7.g[0].g[2].u_register)
|
173
|
-
`rggen_ral_create_reg_model(register_7[0][3], '{0, 3}, 8'h40, RW, 1, g_register_7.g[0].g[3].u_register)
|
174
|
-
`rggen_ral_create_reg_model(register_7[1][0], '{1, 0}, 8'h40, RW, 1, g_register_7.g[1].g[0].u_register)
|
175
|
-
`rggen_ral_create_reg_model(register_7[1][1], '{1, 1}, 8'h40, RW, 1, g_register_7.g[1].g[1].u_register)
|
176
|
-
`rggen_ral_create_reg_model(register_7[1][2], '{1, 2}, 8'h40, RW, 1, g_register_7.g[1].g[2].u_register)
|
177
|
-
`rggen_ral_create_reg_model(register_7[1][3], '{1, 3}, 8'h40, RW, 1, g_register_7.g[1].g[3].u_register)
|
178
|
-
`rggen_ral_create_block_model(register_8, 8'h80, this, INTEGRATE_REGISTER_8)
|
179
|
-
endfunction
|
180
|
-
function uvm_reg_map create_default_map();
|
181
|
-
return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
|
182
|
-
endfunction
|
183
|
-
endclass
|
184
|
-
endpackage
|
data/sample/block_1.md
DELETED
@@ -1,39 +0,0 @@
|
|
1
|
-
## block_1
|
2
|
-
|
3
|
-
* name
|
4
|
-
* block_1
|
5
|
-
* byte_size
|
6
|
-
* 128
|
7
|
-
|
8
|
-
|name|offset_address|
|
9
|
-
|:--|:--|
|
10
|
-
|[register_0](#block_1-register_0)|0x00 - 0x3f|
|
11
|
-
|[register_1](#block_1-register_1)|0x40 - 0x7f|
|
12
|
-
|
13
|
-
### <div id="block_1-register_0"></div>register_0
|
14
|
-
|
15
|
-
* name
|
16
|
-
* register_0
|
17
|
-
* offset_address
|
18
|
-
* 0x00 - 0x3f
|
19
|
-
* array_size
|
20
|
-
* [2, 4]
|
21
|
-
|
22
|
-
|name|bit_assignments|type|initial_value|comment|
|
23
|
-
|:--|:--|:--|:--|:--|
|
24
|
-
|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
|
25
|
-
|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|ro|||
|
26
|
-
|
27
|
-
### <div id="block_1-register_1"></div>register_1
|
28
|
-
|
29
|
-
* name
|
30
|
-
* register_1
|
31
|
-
* offset_address
|
32
|
-
* 0x40 - 0x7f
|
33
|
-
* array_size
|
34
|
-
* [2, 4]
|
35
|
-
|
36
|
-
|name|bit_assignments|type|initial_value|comment|
|
37
|
-
|:--|:--|:--|:--|:--|
|
38
|
-
|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|ro|||
|
39
|
-
|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
|
data/sample/block_1.rb
DELETED
@@ -1,22 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
register_block {
|
4
|
-
name 'block_1'
|
5
|
-
byte_size 128
|
6
|
-
|
7
|
-
register {
|
8
|
-
name 'register_0'
|
9
|
-
offset_address 0x00
|
10
|
-
size [2, 4]
|
11
|
-
bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
|
12
|
-
bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :ro; reference 'register_1.bit_field_1' }
|
13
|
-
}
|
14
|
-
|
15
|
-
register {
|
16
|
-
name 'register_1'
|
17
|
-
offset_address 0x40
|
18
|
-
size [2, 4]
|
19
|
-
bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :ro; reference 'register_0.bit_field_0' }
|
20
|
-
bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
|
21
|
-
}
|
22
|
-
}
|
data/sample/block_1.sv
DELETED
@@ -1,136 +0,0 @@
|
|
1
|
-
`ifndef rggen_connect_bit_field_if
|
2
|
-
`define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
|
3
|
-
assign FIF.valid = RIF.valid; \
|
4
|
-
assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; \
|
5
|
-
assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; \
|
6
|
-
assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; \
|
7
|
-
assign RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
|
8
|
-
assign RIF.value[LSB+:WIDTH] = FIF.value;
|
9
|
-
`endif
|
10
|
-
module block_1
|
11
|
-
import rggen_rtl_pkg::*;
|
12
|
-
(
|
13
|
-
input logic i_clk,
|
14
|
-
input logic i_rst_n,
|
15
|
-
rggen_apb_if.slave apb_if,
|
16
|
-
output logic [1:0][3:0][3:0][7:0] o_register_0_bit_field_0,
|
17
|
-
output logic [1:0][3:0][3:0][7:0] o_register_1_bit_field_1
|
18
|
-
);
|
19
|
-
rggen_register_if #(7, 32, 64) register_if[16]();
|
20
|
-
rggen_apb_adapter #(
|
21
|
-
.ADDRESS_WIDTH (7),
|
22
|
-
.BUS_WIDTH (32),
|
23
|
-
.REGISTERS (16)
|
24
|
-
) u_adapter (
|
25
|
-
.i_clk (i_clk),
|
26
|
-
.i_rst_n (i_rst_n),
|
27
|
-
.apb_if (apb_if),
|
28
|
-
.register_if (register_if)
|
29
|
-
);
|
30
|
-
generate if (1) begin : g_register_0
|
31
|
-
genvar i;
|
32
|
-
genvar j;
|
33
|
-
for (i = 0;i < 2;++i) begin : g
|
34
|
-
for (j = 0;j < 4;++j) begin : g
|
35
|
-
rggen_bit_field_if #(64) bit_field_if();
|
36
|
-
rggen_default_register #(
|
37
|
-
.READABLE (1),
|
38
|
-
.WRITABLE (1),
|
39
|
-
.ADDRESS_WIDTH (7),
|
40
|
-
.OFFSET_ADDRESS (7'h00),
|
41
|
-
.BUS_WIDTH (32),
|
42
|
-
.DATA_WIDTH (64),
|
43
|
-
.VALID_BITS (64'hffffffffffffffff),
|
44
|
-
.REGISTER_INDEX (4*i+j)
|
45
|
-
) u_register (
|
46
|
-
.i_clk (i_clk),
|
47
|
-
.i_rst_n (i_rst_n),
|
48
|
-
.register_if (register_if[0+4*i+j]),
|
49
|
-
.bit_field_if (bit_field_if)
|
50
|
-
);
|
51
|
-
if (1) begin : g_bit_field_0
|
52
|
-
genvar k;
|
53
|
-
for (k = 0;k < 4;++k) begin : g
|
54
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
55
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8)
|
56
|
-
rggen_bit_field_rw #(
|
57
|
-
.WIDTH (8),
|
58
|
-
.INITIAL_VALUE (8'h00)
|
59
|
-
) u_bit_field (
|
60
|
-
.i_clk (i_clk),
|
61
|
-
.i_rst_n (i_rst_n),
|
62
|
-
.bit_field_if (bit_field_sub_if),
|
63
|
-
.o_value (o_register_0_bit_field_0[i][j][k])
|
64
|
-
);
|
65
|
-
end
|
66
|
-
end
|
67
|
-
if (1) begin : g_bit_field_1
|
68
|
-
genvar k;
|
69
|
-
for (k = 0;k < 4;++k) begin : g
|
70
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
71
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8)
|
72
|
-
rggen_bit_field_ro #(
|
73
|
-
.WIDTH (8)
|
74
|
-
) u_bit_field (
|
75
|
-
.bit_field_if (bit_field_sub_if),
|
76
|
-
.i_value (register_if[8+4*i+j].value[8+16*k+:8])
|
77
|
-
);
|
78
|
-
end
|
79
|
-
end
|
80
|
-
end
|
81
|
-
end
|
82
|
-
end endgenerate
|
83
|
-
generate if (1) begin : g_register_1
|
84
|
-
genvar i;
|
85
|
-
genvar j;
|
86
|
-
for (i = 0;i < 2;++i) begin : g
|
87
|
-
for (j = 0;j < 4;++j) begin : g
|
88
|
-
rggen_bit_field_if #(64) bit_field_if();
|
89
|
-
rggen_default_register #(
|
90
|
-
.READABLE (1),
|
91
|
-
.WRITABLE (1),
|
92
|
-
.ADDRESS_WIDTH (7),
|
93
|
-
.OFFSET_ADDRESS (7'h40),
|
94
|
-
.BUS_WIDTH (32),
|
95
|
-
.DATA_WIDTH (64),
|
96
|
-
.VALID_BITS (64'hffffffffffffffff),
|
97
|
-
.REGISTER_INDEX (4*i+j)
|
98
|
-
) u_register (
|
99
|
-
.i_clk (i_clk),
|
100
|
-
.i_rst_n (i_rst_n),
|
101
|
-
.register_if (register_if[8+4*i+j]),
|
102
|
-
.bit_field_if (bit_field_if)
|
103
|
-
);
|
104
|
-
if (1) begin : g_bit_field_0
|
105
|
-
genvar k;
|
106
|
-
for (k = 0;k < 4;++k) begin : g
|
107
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
108
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8)
|
109
|
-
rggen_bit_field_ro #(
|
110
|
-
.WIDTH (8)
|
111
|
-
) u_bit_field (
|
112
|
-
.bit_field_if (bit_field_sub_if),
|
113
|
-
.i_value (register_if[0+4*i+j].value[0+16*k+:8])
|
114
|
-
);
|
115
|
-
end
|
116
|
-
end
|
117
|
-
if (1) begin : g_bit_field_1
|
118
|
-
genvar k;
|
119
|
-
for (k = 0;k < 4;++k) begin : g
|
120
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
121
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8)
|
122
|
-
rggen_bit_field_rw #(
|
123
|
-
.WIDTH (8),
|
124
|
-
.INITIAL_VALUE (8'h00)
|
125
|
-
) u_bit_field (
|
126
|
-
.i_clk (i_clk),
|
127
|
-
.i_rst_n (i_rst_n),
|
128
|
-
.bit_field_if (bit_field_sub_if),
|
129
|
-
.o_value (o_register_1_bit_field_1[i][j][k])
|
130
|
-
);
|
131
|
-
end
|
132
|
-
end
|
133
|
-
end
|
134
|
-
end
|
135
|
-
end endgenerate
|
136
|
-
endmodule
|