rggen 0.12.0 → 0.13.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (78) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +13 -2
  3. data/lib/rggen.rb +0 -1
  4. data/lib/rggen/default.rb +7 -0
  5. data/lib/rggen/default_setup_file.rb +1 -2
  6. data/lib/rggen/version.rb +1 -3
  7. metadata +25 -81
  8. data/lib/rggen/built_in.rb +0 -57
  9. data/lib/rggen/built_in/bit_field/bit_assignment.rb +0 -114
  10. data/lib/rggen/built_in/bit_field/comment.rb +0 -18
  11. data/lib/rggen/built_in/bit_field/initial_value.rb +0 -75
  12. data/lib/rggen/built_in/bit_field/name.rb +0 -41
  13. data/lib/rggen/built_in/bit_field/reference.rb +0 -139
  14. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +0 -89
  15. data/lib/rggen/built_in/bit_field/type.rb +0 -245
  16. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +0 -15
  17. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +0 -59
  18. data/lib/rggen/built_in/bit_field/type/reserved.erb +0 -3
  19. data/lib/rggen/built_in/bit_field/type/reserved.rb +0 -16
  20. data/lib/rggen/built_in/bit_field/type/ro.erb +0 -6
  21. data/lib/rggen/built_in/bit_field/type/ro.rb +0 -31
  22. data/lib/rggen/built_in/bit_field/type/rof.erb +0 -6
  23. data/lib/rggen/built_in/bit_field/type/rof.rb +0 -17
  24. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +0 -13
  25. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +0 -46
  26. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +0 -9
  27. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +0 -30
  28. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +0 -16
  29. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +0 -92
  30. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +0 -9
  31. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +0 -29
  32. data/lib/rggen/built_in/global/address_width.rb +0 -34
  33. data/lib/rggen/built_in/global/array_port_format.rb +0 -19
  34. data/lib/rggen/built_in/global/bus_width.rb +0 -35
  35. data/lib/rggen/built_in/global/fold_sv_interface_port.rb +0 -24
  36. data/lib/rggen/built_in/register/markdown.erb +0 -11
  37. data/lib/rggen/built_in/register/markdown.rb +0 -26
  38. data/lib/rggen/built_in/register/name.rb +0 -36
  39. data/lib/rggen/built_in/register/offset_address.rb +0 -106
  40. data/lib/rggen/built_in/register/size.rb +0 -95
  41. data/lib/rggen/built_in/register/sv_rtl_top.rb +0 -82
  42. data/lib/rggen/built_in/register/type.rb +0 -344
  43. data/lib/rggen/built_in/register/type/default_sv_ral.erb +0 -8
  44. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +0 -15
  45. data/lib/rggen/built_in/register/type/external.erb +0 -11
  46. data/lib/rggen/built_in/register/type/external.rb +0 -128
  47. data/lib/rggen/built_in/register/type/indirect.rb +0 -327
  48. data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +0 -13
  49. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +0 -17
  50. data/lib/rggen/built_in/register_block/byte_size.rb +0 -61
  51. data/lib/rggen/built_in/register_block/markdown.erb +0 -8
  52. data/lib/rggen/built_in/register_block/markdown.rb +0 -36
  53. data/lib/rggen/built_in/register_block/name.rb +0 -38
  54. data/lib/rggen/built_in/register_block/protocol.rb +0 -100
  55. data/lib/rggen/built_in/register_block/protocol/apb.erb +0 -10
  56. data/lib/rggen/built_in/register_block/protocol/apb.rb +0 -89
  57. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +0 -11
  58. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +0 -125
  59. data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +0 -11
  60. data/lib/rggen/built_in/register_block/sv_ral_package.rb +0 -65
  61. data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +0 -9
  62. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +0 -86
  63. data/lib/rggen/built_in/version.rb +0 -7
  64. data/lib/rggen/setup/default.rb +0 -30
  65. data/sample/block_0.md +0 -155
  66. data/sample/block_0.rb +0 -90
  67. data/sample/block_0.sv +0 -678
  68. data/sample/block_0.xlsx +0 -0
  69. data/sample/block_0.yml +0 -99
  70. data/sample/block_0_ral_pkg.sv +0 -184
  71. data/sample/block_1.md +0 -39
  72. data/sample/block_1.rb +0 -22
  73. data/sample/block_1.sv +0 -136
  74. data/sample/block_1.xlsx +0 -0
  75. data/sample/block_1.yml +0 -26
  76. data/sample/block_1_ral_pkg.sv +0 -68
  77. data/sample/config.json +0 -5
  78. data/sample/config.yml +0 -3
data/sample/block_1.xlsx DELETED
Binary file
data/sample/block_1.yml DELETED
@@ -1,26 +0,0 @@
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- register_blocks: [
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- {
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- name: block_1,
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- byte_size: 128,
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- registers: [
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- {
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- name: 'register_0',
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- offset_address: 0x00,
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- size: [2, 4],
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- bit_fields: [
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- { name: bit_field_0, bit_assignment: { lsb: 0, width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0x00 },
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- { name: bit_field_1, bit_assignment: { lsb: 8, width: 8, sequence_size: 4, step: 16 }, type: ro, reference: register_1.bit_field_1 }
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- ]
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- },
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- {
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- name: 'register_1',
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- offset_address: 0x40,
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- size: [2, 4],
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- bit_fields: [
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- { name: bit_field_0, bit_assignment: { lsb: 0, width: 8, sequence_size: 4, step: 16 }, type: ro, reference: register_0.bit_field_0 },
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- { name: bit_field_1, bit_assignment: { lsb: 8, width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0x00 }
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- ]
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- }
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- ]
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- }
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- ]
data/sample/block_1_ral_pkg.sv DELETED
@@ -1,68 +0,0 @@
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- package block_1_ral_pkg;
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- import uvm_pkg::*;
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- import rggen_ral_pkg::*;
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- `include "uvm_macros.svh"
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- `include "rggen_ral_macros.svh"
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- class register_0_reg_model extends rggen_ral_reg;
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- rand rggen_ral_field bit_field_0[4];
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- rand rggen_ral_field bit_field_1[4];
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- function new(string name);
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- super.new(name, 64, 0);
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- endfunction
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- function void build();
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- `rggen_ral_create_field_model(bit_field_0[0], 0, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_0[1], 16, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_0[2], 32, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_0[3], 48, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_1[0], 8, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_1[1], 24, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_1[2], 40, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_1[3], 56, 8, RO, 1, 8'h00, 0)
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- endfunction
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- endclass
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- class register_1_reg_model extends rggen_ral_reg;
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- rand rggen_ral_field bit_field_0[4];
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- rand rggen_ral_field bit_field_1[4];
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- function new(string name);
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- super.new(name, 64, 0);
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- endfunction
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- function void build();
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- `rggen_ral_create_field_model(bit_field_0[0], 0, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_0[1], 16, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_0[2], 32, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_0[3], 48, 8, RO, 1, 8'h00, 0)
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- `rggen_ral_create_field_model(bit_field_1[0], 8, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_1[1], 24, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_1[2], 40, 8, RW, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_1[3], 56, 8, RW, 0, 8'h00, 1)
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- endfunction
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- endclass
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- class block_1_block_model extends rggen_ral_block;
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- rand register_0_reg_model register_0[2][4];
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- rand register_1_reg_model register_1[2][4];
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- function new(string name);
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- super.new(name);
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- endfunction
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- function void build();
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- `rggen_ral_create_reg_model(register_0[0][0], '{0, 0}, 7'h00, RW, 0, g_register_0.g[0].g[0].u_register)
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- `rggen_ral_create_reg_model(register_0[0][1], '{0, 1}, 7'h08, RW, 0, g_register_0.g[0].g[1].u_register)
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- `rggen_ral_create_reg_model(register_0[0][2], '{0, 2}, 7'h10, RW, 0, g_register_0.g[0].g[2].u_register)
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- `rggen_ral_create_reg_model(register_0[0][3], '{0, 3}, 7'h18, RW, 0, g_register_0.g[0].g[3].u_register)
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- `rggen_ral_create_reg_model(register_0[1][0], '{1, 0}, 7'h20, RW, 0, g_register_0.g[1].g[0].u_register)
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- `rggen_ral_create_reg_model(register_0[1][1], '{1, 1}, 7'h28, RW, 0, g_register_0.g[1].g[1].u_register)
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- `rggen_ral_create_reg_model(register_0[1][2], '{1, 2}, 7'h30, RW, 0, g_register_0.g[1].g[2].u_register)
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- `rggen_ral_create_reg_model(register_0[1][3], '{1, 3}, 7'h38, RW, 0, g_register_0.g[1].g[3].u_register)
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- `rggen_ral_create_reg_model(register_1[0][0], '{0, 0}, 7'h40, RW, 0, g_register_1.g[0].g[0].u_register)
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- `rggen_ral_create_reg_model(register_1[0][1], '{0, 1}, 7'h48, RW, 0, g_register_1.g[0].g[1].u_register)
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- `rggen_ral_create_reg_model(register_1[0][2], '{0, 2}, 7'h50, RW, 0, g_register_1.g[0].g[2].u_register)
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- `rggen_ral_create_reg_model(register_1[0][3], '{0, 3}, 7'h58, RW, 0, g_register_1.g[0].g[3].u_register)
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- `rggen_ral_create_reg_model(register_1[1][0], '{1, 0}, 7'h60, RW, 0, g_register_1.g[1].g[0].u_register)
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- `rggen_ral_create_reg_model(register_1[1][1], '{1, 1}, 7'h68, RW, 0, g_register_1.g[1].g[1].u_register)
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- `rggen_ral_create_reg_model(register_1[1][2], '{1, 2}, 7'h70, RW, 0, g_register_1.g[1].g[2].u_register)
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- `rggen_ral_create_reg_model(register_1[1][3], '{1, 3}, 7'h78, RW, 0, g_register_1.g[1].g[3].u_register)
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- endfunction
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- function uvm_reg_map create_default_map();
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- return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
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- endfunction
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- endclass
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- endpackage
data/sample/config.json DELETED
@@ -1,5 +0,0 @@
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- {
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- "bus_width": 32,
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- "address_width": 16,
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- "protocol": "apb"
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- }
data/sample/config.yml DELETED
@@ -1,3 +0,0 @@
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- bus_width: 32
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- address_width: 16
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- protocol: apb