rggen 0.12.0 → 0.13.0

data/lib/rggen/built_in/register_block/sv_ral_block_model.erb

@@ -1,11 +0,0 @@
-function new(string name);
-  super.new(name);
-endfunction
-function void build();
-<% reg_model_constructors.each do |constructor| %>
-  <%= constructor %>
-<% end %>
-endfunction
-function uvm_reg_map create_default_map();
-  return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
-endfunction

data/lib/rggen/built_in/register_block/sv_ral_package.rb

@@ -1,65 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:register_block, :sv_ral_package) do
-  sv_ral do
-    write_file '<%= package_name %>.sv' do |file|
-      file.body do
-        package_definition(package_name) do |package|
-          package.package_imports packages
-          package.include_files include_files
-          package.body do |code|
-            register_block.generate_code(:ral_package, :bottom_up, code)
-          end
-        end
-      end
-    end
-
-    main_code :ral_package do
-      class_definition(model_name) do |sv_class|
-        sv_class.base 'rggen_ral_block'
-        sv_class.parameters parameters
-        sv_class.variables variables
-        sv_class.body do
-          process_template(File.join(__dir__, 'sv_ral_block_model.erb'))
-        end
-      end
-    end
-
-    private
-
-    def package_name
-      "#{register_block.name}_ral_pkg"
-    end
-
-    def packages
-      [
-        'uvm_pkg', 'rggen_ral_pkg',
-        *register_block.package_imports(:ral_package)
-      ]
-    end
-
-    def include_files
-      ['uvm_macros.svh', 'rggen_ral_macros.svh']
-    end
-
-    def model_name
-      "#{register_block.name}_block_model"
-    end
-
-    def parameters
-      register_block.declarations(:register_block, :parameter)
-    end
-
-    def variables
-      register_block.declarations(:register_block, :variable)
-    end
-
-    def reg_model_constructors
-      register_block.registers.flat_map(&:constructors)
-    end
-
-    def byte_width
-      configuration.byte_width
-    end
-  end
-end

data/lib/rggen/built_in/register_block/sv_rtl_macros.erb

@@ -1,9 +0,0 @@
-`ifndef rggen_connect_bit_field_if
-  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
-  assign  FIF.valid                 = RIF.valid; \
-  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
-  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
-  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
-  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
-  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
-`endif

data/lib/rggen/built_in/register_block/sv_rtl_top.rb

@@ -1,86 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
-  sv_rtl do
-    export :total_registers
-
-    build do
-      input :register_block, :clock, {
-        name: 'i_clk', data_type: :logic, width: 1
-      }
-      input :register_block, :reset, {
-        name: 'i_rst_n', data_type: :logic, width: 1
-      }
-      interface :register_block, :register_if, {
-        name: 'register_if', interface_type: 'rggen_register_if',
-        parameter_values: [address_width, bus_width, value_width],
-        array_size: [total_registers],
-        variables: ['value']
-      }
-    end
-
-    write_file '<%= register_block.name %>.sv' do |file|
-      file.body(&method(:body_code))
-    end
-
-    def total_registers
-      register_block
-        .registers
-        .map(&:count)
-        .inject(:+)
-    end
-
-    private
-
-    def address_width
-      register_block.local_address_width
-    end
-
-    def bus_width
-      configuration.bus_width
-    end
-
-    def value_width
-      register_block.registers.map(&:width).max
-    end
-
-    def body_code(code)
-      macro_definition(code)
-      sv_module_definition(code)
-    end
-
-    def macro_definition(code)
-      code << process_template(File.join(__dir__, 'sv_rtl_macros.erb'))
-    end
-
-    def sv_module_definition(code)
-      code << module_definition(register_block.name) do |sv_module|
-        sv_module.package_imports packages
-        sv_module.parameters parameters
-        sv_module.ports ports
-        sv_module.variables variables
-        sv_module.body(&method(:sv_module_body))
-      end
-    end
-
-    def packages
-      ['rggen_rtl_pkg', *register_block.package_imports(:register_block)]
-    end
-
-    def parameters
-      register_block.declarations(:register_block, :parameter)
-    end
-
-    def ports
-      register_block.declarations(:register_block, :port)
-    end
-
-    def variables
-      register_block.declarations(:register_block, :variable)
-    end
-
-    def sv_module_body(code)
-      register_block.generate_code(:register_block, :top_down, code)
-    end
-  end
-end

data/lib/rggen/built_in/version.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module BuiltIn
-    VERSION = '0.12.0'
-  end
-end

data/lib/rggen/setup/default.rb

@@ -1,30 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/built_in'
-require 'rggen/spreadsheet_loader'
-
-RgGen.enable :global, [
-  :bus_width, :address_width, :array_port_format, :fold_sv_interface_port
-]
-
-RgGen.enable :register_block, [:name, :byte_size]
-RgGen.enable :register, [:name, :offset_address, :size, :type]
-RgGen.enable :register, :type, [:external, :indirect]
-RgGen.enable :bit_field, [
-  :name, :bit_assignment, :type, :initial_value, :reference, :comment
-]
-RgGen.enable :bit_field, :type, [
-  :rc, :reserved, :ro, :rof, :rs,
-  :rw, :rwc, :rwe, :rwl, :w0c, :w1c, :w0s, :w1s,
-  :w0trg, :w1trg, :wo
-]
-
-RgGen.enable :register_block, [:sv_rtl_top, :protocol]
-RgGen.enable :register_block, :protocol, [:apb, :axi4lite]
-RgGen.enable :register, [:sv_rtl_top]
-RgGen.enable :bit_field, [:sv_rtl_top]
-
-RgGen.enable :register_block, [:sv_ral_package]
-
-RgGen.enable :register_block, [:markdown]
-RgGen.enable :register, [:markdown]

data/sample/block_0.md

@@ -1,155 +0,0 @@
-## block_0
-
-* name
-    * block_0
-* byte_size
-    * 256
-
-|name|offset_address|
-|:--|:--|
-|[register_0](#block_0-register_0)|0x00 - 0x03|
-|[register_1](#block_0-register_1)|0x04 - 0x07|
-|[register_2](#block_0-register_2)|0x04 - 0x07|
-|[register_3](#block_0-register_3)|0x08 - 0x0b|
-|[register_4](#block_0-register_4)|0x0c - 0x0f|
-|[register_5](#block_0-register_5)|0x10 - 0x13|
-|[register_6](#block_0-register_6)|0x20 - 0x3f|
-|[register_7](#block_0-register_7)|0x40 - 0x47|
-|[register_8](#block_0-register_8)|0x80 - 0xff|
-
-### <div id="block_0-register_0"></div>register_0
-
-* name
-    * register_0
-* offset_address
-    * 0x00 - 0x03
-* array_size
-    * NA
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[3:0]|rw|0x0||
-|bit_field_1|[7:4]|rw|0x0||
-|bit_field_2|[8]|rw|0x0||
-
-### <div id="block_0-register_1"></div>register_1
-
-* name
-    * register_1
-* offset_address
-    * 0x04 - 0x07
-* array_size
-    * NA
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[3:0]|ro|||
-|bit_field_1|[11:8]|ro|||
-|bit_field_2|[23:16]|rof|0xab||
-|bit_field_3|[31:24]|reserved|||
-
-### <div id="block_0-register_2"></div>register_2
-
-* name
-    * register_2
-* offset_address
-    * 0x04 - 0x07
-* array_size
-    * NA
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[3:0]|wo|0x0||
-|bit_field_1|[11:8]|w0trg|||
-|bit_field_2|[19:16]|w1trg|||
-
-### <div id="block_0-register_3"></div>register_3
-
-* name
-    * register_3
-* offset_address
-    * 0x08 - 0x0b
-* array_size
-    * NA
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[3:0]|rc|0x0||
-|bit_field_1|[11:8]|rc|0x0||
-|bit_field_2|[15:12]|ro|||
-|bit_field_3|[19:16]|rs|0x0||
-
-### <div id="block_0-register_4"></div>register_4
-
-* name
-    * register_4
-* offset_address
-    * 0x0c - 0x0f
-* array_size
-    * NA
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[3:0]|rwc|0x0||
-|bit_field_1|[7:4]|rwc|0x0||
-|bit_field_2|[11:8]|rwe|0x0||
-|bit_field_3|[15:12]|rwe|0x0||
-|bit_field_4|[19:16]|rwl|0x0||
-|bit_field_5|[23:20]|rwl|0x0||
-
-### <div id="block_0-register_5"></div>register_5
-
-* name
-    * register_5
-* offset_address
-    * 0x10 - 0x13
-* array_size
-    * NA
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[3:0]|w0c|0x0||
-|bit_field_1|[7:4]|w0c|0x0||
-|bit_field_2|[11:8]|ro|||
-|bit_field_3|[15:12]|w1c|0x0||
-|bit_field_4|[19:16]|w1c|0x0||
-|bit_field_5|[23:20]|ro|||
-|bit_field_6|[27:24]|w0s|0x0||
-|bit_field_7|[31:28]|w1s|0x0||
-
-### <div id="block_0-register_6"></div>register_6
-
-* name
-    * register_6
-* offset_address
-    * 0x20 - 0x3f
-* array_size
-    * [4]
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
-|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
-
-### <div id="block_0-register_7"></div>register_7
-
-* name
-    * register_7
-* offset_address
-    * 0x40 - 0x47
-* array_size
-    * [2, 4]
-
-|name|bit_assignments|type|initial_value|comment|
-|:--|:--|:--|:--|:--|
-|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
-|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
-
-### <div id="block_0-register_8"></div>register_8
-
-* name
-    * register_8
-* offset_address
-    * 0x80 - 0xff
-* array_size
-    * NA

data/sample/block_0.rb

@@ -1,90 +0,0 @@
-# frozen_string_literal: true
-
-register_block {
-  name 'block_0'
-  byte_size 256
-
-  register {
-    name 'register_0'
-    offset_address 0x00
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rw; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :rw; initial_value 0 }
-    bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 1; type :rw; initial_value 0 }
-  }
-
-  register {
-    name 'register_1'
-    offset_address 0x04
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :ro }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :ro }
-    bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 8; type :rof; initial_value 0xab }
-    bit_field { name 'bit_field_3'; bit_assignment lsb: 24, width: 8; type :reserved }
-  }
-
-  register {
-    name 'register_2'
-    offset_address 0x04
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :wo; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :w0trg }
-    bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4; type :w1trg }
-  }
-
-  register {
-    name 'register_3'
-    offset_address 0x08
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rc; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :rc; initial_value 0; reference 'register_0.bit_field_0' }
-    bit_field { name 'bit_field_2'; bit_assignment lsb: 12, width: 4; type :ro;                  reference 'register_3.bit_field_1' }
-    bit_field { name 'bit_field_3'; bit_assignment lsb: 16, width: 4; type :rs; initial_value 0 }
-  }
-
-  register {
-    name 'register_4'
-    offset_address 0x0C
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rwc; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :rwc; initial_value 0; reference 'register_2.bit_field_1' }
-    bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 4; type :rwe; initial_value 0 }
-    bit_field { name 'bit_field_3'; bit_assignment lsb: 12, width: 4; type :rwe; initial_value 0; reference 'register_0.bit_field_2' }
-    bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4; type :rwl; initial_value 0 }
-    bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4; type :rwl; initial_value 0; reference 'register_0.bit_field_2' }
-  }
-
-  register {
-    name 'register_5'
-    offset_address 0x10
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :w0c; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :w0c; initial_value 0; reference 'register_0.bit_field_0' }
-    bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 4; type :ro ;                  reference 'register_5.bit_field_1' }
-    bit_field { name 'bit_field_3'; bit_assignment lsb: 12, width: 4; type :w1c; initial_value 0 }
-    bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4; type :w1c; initial_value 0; reference 'register_0.bit_field_0' }
-    bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4; type :ro ;                  reference 'register_5.bit_field_4' }
-    bit_field { name 'bit_field_6'; bit_assignment lsb: 24, width: 4; type :w0s; initial_value 0 }
-    bit_field { name 'bit_field_7'; bit_assignment lsb: 28, width: 4; type :w1s; initial_value 0 }
-  }
-
-  register {
-    name 'register_6'
-    offset_address 0x20
-    size 4
-    # bit assignments: [7:0] [23:16] [39:32] [55:48]
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
-    # bit assignments: [15:8] [31:24] [47:40] [63:56]
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
-  }
-
-  register {
-    name 'register_7'
-    offset_address 0x40
-    size [2, 4]
-    type [:indirect, 'register_0.bit_field_0', 'register_0.bit_field_1', ['register_0.bit_field_2', 1]]
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
-  }
-
-  register {
-    name 'register_8'
-    offset_address 0x80
-    size 32
-    type :external
-  }
-}