rggen 0.12.0 → 0.13.0

data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb

@@ -1,15 +0,0 @@
-<%= module_name %> #(
-<% if [:w0c, :w1c].include?(bit_field.type) %>
-  .CLEAR_VALUE    (<%= clear_value %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk            (<%= register_block.clock %>),
-  .i_rst_n          (<%= register_block.reset%>),
-  .bit_field_if     (<%= bit_field_if %>),
-  .i_set            (<%= set[loop_variables] %>),
-  .i_mask           (<%= mask %>),
-  .o_value          (<%= value_out[loop_variables] %>),
-  .o_value_unmasked (<%= value_out_unmasked %>)
-);

data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb

@@ -1,59 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rc) do
-  register_map do
-    read_only
-    reference use: true
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c]) do
-  register_map do
-    read_write
-    reference use: true
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
-  sv_rtl do
-    build do
-      input :register_block, :set, {
-        name: "i_#{full_name}_set", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-      output :register_block, :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-      if bit_field.reference?
-        output :register_block, :value_unmasked, {
-          name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def module_name
-      if bit_field.type == :rc
-        'rggen_bit_field_rc'
-      else
-        'rggen_bit_field_w01c'
-      end
-    end
-
-    def clear_value
-      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
-    end
-
-    def value_out_unmasked
-      (bit_field.reference? || nil) &&
-        value_unmasked[loop_variables]
-    end
-  end
-end

data/lib/rggen/built_in/bit_field/type/reserved.erb

@@ -1,3 +0,0 @@
-rggen_bit_field_reserved u_bit_field (
-  .bit_field_if (<%= bit_field_if %>)
-);

data/lib/rggen/built_in/bit_field/type/reserved.rb

@@ -1,16 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
-  register_map do
-    reserved
-    non_volatile
-  end
-
-  sv_rtl do
-    main_code :bit_field, from_template: true
-  end
-
-  sv_ral do
-    access 'RO'
-  end
-end

data/lib/rggen/built_in/bit_field/type/ro.erb

@@ -1,6 +0,0 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
-) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= reference_or_value_in %>)
-);

data/lib/rggen/built_in/bit_field/type/ro.rb

@@ -1,31 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :ro) do
-  register_map do
-    read_only
-    reference use: true
-  end
-
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :register_block, :value_in, {
-          name: "i_#{full_name}", data_type: :logic, width: width,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def reference_or_value_in
-      if bit_field.reference?
-        reference_bit_field
-      else
-        value_in[loop_variables]
-      end
-    end
-  end
-end

data/lib/rggen/built_in/bit_field/type/rof.erb

@@ -1,6 +0,0 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
-) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= initial_value %>)
-);

data/lib/rggen/built_in/bit_field/type/rof.rb

@@ -1,17 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rof) do
-  register_map do
-    read_only
-    non_volatile
-    initial_value require: true
-  end
-
-  sv_rtl do
-    main_code :bit_field, from_template: true
-  end
-
-  sv_ral do
-    access 'RO'
-  end
-end

data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb

@@ -1,13 +0,0 @@
-<%= module_name %> #(
-<% if [:w0s, :w1s].include?(bit_field.type) %>
-  .SET_VALUE      (<%= set_value %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb

@@ -1,46 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rs) do
-  register_map do
-    read_only
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s]) do
-  register_map do
-    read_write
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
-  sv_rtl do
-    build do
-      input :register_block, :clear, {
-        name: "i_#{full_name}_clear", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-      output :register_block, :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def module_name
-      if bit_field.type == :rs
-        'rggen_bit_field_rs'
-      else
-        'rggen_bit_field_w01s'
-      end
-    end
-
-    def set_value
-      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
-    end
-  end
-end

data/lib/rggen/built_in/bit_field/type/rw_wo.erb

@@ -1,9 +0,0 @@
-rggen_bit_field_<%= bit_field.type %> #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/built_in/bit_field/type/rw_wo.rb

@@ -1,30 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rw) do
-  register_map do
-    read_write
-    non_volatile
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, :wo) do
-  register_map do
-    write_only
-    non_volatile
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
-  sv_rtl do
-    build do
-      output :register_block, :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-  end
-end

data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb

@@ -1,16 +0,0 @@
-rggen_bit_field_<%= bit_field.type %> #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-<% if bit_field.type == :rwc %>
-  .i_clear      (<%= control_signal %>),
-<% elsif bit_field.type == :rwe %>
-  .i_enable     (<%= control_signal %>),
-<% else %>
-  .i_lock       (<%= control_signal %>),
-<% end %>
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb

@@ -1,92 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwe, :rwl]) do
-  register_map do
-    read_write
-    volatile? { bit_field.type == :rwc || !bit_field.reference? }
-    initial_value require: true
-    reference use: true, width: 1
-  end
-
-  sv_rtl do
-    build do
-      if clear_port?
-        input :register_block, :clear, {
-          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      if enable_port?
-        input :register_block, :enable, {
-          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      if lock_port?
-        input :register_block, :lock, {
-          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :register_block, :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def clear_port?
-      bit_field.type == :rwc && !bit_field.reference?
-    end
-
-    def enable_port?
-      bit_field.type == :rwe && !bit_field.reference?
-    end
-
-    def lock_port?
-      bit_field.type == :rwl && !bit_field.reference?
-    end
-
-    def control_signal
-      reference_bit_field || control_port[loop_variables]
-    end
-
-    def control_port
-      case bit_field.type
-      when :rwc
-        clear
-      when :rwe
-        enable
-      when :rwl
-        lock
-      end
-    end
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
-  sv_ral do
-    access 'RW'
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
-  sv_ral do
-    model_name do
-      "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
-    end
-
-    private
-
-    def reference_names
-      reference = bit_field.reference
-      register = reference&.register
-      [register&.name, reference&.name]
-        .map { |name| string(name) }
-        .join(', ')
-    end
-  end
-end

data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb

@@ -1,9 +0,0 @@
-rggen_bit_field_w01trg #(
-  .TRIGGER_VALUE  (<%= trigger_value %>),
-  .WIDTH          (<%= width %>)
-) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_trigger    (<%= trigger[loop_variables] %>)
-);

data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb

@@ -1,29 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
-  register_map do
-    write_only
-    non_volatile
-  end
-
-  sv_rtl do
-    build do
-      output :register_block, :trigger, {
-        name: "o_#{full_name}_trigger", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def trigger_value
-      bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1)
-    end
-  end
-
-  sv_ral do
-    model_name { "rggen_ral_#{bit_field.type}_field" }
-  end
-end

data/lib/rggen/built_in/global/address_width.rb

@@ -1,34 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:global, :address_width) do
-  configuration do
-    property :address_width, default: 32
-
-    build do |value|
-      @address_width =
-        begin
-          Integer(value)
-        rescue ArgumentError, TypeError
-          error "cannot convert #{value.inspect} into address width"
-        end
-    end
-
-    verify(:component) do
-      error_condition { address_width < min_address_width }
-      message do
-        'input address width is less than minimum address width: ' \
-        "address width #{address_width} " \
-        "minimum address width #{min_address_width}"
-      end
-    end
-
-    printable :address_width
-
-    private
-
-    def min_address_width
-      byte_width = configuration.byte_width
-      byte_width == 1 ? 1 : (byte_width - 1).bit_length
-    end
-  end
-end