rggen 0.12.0 → 0.13.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +13 -2
- data/lib/rggen.rb +0 -1
- data/lib/rggen/default.rb +7 -0
- data/lib/rggen/default_setup_file.rb +1 -2
- data/lib/rggen/version.rb +1 -3
- metadata +25 -81
- data/lib/rggen/built_in.rb +0 -57
- data/lib/rggen/built_in/bit_field/bit_assignment.rb +0 -114
- data/lib/rggen/built_in/bit_field/comment.rb +0 -18
- data/lib/rggen/built_in/bit_field/initial_value.rb +0 -75
- data/lib/rggen/built_in/bit_field/name.rb +0 -41
- data/lib/rggen/built_in/bit_field/reference.rb +0 -139
- data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +0 -89
- data/lib/rggen/built_in/bit_field/type.rb +0 -245
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +0 -59
- data/lib/rggen/built_in/bit_field/type/reserved.erb +0 -3
- data/lib/rggen/built_in/bit_field/type/reserved.rb +0 -16
- data/lib/rggen/built_in/bit_field/type/ro.erb +0 -6
- data/lib/rggen/built_in/bit_field/type/ro.rb +0 -31
- data/lib/rggen/built_in/bit_field/type/rof.erb +0 -6
- data/lib/rggen/built_in/bit_field/type/rof.rb +0 -17
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +0 -46
- data/lib/rggen/built_in/bit_field/type/rw_wo.erb +0 -9
- data/lib/rggen/built_in/bit_field/type/rw_wo.rb +0 -30
- data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +0 -16
- data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +0 -92
- data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +0 -9
- data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +0 -29
- data/lib/rggen/built_in/global/address_width.rb +0 -34
- data/lib/rggen/built_in/global/array_port_format.rb +0 -19
- data/lib/rggen/built_in/global/bus_width.rb +0 -35
- data/lib/rggen/built_in/global/fold_sv_interface_port.rb +0 -24
- data/lib/rggen/built_in/register/markdown.erb +0 -11
- data/lib/rggen/built_in/register/markdown.rb +0 -26
- data/lib/rggen/built_in/register/name.rb +0 -36
- data/lib/rggen/built_in/register/offset_address.rb +0 -106
- data/lib/rggen/built_in/register/size.rb +0 -95
- data/lib/rggen/built_in/register/sv_rtl_top.rb +0 -82
- data/lib/rggen/built_in/register/type.rb +0 -344
- data/lib/rggen/built_in/register/type/default_sv_ral.erb +0 -8
- data/lib/rggen/built_in/register/type/default_sv_rtl.erb +0 -15
- data/lib/rggen/built_in/register/type/external.erb +0 -11
- data/lib/rggen/built_in/register/type/external.rb +0 -128
- data/lib/rggen/built_in/register/type/indirect.rb +0 -327
- data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +0 -13
- data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +0 -17
- data/lib/rggen/built_in/register_block/byte_size.rb +0 -61
- data/lib/rggen/built_in/register_block/markdown.erb +0 -8
- data/lib/rggen/built_in/register_block/markdown.rb +0 -36
- data/lib/rggen/built_in/register_block/name.rb +0 -38
- data/lib/rggen/built_in/register_block/protocol.rb +0 -100
- data/lib/rggen/built_in/register_block/protocol/apb.erb +0 -10
- data/lib/rggen/built_in/register_block/protocol/apb.rb +0 -89
- data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +0 -11
- data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +0 -125
- data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/built_in/register_block/sv_ral_package.rb +0 -65
- data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +0 -9
- data/lib/rggen/built_in/register_block/sv_rtl_top.rb +0 -86
- data/lib/rggen/built_in/version.rb +0 -7
- data/lib/rggen/setup/default.rb +0 -30
- data/sample/block_0.md +0 -155
- data/sample/block_0.rb +0 -90
- data/sample/block_0.sv +0 -678
- data/sample/block_0.xlsx +0 -0
- data/sample/block_0.yml +0 -99
- data/sample/block_0_ral_pkg.sv +0 -184
- data/sample/block_1.md +0 -39
- data/sample/block_1.rb +0 -22
- data/sample/block_1.sv +0 -136
- data/sample/block_1.xlsx +0 -0
- data/sample/block_1.yml +0 -26
- data/sample/block_1_ral_pkg.sv +0 -68
- data/sample/config.json +0 -5
- data/sample/config.yml +0 -3
data/sample/block_0.sv
DELETED
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`ifndef rggen_connect_bit_field_if
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`define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
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assign FIF.valid = RIF.valid; \
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assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; \
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assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; \
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assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; \
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assign RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
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assign RIF.value[LSB+:WIDTH] = FIF.value;
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`endif
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module block_0
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import rggen_rtl_pkg::*;
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(
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input logic i_clk,
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input logic i_rst_n,
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rggen_apb_if.slave apb_if,
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output logic [3:0] o_register_0_bit_field_0,
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output logic [3:0] o_register_0_bit_field_1,
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output logic o_register_0_bit_field_2,
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input logic [3:0] i_register_1_bit_field_0,
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input logic [3:0] i_register_1_bit_field_1,
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output logic [3:0] o_register_2_bit_field_0,
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output logic [3:0] o_register_2_bit_field_1_trigger,
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output logic [3:0] o_register_2_bit_field_2_trigger,
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input logic [3:0] i_register_3_bit_field_0_set,
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output logic [3:0] o_register_3_bit_field_0,
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input logic [3:0] i_register_3_bit_field_1_set,
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output logic [3:0] o_register_3_bit_field_1,
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output logic [3:0] o_register_3_bit_field_1_unmasked,
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input logic [3:0] i_register_3_bit_field_3_clear,
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output logic [3:0] o_register_3_bit_field_3,
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input logic i_register_4_bit_field_0_clear,
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output logic [3:0] o_register_4_bit_field_0,
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output logic [3:0] o_register_4_bit_field_1,
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input logic i_register_4_bit_field_2_enable,
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output logic [3:0] o_register_4_bit_field_2,
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output logic [3:0] o_register_4_bit_field_3,
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input logic i_register_4_bit_field_4_lock,
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output logic [3:0] o_register_4_bit_field_4,
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output logic [3:0] o_register_4_bit_field_5,
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input logic [3:0] i_register_5_bit_field_0_set,
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output logic [3:0] o_register_5_bit_field_0,
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input logic [3:0] i_register_5_bit_field_1_set,
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output logic [3:0] o_register_5_bit_field_1,
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output logic [3:0] o_register_5_bit_field_1_unmasked,
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input logic [3:0] i_register_5_bit_field_3_set,
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output logic [3:0] o_register_5_bit_field_3,
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input logic [3:0] i_register_5_bit_field_4_set,
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output logic [3:0] o_register_5_bit_field_4,
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output logic [3:0] o_register_5_bit_field_4_unmasked,
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input logic [3:0] i_register_5_bit_field_6_clear,
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output logic [3:0] o_register_5_bit_field_6,
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input logic [3:0] i_register_5_bit_field_7_clear,
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output logic [3:0] o_register_5_bit_field_7,
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output logic [3:0][3:0][7:0] o_register_6_bit_field_0,
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output logic [3:0][3:0][7:0] o_register_6_bit_field_1,
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output logic [1:0][3:0][3:0][7:0] o_register_7_bit_field_0,
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output logic [1:0][3:0][3:0][7:0] o_register_7_bit_field_1,
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rggen_bus_if.master register_8_bus_if
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);
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rggen_register_if #(8, 32, 64) register_if[19]();
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rggen_apb_adapter #(
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.ADDRESS_WIDTH (8),
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.BUS_WIDTH (32),
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.REGISTERS (19)
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) u_adapter (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.apb_if (apb_if),
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.register_if (register_if)
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);
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generate if (1) begin : g_register_0
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rggen_bit_field_if #(32) bit_field_if();
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rggen_default_register #(
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.READABLE (1),
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.WRITABLE (1),
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.ADDRESS_WIDTH (8),
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.OFFSET_ADDRESS (8'h00),
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.BUS_WIDTH (32),
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.DATA_WIDTH (32),
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.VALID_BITS (32'h000001ff),
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.REGISTER_INDEX (0)
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) u_register (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.register_if (register_if[0]),
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.bit_field_if (bit_field_if)
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);
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if (1) begin : g_bit_field_0
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rggen_bit_field_if #(4) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
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rggen_bit_field_rw #(
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.WIDTH (4),
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.INITIAL_VALUE (4'h0)
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) u_bit_field (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.bit_field_if (bit_field_sub_if),
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.o_value (o_register_0_bit_field_0)
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);
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end
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if (1) begin : g_bit_field_1
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rggen_bit_field_if #(4) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
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rggen_bit_field_rw #(
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.WIDTH (4),
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.INITIAL_VALUE (4'h0)
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) u_bit_field (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.bit_field_if (bit_field_sub_if),
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.o_value (o_register_0_bit_field_1)
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);
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end
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if (1) begin : g_bit_field_2
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rggen_bit_field_if #(1) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 1)
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rggen_bit_field_rw #(
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.WIDTH (1),
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.INITIAL_VALUE (1'h0)
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) u_bit_field (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.bit_field_if (bit_field_sub_if),
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.o_value (o_register_0_bit_field_2)
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);
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end
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end endgenerate
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generate if (1) begin : g_register_1
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rggen_bit_field_if #(32) bit_field_if();
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rggen_default_register #(
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.READABLE (1),
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.WRITABLE (0),
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.ADDRESS_WIDTH (8),
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.OFFSET_ADDRESS (8'h04),
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.BUS_WIDTH (32),
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.DATA_WIDTH (32),
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.VALID_BITS (32'hffff0f0f),
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.REGISTER_INDEX (0)
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) u_register (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.register_if (register_if[1]),
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.bit_field_if (bit_field_if)
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);
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if (1) begin : g_bit_field_0
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rggen_bit_field_if #(4) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
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rggen_bit_field_ro #(
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.WIDTH (4)
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) u_bit_field (
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.bit_field_if (bit_field_sub_if),
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.i_value (i_register_1_bit_field_0)
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);
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end
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if (1) begin : g_bit_field_1
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rggen_bit_field_if #(4) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
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rggen_bit_field_ro #(
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.WIDTH (4)
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) u_bit_field (
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.bit_field_if (bit_field_sub_if),
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.i_value (i_register_1_bit_field_1)
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);
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end
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if (1) begin : g_bit_field_2
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rggen_bit_field_if #(8) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 8)
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rggen_bit_field_ro #(
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.WIDTH (8)
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) u_bit_field (
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.bit_field_if (bit_field_sub_if),
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.i_value (8'hab)
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);
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end
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if (1) begin : g_bit_field_3
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rggen_bit_field_if #(8) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 8)
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rggen_bit_field_reserved u_bit_field (
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.bit_field_if (bit_field_sub_if)
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);
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end
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end endgenerate
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generate if (1) begin : g_register_2
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rggen_bit_field_if #(32) bit_field_if();
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rggen_default_register #(
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.READABLE (0),
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.WRITABLE (1),
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.ADDRESS_WIDTH (8),
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.OFFSET_ADDRESS (8'h04),
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.BUS_WIDTH (32),
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.DATA_WIDTH (32),
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.VALID_BITS (32'h000f0f0f),
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.REGISTER_INDEX (0)
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) u_register (
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.i_clk (i_clk),
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.i_rst_n (i_rst_n),
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.register_if (register_if[2]),
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.bit_field_if (bit_field_if)
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);
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if (1) begin : g_bit_field_0
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rggen_bit_field_if #(4) bit_field_sub_if();
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`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
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rggen_bit_field_wo #(
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|
204
|
-
.WIDTH (4),
|
|
205
|
-
.INITIAL_VALUE (4'h0)
|
|
206
|
-
) u_bit_field (
|
|
207
|
-
.i_clk (i_clk),
|
|
208
|
-
.i_rst_n (i_rst_n),
|
|
209
|
-
.bit_field_if (bit_field_sub_if),
|
|
210
|
-
.o_value (o_register_2_bit_field_0)
|
|
211
|
-
);
|
|
212
|
-
end
|
|
213
|
-
if (1) begin : g_bit_field_1
|
|
214
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
215
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
|
|
216
|
-
rggen_bit_field_w01trg #(
|
|
217
|
-
.TRIGGER_VALUE (1'b0),
|
|
218
|
-
.WIDTH (4)
|
|
219
|
-
) u_bit_field (
|
|
220
|
-
.i_clk (i_clk),
|
|
221
|
-
.i_rst_n (i_rst_n),
|
|
222
|
-
.bit_field_if (bit_field_sub_if),
|
|
223
|
-
.o_trigger (o_register_2_bit_field_1_trigger)
|
|
224
|
-
);
|
|
225
|
-
end
|
|
226
|
-
if (1) begin : g_bit_field_2
|
|
227
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
228
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
|
|
229
|
-
rggen_bit_field_w01trg #(
|
|
230
|
-
.TRIGGER_VALUE (1'b1),
|
|
231
|
-
.WIDTH (4)
|
|
232
|
-
) u_bit_field (
|
|
233
|
-
.i_clk (i_clk),
|
|
234
|
-
.i_rst_n (i_rst_n),
|
|
235
|
-
.bit_field_if (bit_field_sub_if),
|
|
236
|
-
.o_trigger (o_register_2_bit_field_2_trigger)
|
|
237
|
-
);
|
|
238
|
-
end
|
|
239
|
-
end endgenerate
|
|
240
|
-
generate if (1) begin : g_register_3
|
|
241
|
-
rggen_bit_field_if #(32) bit_field_if();
|
|
242
|
-
rggen_default_register #(
|
|
243
|
-
.READABLE (1),
|
|
244
|
-
.WRITABLE (0),
|
|
245
|
-
.ADDRESS_WIDTH (8),
|
|
246
|
-
.OFFSET_ADDRESS (8'h08),
|
|
247
|
-
.BUS_WIDTH (32),
|
|
248
|
-
.DATA_WIDTH (32),
|
|
249
|
-
.VALID_BITS (32'h000fff0f),
|
|
250
|
-
.REGISTER_INDEX (0)
|
|
251
|
-
) u_register (
|
|
252
|
-
.i_clk (i_clk),
|
|
253
|
-
.i_rst_n (i_rst_n),
|
|
254
|
-
.register_if (register_if[3]),
|
|
255
|
-
.bit_field_if (bit_field_if)
|
|
256
|
-
);
|
|
257
|
-
if (1) begin : g_bit_field_0
|
|
258
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
259
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
|
|
260
|
-
rggen_bit_field_rc #(
|
|
261
|
-
.WIDTH (4),
|
|
262
|
-
.INITIAL_VALUE (4'h0)
|
|
263
|
-
) u_bit_field (
|
|
264
|
-
.i_clk (i_clk),
|
|
265
|
-
.i_rst_n (i_rst_n),
|
|
266
|
-
.bit_field_if (bit_field_sub_if),
|
|
267
|
-
.i_set (i_register_3_bit_field_0_set),
|
|
268
|
-
.i_mask (4'hf),
|
|
269
|
-
.o_value (o_register_3_bit_field_0),
|
|
270
|
-
.o_value_unmasked ()
|
|
271
|
-
);
|
|
272
|
-
end
|
|
273
|
-
if (1) begin : g_bit_field_1
|
|
274
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
275
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
|
|
276
|
-
rggen_bit_field_rc #(
|
|
277
|
-
.WIDTH (4),
|
|
278
|
-
.INITIAL_VALUE (4'h0)
|
|
279
|
-
) u_bit_field (
|
|
280
|
-
.i_clk (i_clk),
|
|
281
|
-
.i_rst_n (i_rst_n),
|
|
282
|
-
.bit_field_if (bit_field_sub_if),
|
|
283
|
-
.i_set (i_register_3_bit_field_1_set),
|
|
284
|
-
.i_mask (register_if[0].value[0+:4]),
|
|
285
|
-
.o_value (o_register_3_bit_field_1),
|
|
286
|
-
.o_value_unmasked (o_register_3_bit_field_1_unmasked)
|
|
287
|
-
);
|
|
288
|
-
end
|
|
289
|
-
if (1) begin : g_bit_field_2
|
|
290
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
291
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
|
|
292
|
-
rggen_bit_field_ro #(
|
|
293
|
-
.WIDTH (4)
|
|
294
|
-
) u_bit_field (
|
|
295
|
-
.bit_field_if (bit_field_sub_if),
|
|
296
|
-
.i_value (register_if[3].value[8+:4])
|
|
297
|
-
);
|
|
298
|
-
end
|
|
299
|
-
if (1) begin : g_bit_field_3
|
|
300
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
301
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
|
|
302
|
-
rggen_bit_field_rs #(
|
|
303
|
-
.WIDTH (4),
|
|
304
|
-
.INITIAL_VALUE (4'h0)
|
|
305
|
-
) u_bit_field (
|
|
306
|
-
.i_clk (i_clk),
|
|
307
|
-
.i_rst_n (i_rst_n),
|
|
308
|
-
.bit_field_if (bit_field_sub_if),
|
|
309
|
-
.i_clear (i_register_3_bit_field_3_clear),
|
|
310
|
-
.o_value (o_register_3_bit_field_3)
|
|
311
|
-
);
|
|
312
|
-
end
|
|
313
|
-
end endgenerate
|
|
314
|
-
generate if (1) begin : g_register_4
|
|
315
|
-
rggen_bit_field_if #(32) bit_field_if();
|
|
316
|
-
rggen_default_register #(
|
|
317
|
-
.READABLE (1),
|
|
318
|
-
.WRITABLE (1),
|
|
319
|
-
.ADDRESS_WIDTH (8),
|
|
320
|
-
.OFFSET_ADDRESS (8'h0c),
|
|
321
|
-
.BUS_WIDTH (32),
|
|
322
|
-
.DATA_WIDTH (32),
|
|
323
|
-
.VALID_BITS (32'h00ffffff),
|
|
324
|
-
.REGISTER_INDEX (0)
|
|
325
|
-
) u_register (
|
|
326
|
-
.i_clk (i_clk),
|
|
327
|
-
.i_rst_n (i_rst_n),
|
|
328
|
-
.register_if (register_if[4]),
|
|
329
|
-
.bit_field_if (bit_field_if)
|
|
330
|
-
);
|
|
331
|
-
if (1) begin : g_bit_field_0
|
|
332
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
333
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
|
|
334
|
-
rggen_bit_field_rwc #(
|
|
335
|
-
.WIDTH (4),
|
|
336
|
-
.INITIAL_VALUE (4'h0)
|
|
337
|
-
) u_bit_field (
|
|
338
|
-
.i_clk (i_clk),
|
|
339
|
-
.i_rst_n (i_rst_n),
|
|
340
|
-
.bit_field_if (bit_field_sub_if),
|
|
341
|
-
.i_clear (i_register_4_bit_field_0_clear),
|
|
342
|
-
.o_value (o_register_4_bit_field_0)
|
|
343
|
-
);
|
|
344
|
-
end
|
|
345
|
-
if (1) begin : g_bit_field_1
|
|
346
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
347
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
|
|
348
|
-
rggen_bit_field_rwc #(
|
|
349
|
-
.WIDTH (4),
|
|
350
|
-
.INITIAL_VALUE (4'h0)
|
|
351
|
-
) u_bit_field (
|
|
352
|
-
.i_clk (i_clk),
|
|
353
|
-
.i_rst_n (i_rst_n),
|
|
354
|
-
.bit_field_if (bit_field_sub_if),
|
|
355
|
-
.i_clear (register_if[2].value[8+:1]),
|
|
356
|
-
.o_value (o_register_4_bit_field_1)
|
|
357
|
-
);
|
|
358
|
-
end
|
|
359
|
-
if (1) begin : g_bit_field_2
|
|
360
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
361
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
|
|
362
|
-
rggen_bit_field_rwe #(
|
|
363
|
-
.WIDTH (4),
|
|
364
|
-
.INITIAL_VALUE (4'h0)
|
|
365
|
-
) u_bit_field (
|
|
366
|
-
.i_clk (i_clk),
|
|
367
|
-
.i_rst_n (i_rst_n),
|
|
368
|
-
.bit_field_if (bit_field_sub_if),
|
|
369
|
-
.i_enable (i_register_4_bit_field_2_enable),
|
|
370
|
-
.o_value (o_register_4_bit_field_2)
|
|
371
|
-
);
|
|
372
|
-
end
|
|
373
|
-
if (1) begin : g_bit_field_3
|
|
374
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
375
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
|
|
376
|
-
rggen_bit_field_rwe #(
|
|
377
|
-
.WIDTH (4),
|
|
378
|
-
.INITIAL_VALUE (4'h0)
|
|
379
|
-
) u_bit_field (
|
|
380
|
-
.i_clk (i_clk),
|
|
381
|
-
.i_rst_n (i_rst_n),
|
|
382
|
-
.bit_field_if (bit_field_sub_if),
|
|
383
|
-
.i_enable (register_if[0].value[8+:1]),
|
|
384
|
-
.o_value (o_register_4_bit_field_3)
|
|
385
|
-
);
|
|
386
|
-
end
|
|
387
|
-
if (1) begin : g_bit_field_4
|
|
388
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
389
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
|
|
390
|
-
rggen_bit_field_rwl #(
|
|
391
|
-
.WIDTH (4),
|
|
392
|
-
.INITIAL_VALUE (4'h0)
|
|
393
|
-
) u_bit_field (
|
|
394
|
-
.i_clk (i_clk),
|
|
395
|
-
.i_rst_n (i_rst_n),
|
|
396
|
-
.bit_field_if (bit_field_sub_if),
|
|
397
|
-
.i_lock (i_register_4_bit_field_4_lock),
|
|
398
|
-
.o_value (o_register_4_bit_field_4)
|
|
399
|
-
);
|
|
400
|
-
end
|
|
401
|
-
if (1) begin : g_bit_field_5
|
|
402
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
403
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4)
|
|
404
|
-
rggen_bit_field_rwl #(
|
|
405
|
-
.WIDTH (4),
|
|
406
|
-
.INITIAL_VALUE (4'h0)
|
|
407
|
-
) u_bit_field (
|
|
408
|
-
.i_clk (i_clk),
|
|
409
|
-
.i_rst_n (i_rst_n),
|
|
410
|
-
.bit_field_if (bit_field_sub_if),
|
|
411
|
-
.i_lock (register_if[0].value[8+:1]),
|
|
412
|
-
.o_value (o_register_4_bit_field_5)
|
|
413
|
-
);
|
|
414
|
-
end
|
|
415
|
-
end endgenerate
|
|
416
|
-
generate if (1) begin : g_register_5
|
|
417
|
-
rggen_bit_field_if #(32) bit_field_if();
|
|
418
|
-
rggen_default_register #(
|
|
419
|
-
.READABLE (1),
|
|
420
|
-
.WRITABLE (1),
|
|
421
|
-
.ADDRESS_WIDTH (8),
|
|
422
|
-
.OFFSET_ADDRESS (8'h10),
|
|
423
|
-
.BUS_WIDTH (32),
|
|
424
|
-
.DATA_WIDTH (32),
|
|
425
|
-
.VALID_BITS (32'hffffffff),
|
|
426
|
-
.REGISTER_INDEX (0)
|
|
427
|
-
) u_register (
|
|
428
|
-
.i_clk (i_clk),
|
|
429
|
-
.i_rst_n (i_rst_n),
|
|
430
|
-
.register_if (register_if[5]),
|
|
431
|
-
.bit_field_if (bit_field_if)
|
|
432
|
-
);
|
|
433
|
-
if (1) begin : g_bit_field_0
|
|
434
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
435
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
|
|
436
|
-
rggen_bit_field_w01c #(
|
|
437
|
-
.CLEAR_VALUE (1'b0),
|
|
438
|
-
.WIDTH (4),
|
|
439
|
-
.INITIAL_VALUE (4'h0)
|
|
440
|
-
) u_bit_field (
|
|
441
|
-
.i_clk (i_clk),
|
|
442
|
-
.i_rst_n (i_rst_n),
|
|
443
|
-
.bit_field_if (bit_field_sub_if),
|
|
444
|
-
.i_set (i_register_5_bit_field_0_set),
|
|
445
|
-
.i_mask (4'hf),
|
|
446
|
-
.o_value (o_register_5_bit_field_0),
|
|
447
|
-
.o_value_unmasked ()
|
|
448
|
-
);
|
|
449
|
-
end
|
|
450
|
-
if (1) begin : g_bit_field_1
|
|
451
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
452
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
|
|
453
|
-
rggen_bit_field_w01c #(
|
|
454
|
-
.CLEAR_VALUE (1'b0),
|
|
455
|
-
.WIDTH (4),
|
|
456
|
-
.INITIAL_VALUE (4'h0)
|
|
457
|
-
) u_bit_field (
|
|
458
|
-
.i_clk (i_clk),
|
|
459
|
-
.i_rst_n (i_rst_n),
|
|
460
|
-
.bit_field_if (bit_field_sub_if),
|
|
461
|
-
.i_set (i_register_5_bit_field_1_set),
|
|
462
|
-
.i_mask (register_if[0].value[0+:4]),
|
|
463
|
-
.o_value (o_register_5_bit_field_1),
|
|
464
|
-
.o_value_unmasked (o_register_5_bit_field_1_unmasked)
|
|
465
|
-
);
|
|
466
|
-
end
|
|
467
|
-
if (1) begin : g_bit_field_2
|
|
468
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
469
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
|
|
470
|
-
rggen_bit_field_ro #(
|
|
471
|
-
.WIDTH (4)
|
|
472
|
-
) u_bit_field (
|
|
473
|
-
.bit_field_if (bit_field_sub_if),
|
|
474
|
-
.i_value (register_if[5].value[4+:4])
|
|
475
|
-
);
|
|
476
|
-
end
|
|
477
|
-
if (1) begin : g_bit_field_3
|
|
478
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
479
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
|
|
480
|
-
rggen_bit_field_w01c #(
|
|
481
|
-
.CLEAR_VALUE (1'b1),
|
|
482
|
-
.WIDTH (4),
|
|
483
|
-
.INITIAL_VALUE (4'h0)
|
|
484
|
-
) u_bit_field (
|
|
485
|
-
.i_clk (i_clk),
|
|
486
|
-
.i_rst_n (i_rst_n),
|
|
487
|
-
.bit_field_if (bit_field_sub_if),
|
|
488
|
-
.i_set (i_register_5_bit_field_3_set),
|
|
489
|
-
.i_mask (4'hf),
|
|
490
|
-
.o_value (o_register_5_bit_field_3),
|
|
491
|
-
.o_value_unmasked ()
|
|
492
|
-
);
|
|
493
|
-
end
|
|
494
|
-
if (1) begin : g_bit_field_4
|
|
495
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
496
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
|
|
497
|
-
rggen_bit_field_w01c #(
|
|
498
|
-
.CLEAR_VALUE (1'b1),
|
|
499
|
-
.WIDTH (4),
|
|
500
|
-
.INITIAL_VALUE (4'h0)
|
|
501
|
-
) u_bit_field (
|
|
502
|
-
.i_clk (i_clk),
|
|
503
|
-
.i_rst_n (i_rst_n),
|
|
504
|
-
.bit_field_if (bit_field_sub_if),
|
|
505
|
-
.i_set (i_register_5_bit_field_4_set),
|
|
506
|
-
.i_mask (register_if[0].value[0+:4]),
|
|
507
|
-
.o_value (o_register_5_bit_field_4),
|
|
508
|
-
.o_value_unmasked (o_register_5_bit_field_4_unmasked)
|
|
509
|
-
);
|
|
510
|
-
end
|
|
511
|
-
if (1) begin : g_bit_field_5
|
|
512
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
513
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4)
|
|
514
|
-
rggen_bit_field_ro #(
|
|
515
|
-
.WIDTH (4)
|
|
516
|
-
) u_bit_field (
|
|
517
|
-
.bit_field_if (bit_field_sub_if),
|
|
518
|
-
.i_value (register_if[5].value[16+:4])
|
|
519
|
-
);
|
|
520
|
-
end
|
|
521
|
-
if (1) begin : g_bit_field_6
|
|
522
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
523
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 4)
|
|
524
|
-
rggen_bit_field_w01s #(
|
|
525
|
-
.SET_VALUE (1'b0),
|
|
526
|
-
.WIDTH (4),
|
|
527
|
-
.INITIAL_VALUE (4'h0)
|
|
528
|
-
) u_bit_field (
|
|
529
|
-
.i_clk (i_clk),
|
|
530
|
-
.i_rst_n (i_rst_n),
|
|
531
|
-
.bit_field_if (bit_field_sub_if),
|
|
532
|
-
.i_clear (i_register_5_bit_field_6_clear),
|
|
533
|
-
.o_value (o_register_5_bit_field_6)
|
|
534
|
-
);
|
|
535
|
-
end
|
|
536
|
-
if (1) begin : g_bit_field_7
|
|
537
|
-
rggen_bit_field_if #(4) bit_field_sub_if();
|
|
538
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 28, 4)
|
|
539
|
-
rggen_bit_field_w01s #(
|
|
540
|
-
.SET_VALUE (1'b1),
|
|
541
|
-
.WIDTH (4),
|
|
542
|
-
.INITIAL_VALUE (4'h0)
|
|
543
|
-
) u_bit_field (
|
|
544
|
-
.i_clk (i_clk),
|
|
545
|
-
.i_rst_n (i_rst_n),
|
|
546
|
-
.bit_field_if (bit_field_sub_if),
|
|
547
|
-
.i_clear (i_register_5_bit_field_7_clear),
|
|
548
|
-
.o_value (o_register_5_bit_field_7)
|
|
549
|
-
);
|
|
550
|
-
end
|
|
551
|
-
end endgenerate
|
|
552
|
-
generate if (1) begin : g_register_6
|
|
553
|
-
genvar i;
|
|
554
|
-
for (i = 0;i < 4;++i) begin : g
|
|
555
|
-
rggen_bit_field_if #(64) bit_field_if();
|
|
556
|
-
rggen_default_register #(
|
|
557
|
-
.READABLE (1),
|
|
558
|
-
.WRITABLE (1),
|
|
559
|
-
.ADDRESS_WIDTH (8),
|
|
560
|
-
.OFFSET_ADDRESS (8'h20),
|
|
561
|
-
.BUS_WIDTH (32),
|
|
562
|
-
.DATA_WIDTH (64),
|
|
563
|
-
.VALID_BITS (64'hffffffffffffffff),
|
|
564
|
-
.REGISTER_INDEX (i)
|
|
565
|
-
) u_register (
|
|
566
|
-
.i_clk (i_clk),
|
|
567
|
-
.i_rst_n (i_rst_n),
|
|
568
|
-
.register_if (register_if[6+i]),
|
|
569
|
-
.bit_field_if (bit_field_if)
|
|
570
|
-
);
|
|
571
|
-
if (1) begin : g_bit_field_0
|
|
572
|
-
genvar j;
|
|
573
|
-
for (j = 0;j < 4;++j) begin : g
|
|
574
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
|
575
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*j, 8)
|
|
576
|
-
rggen_bit_field_rw #(
|
|
577
|
-
.WIDTH (8),
|
|
578
|
-
.INITIAL_VALUE (8'h00)
|
|
579
|
-
) u_bit_field (
|
|
580
|
-
.i_clk (i_clk),
|
|
581
|
-
.i_rst_n (i_rst_n),
|
|
582
|
-
.bit_field_if (bit_field_sub_if),
|
|
583
|
-
.o_value (o_register_6_bit_field_0[i][j])
|
|
584
|
-
);
|
|
585
|
-
end
|
|
586
|
-
end
|
|
587
|
-
if (1) begin : g_bit_field_1
|
|
588
|
-
genvar j;
|
|
589
|
-
for (j = 0;j < 4;++j) begin : g
|
|
590
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
|
591
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*j, 8)
|
|
592
|
-
rggen_bit_field_rw #(
|
|
593
|
-
.WIDTH (8),
|
|
594
|
-
.INITIAL_VALUE (8'h00)
|
|
595
|
-
) u_bit_field (
|
|
596
|
-
.i_clk (i_clk),
|
|
597
|
-
.i_rst_n (i_rst_n),
|
|
598
|
-
.bit_field_if (bit_field_sub_if),
|
|
599
|
-
.o_value (o_register_6_bit_field_1[i][j])
|
|
600
|
-
);
|
|
601
|
-
end
|
|
602
|
-
end
|
|
603
|
-
end
|
|
604
|
-
end endgenerate
|
|
605
|
-
generate if (1) begin : g_register_7
|
|
606
|
-
genvar i;
|
|
607
|
-
genvar j;
|
|
608
|
-
for (i = 0;i < 2;++i) begin : g
|
|
609
|
-
for (j = 0;j < 4;++j) begin : g
|
|
610
|
-
logic [8:0] indirect_index;
|
|
611
|
-
rggen_bit_field_if #(64) bit_field_if();
|
|
612
|
-
assign indirect_index = {register_if[0].value[0+:4], register_if[0].value[4+:4], register_if[0].value[8+:1]};
|
|
613
|
-
rggen_indirect_register #(
|
|
614
|
-
.READABLE (1),
|
|
615
|
-
.WRITABLE (1),
|
|
616
|
-
.ADDRESS_WIDTH (8),
|
|
617
|
-
.OFFSET_ADDRESS (8'h40),
|
|
618
|
-
.BUS_WIDTH (32),
|
|
619
|
-
.DATA_WIDTH (64),
|
|
620
|
-
.VALID_BITS (64'hffffffffffffffff),
|
|
621
|
-
.INDIRECT_INDEX_WIDTH (9),
|
|
622
|
-
.INDIRECT_INDEX_VALUE ({i[0+:4], j[0+:4], 1'h1})
|
|
623
|
-
) u_register (
|
|
624
|
-
.i_clk (i_clk),
|
|
625
|
-
.i_rst_n (i_rst_n),
|
|
626
|
-
.register_if (register_if[10+4*i+j]),
|
|
627
|
-
.i_indirect_index (indirect_index),
|
|
628
|
-
.bit_field_if (bit_field_if)
|
|
629
|
-
);
|
|
630
|
-
if (1) begin : g_bit_field_0
|
|
631
|
-
genvar k;
|
|
632
|
-
for (k = 0;k < 4;++k) begin : g
|
|
633
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
|
634
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8)
|
|
635
|
-
rggen_bit_field_rw #(
|
|
636
|
-
.WIDTH (8),
|
|
637
|
-
.INITIAL_VALUE (8'h00)
|
|
638
|
-
) u_bit_field (
|
|
639
|
-
.i_clk (i_clk),
|
|
640
|
-
.i_rst_n (i_rst_n),
|
|
641
|
-
.bit_field_if (bit_field_sub_if),
|
|
642
|
-
.o_value (o_register_7_bit_field_0[i][j][k])
|
|
643
|
-
);
|
|
644
|
-
end
|
|
645
|
-
end
|
|
646
|
-
if (1) begin : g_bit_field_1
|
|
647
|
-
genvar k;
|
|
648
|
-
for (k = 0;k < 4;++k) begin : g
|
|
649
|
-
rggen_bit_field_if #(8) bit_field_sub_if();
|
|
650
|
-
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8)
|
|
651
|
-
rggen_bit_field_rw #(
|
|
652
|
-
.WIDTH (8),
|
|
653
|
-
.INITIAL_VALUE (8'h00)
|
|
654
|
-
) u_bit_field (
|
|
655
|
-
.i_clk (i_clk),
|
|
656
|
-
.i_rst_n (i_rst_n),
|
|
657
|
-
.bit_field_if (bit_field_sub_if),
|
|
658
|
-
.o_value (o_register_7_bit_field_1[i][j][k])
|
|
659
|
-
);
|
|
660
|
-
end
|
|
661
|
-
end
|
|
662
|
-
end
|
|
663
|
-
end
|
|
664
|
-
end endgenerate
|
|
665
|
-
generate if (1) begin : g_register_8
|
|
666
|
-
rggen_external_register #(
|
|
667
|
-
.ADDRESS_WIDTH (8),
|
|
668
|
-
.BUS_WIDTH (32),
|
|
669
|
-
.START_ADDRESS (8'h80),
|
|
670
|
-
.END_ADDRESS (8'hff)
|
|
671
|
-
) u_register (
|
|
672
|
-
.i_clk (i_clk),
|
|
673
|
-
.i_rst_n (i_rst_n),
|
|
674
|
-
.register_if (register_if[18]),
|
|
675
|
-
.bus_if (register_8_bus_if)
|
|
676
|
-
);
|
|
677
|
-
end endgenerate
|
|
678
|
-
endmodule
|