rggen-verilog 0.1.0

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Files changed (60) hide show
  1. checksums.yaml +7 -0
  2. data/CODE_OF_CONDUCT.md +74 -0
  3. data/LICENSE +21 -0
  4. data/README.md +74 -0
  5. data/lib/rggen/verilog.rb +64 -0
  6. data/lib/rggen/verilog/bit_field/type.rb +85 -0
  7. data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb +21 -0
  8. data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb +40 -0
  9. data/lib/rggen/verilog/bit_field/type/reserved.erb +10 -0
  10. data/lib/rggen/verilog/bit_field/type/reserved.rb +7 -0
  11. data/lib/rggen/verilog/bit_field/type/ro.erb +11 -0
  12. data/lib/rggen/verilog/bit_field/type/ro.rb +21 -0
  13. data/lib/rggen/verilog/bit_field/type/rof.erb +11 -0
  14. data/lib/rggen/verilog/bit_field/type/rof.rb +7 -0
  15. data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
  16. data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb +31 -0
  17. data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.erb +16 -0
  18. data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb +23 -0
  19. data/lib/rggen/verilog/bit_field/type/rwc.erb +15 -0
  20. data/lib/rggen/verilog/bit_field/type/rwc.rb +24 -0
  21. data/lib/rggen/verilog/bit_field/type/rwe.erb +15 -0
  22. data/lib/rggen/verilog/bit_field/type/rwe.rb +24 -0
  23. data/lib/rggen/verilog/bit_field/type/rwl.erb +15 -0
  24. data/lib/rggen/verilog/bit_field/type/rwl.rb +24 -0
  25. data/lib/rggen/verilog/bit_field/type/rws.erb +16 -0
  26. data/lib/rggen/verilog/bit_field/type/rws.rb +27 -0
  27. data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.erb +15 -0
  28. data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.rb +20 -0
  29. data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.erb +15 -0
  30. data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.rb +20 -0
  31. data/lib/rggen/verilog/bit_field/type/w0t_w1t.erb +15 -0
  32. data/lib/rggen/verilog/bit_field/type/w0t_w1t.rb +19 -0
  33. data/lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb +14 -0
  34. data/lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb +19 -0
  35. data/lib/rggen/verilog/bit_field/type/wrc_wrs.erb +14 -0
  36. data/lib/rggen/verilog/bit_field/type/wrc_wrs.rb +13 -0
  37. data/lib/rggen/verilog/bit_field/verilog_top.rb +89 -0
  38. data/lib/rggen/verilog/component.rb +7 -0
  39. data/lib/rggen/verilog/factories.rb +11 -0
  40. data/lib/rggen/verilog/feature.rb +35 -0
  41. data/lib/rggen/verilog/register/type.rb +101 -0
  42. data/lib/rggen/verilog/register/type/default.erb +29 -0
  43. data/lib/rggen/verilog/register/type/external.erb +27 -0
  44. data/lib/rggen/verilog/register/type/external.rb +45 -0
  45. data/lib/rggen/verilog/register/type/indirect.erb +31 -0
  46. data/lib/rggen/verilog/register/type/indirect.rb +18 -0
  47. data/lib/rggen/verilog/register/verilog_top.rb +58 -0
  48. data/lib/rggen/verilog/register_block/protocol.rb +51 -0
  49. data/lib/rggen/verilog/register_block/protocol/apb.erb +33 -0
  50. data/lib/rggen/verilog/register_block/protocol/apb.rb +40 -0
  51. data/lib/rggen/verilog/register_block/protocol/axi4lite.erb +48 -0
  52. data/lib/rggen/verilog/register_block/protocol/axi4lite.rb +92 -0
  53. data/lib/rggen/verilog/register_block/verilog_macros.erb +4 -0
  54. data/lib/rggen/verilog/register_block/verilog_top.rb +104 -0
  55. data/lib/rggen/verilog/register_file/verilog_top.rb +30 -0
  56. data/lib/rggen/verilog/setup.rb +11 -0
  57. data/lib/rggen/verilog/utility.rb +13 -0
  58. data/lib/rggen/verilog/utility/local_scope.rb +15 -0
  59. data/lib/rggen/verilog/version.rb +7 -0
  60. metadata +133 -0
@@ -0,0 +1,7 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
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+ module Verilog
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+ VERSION = '0.1.0'
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+ end
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+ end
metadata ADDED
@@ -0,0 +1,133 @@
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+ --- !ruby/object:Gem::Specification
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+ name: rggen-verilog
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+ version: !ruby/object:Gem::Version
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+ version: 0.1.0
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+ platform: ruby
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+ authors:
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+ - Taichi Ishitani
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+ autorequire:
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+ bindir: bin
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+ cert_chain: []
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+ date: 2020-10-24 00:00:00.000000000 Z
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+ dependencies:
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+ - !ruby/object:Gem::Dependency
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+ name: rggen-systemverilog
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+ requirement: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - ">="
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+ - !ruby/object:Gem::Version
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+ version: 0.23.1
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+ type: :runtime
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+ prerelease: false
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+ version_requirements: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - ">="
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+ - !ruby/object:Gem::Version
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+ version: 0.23.1
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+ - !ruby/object:Gem::Dependency
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+ name: bundler
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+ requirement: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - ">="
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+ - !ruby/object:Gem::Version
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+ version: '0'
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+ type: :development
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+ prerelease: false
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+ version_requirements: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - ">="
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+ - !ruby/object:Gem::Version
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+ version: '0'
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+ description: Verilog write plugin for RgGen
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+ email:
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+ - rggen@googlegroups.com
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+ executables: []
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+ extensions: []
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+ extra_rdoc_files: []
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+ files:
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+ - CODE_OF_CONDUCT.md
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+ - LICENSE
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+ - README.md
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+ - lib/rggen/verilog.rb
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+ - lib/rggen/verilog/bit_field/type.rb
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+ - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb
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+ - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb
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+ - lib/rggen/verilog/bit_field/type/reserved.erb
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+ - lib/rggen/verilog/bit_field/type/reserved.rb
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+ - lib/rggen/verilog/bit_field/type/ro.erb
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+ - lib/rggen/verilog/bit_field/type/ro.rb
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+ - lib/rggen/verilog/bit_field/type/rof.erb
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+ - lib/rggen/verilog/bit_field/type/rof.rb
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+ - lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb
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+ - lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb
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+ - lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.erb
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+ - lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb
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+ - lib/rggen/verilog/bit_field/type/rwc.erb
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+ - lib/rggen/verilog/bit_field/type/rwc.rb
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+ - lib/rggen/verilog/bit_field/type/rwe.erb
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+ - lib/rggen/verilog/bit_field/type/rwe.rb
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+ - lib/rggen/verilog/bit_field/type/rwl.erb
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+ - lib/rggen/verilog/bit_field/type/rwl.rb
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+ - lib/rggen/verilog/bit_field/type/rws.erb
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+ - lib/rggen/verilog/bit_field/type/rws.rb
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+ - lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.erb
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+ - lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.rb
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+ - lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.erb
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+ - lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.rb
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+ - lib/rggen/verilog/bit_field/type/w0t_w1t.erb
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+ - lib/rggen/verilog/bit_field/type/w0t_w1t.rb
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+ - lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb
80
+ - lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb
81
+ - lib/rggen/verilog/bit_field/type/wrc_wrs.erb
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+ - lib/rggen/verilog/bit_field/type/wrc_wrs.rb
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+ - lib/rggen/verilog/bit_field/verilog_top.rb
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+ - lib/rggen/verilog/component.rb
85
+ - lib/rggen/verilog/factories.rb
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+ - lib/rggen/verilog/feature.rb
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+ - lib/rggen/verilog/register/type.rb
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+ - lib/rggen/verilog/register/type/default.erb
89
+ - lib/rggen/verilog/register/type/external.erb
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+ - lib/rggen/verilog/register/type/external.rb
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+ - lib/rggen/verilog/register/type/indirect.erb
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+ - lib/rggen/verilog/register/type/indirect.rb
93
+ - lib/rggen/verilog/register/verilog_top.rb
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+ - lib/rggen/verilog/register_block/protocol.rb
95
+ - lib/rggen/verilog/register_block/protocol/apb.erb
96
+ - lib/rggen/verilog/register_block/protocol/apb.rb
97
+ - lib/rggen/verilog/register_block/protocol/axi4lite.erb
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+ - lib/rggen/verilog/register_block/protocol/axi4lite.rb
99
+ - lib/rggen/verilog/register_block/verilog_macros.erb
100
+ - lib/rggen/verilog/register_block/verilog_top.rb
101
+ - lib/rggen/verilog/register_file/verilog_top.rb
102
+ - lib/rggen/verilog/setup.rb
103
+ - lib/rggen/verilog/utility.rb
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+ - lib/rggen/verilog/utility/local_scope.rb
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+ - lib/rggen/verilog/version.rb
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+ homepage: https://github.com/rggen/rggen-verilog
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+ licenses:
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+ - MIT
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+ metadata:
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+ bug_tracker_uri: https://github.com/rggen/rggen-verilog/issues
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+ mailing_list_uri: https://groups.google.com/d/forum/rggen
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+ source_code_uri: https://github.com/rggen/rggen-verilog
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+ wiki_uri: https://github.com/rggen/rggen/wiki
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+ post_install_message:
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+ rdoc_options: []
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+ require_paths:
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+ - lib
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+ required_ruby_version: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - ">="
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+ - !ruby/object:Gem::Version
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+ version: 2.4.0
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+ required_rubygems_version: !ruby/object:Gem::Requirement
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+ requirements:
125
+ - - ">="
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+ - !ruby/object:Gem::Version
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+ version: '0'
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+ requirements: []
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+ rubygems_version: 3.1.2
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+ signing_key:
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+ specification_version: 4
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+ summary: rggen-verilog-0.1.0
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+ test_files: []