rggen-verilog 0.1.0

data/lib/rggen/verilog/bit_field/type/rof.erb

@@ -0,0 +1,11 @@
+rggen_bit_field_ro #(
+  .WIDTH  (<%= width %>)
+) u_bit_field (
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_value                (<%= initial_value %>)
+);

data/lib/rggen/verilog/bit_field/type/rof.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  verilog do
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -0,0 +1,19 @@
+<%= module_name %> #(
+<% if bit_field.type != :rs %>
+  .SET_VALUE      (<%= set_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
+<% end %>
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_clear                (<%= clear[loop_variables] %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -0,0 +1,31 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
+  verilog do
+    build do
+      input :clear, {
+        name: "i_#{full_name}_clear", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def module_name
+      bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
+    end
+
+    def set_value
+      value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.erb

@@ -0,0 +1,16 @@
+rggen_bit_field_rw_wo #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
+  .WRITE_ONCE     (<%= write_once %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def write_only
+      bit_field.write_only? && 1 || 0
+    end
+
+    def write_once
+      [:w1, :wo1].include?(bit_field.type) && 1 || 0
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rwc.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_rwc #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_clear                (<%= clear_signal %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/rwc.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :clear, {
+          name: "i_#{full_name}_clear", width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rwe.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_rwe #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_enable               (<%= enable_signal %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/rwe.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :enable, {
+          name: "i_#{full_name}_enable", width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_signal
+      reference_bit_field || enable[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rwl.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_rwl #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_lock                 (<%= lock_signal %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/rwl.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :lock, {
+          name: "i_#{full_name}_lock", width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def lock_signal
+      reference_bit_field || lock[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rws.erb

@@ -0,0 +1,16 @@
+rggen_bit_field_rws #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_set                  (<%= set_signal %>),
+  .i_value                (<%= value_in[loop_variables] %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/rws.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rws) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :set, {
+          name: "i_#{full_name}_set", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_signal
+      reference_bit_field || set[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_w01crs_wcrs #(
+  .CLEAR_VALUE    (<%= clear_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_value
+      value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_w01src_wsrc #(
+  .SET_VALUE      (<%= set_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_value
+      value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_w01t #(
+  .TOGGLE_VALUE   (<%= toggle_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/w0t_w1t.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def toggle_value
+      bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb

@@ -0,0 +1,14 @@
+rggen_bit_field_w01trg #(
+  .TRIGGER_VALUE  (<%= trigger_value %>),
+  .WIDTH          (<%= width %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .o_trigger              (<%= trigger[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+  verilog do
+    build do
+      output :trigger, {
+        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def trigger_value
+      bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,14 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .o_value                (<%= value_out[loop_variables] %>)
+);