rggen-verilog 0.1.0

data/lib/rggen/verilog/bit_field/type/wrc_wrs.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/verilog/bit_field/verilog_top.rb

@@ -0,0 +1,89 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:bit_field, :verilog_top) do
+  verilog do
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
+    export :initial_value
+    export :value
+
+    build do
+      if parameterized_initial_value?
+        parameter :initial_value, {
+          name: initial_value_name, width: bit_field.width,
+          array_size: initial_value_array_size, default: initial_value_rhs
+        }
+      else
+        define_accessor_for_initial_value
+      end
+    end
+
+    main_code :register do
+      local_scope("g_#{bit_field.name}") do |scope|
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    def value(offsets = nil, width = nil)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
+      value_width = width || bit_field.width
+      register_value(offsets&.slice(0..-2), value_lsb, value_width)
+    end
+
+    private
+
+    def register_value(offsets, lsb, width)
+      index = register.index(offsets || register.local_indices)
+      register_block.register_value[[index], lsb, width]
+    end
+
+    def parameterized_initial_value?
+      bit_field.initial_value? && !bit_field.fixed_initial_value?
+    end
+
+    def define_accessor_for_initial_value
+      define_singleton_method(:initial_value) do
+        bit_field.initial_value? && initial_value_rhs || nil
+      end
+    end
+
+    def initial_value_name
+      "#{bit_field.full_name('_')}_initial_value".upcase
+    end
+
+    def initial_value_array_size
+      bit_field.initial_value_array? && [bit_field.sequence_size] || nil
+    end
+
+    def initial_value_rhs
+      if !bit_field.initial_value_array?
+        sized_initial_value
+      elsif bit_field.fixed_initial_value?
+        concat(sized_initial_values)
+      else
+        repeat(bit_field.sequence_size, sized_initial_value)
+      end
+    end
+
+    def sized_initial_value
+      hex(bit_field.register_map.initial_value, bit_field.width)
+    end
+
+    def sized_initial_values
+      bit_field
+        .initial_values
+        .reverse
+        .map { |v| hex(v, bit_field.width) }
+    end
+
+    def loop_size
+      loop_variable = local_index
+      loop_variable && { loop_variable => bit_field.sequence_size }
+    end
+
+    def body_code(code)
+      bit_field.generate_code(code, :bit_field, :top_down)
+    end
+  end
+end

data/lib/rggen/verilog/component.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    Component = SystemVerilog::Common::Component
+  end
+end

data/lib/rggen/verilog/factories.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    class ComponentFactory < Core::OutputBase::ComponentFactory
+    end
+
+    class FeatureFactory < Core::OutputBase::FeatureFactory
+    end
+  end
+end

data/lib/rggen/verilog/feature.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    class Feature < SystemVerilog::RTL::Feature
+      include Utility
+
+      private
+
+      def create_variable(data_type, attributes, &block)
+        attributes = attributes.merge(array_format: :serialized)
+        super
+      end
+
+      def create_argument(direction, attributes, &block)
+        attributes =
+          attributes
+            .reject { |key, _| key == :data_type }
+            .merge(array_format: :serialized)
+        super
+      end
+
+      def create_parameter(parameter_type, attributes, &block)
+        attributes = attributes.merge(array_format: :serialized)
+        super
+      end
+
+      define_entity :wire, :create_variable, :variable, -> { component }
+
+      undef_method :interface
+      undef_method :interface_port
+      undef_method :localparam
+    end
+  end
+end

data/lib/rggen/verilog/register/type.rb

@@ -0,0 +1,101 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register, :type) do
+  verilog do
+    base_feature do
+      include RgGen::SystemVerilog::RTL::RegisterType
+
+      private
+
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
+      def register_valid
+        register_block.register_valid
+      end
+
+      def register_access
+        register_block.register_access
+      end
+
+      def register_address
+        register_block.register_address
+      end
+
+      def register_write_data
+        register_block.register_write_data
+      end
+
+      def register_strobe
+        register_block.register_strobe
+      end
+
+      def register_active
+        register_block.register_active[[register.index]]
+      end
+
+      def register_ready
+        register_block.register_ready[[register.index]]
+      end
+
+      def register_status
+        register_block.register_status[[register.index]]
+      end
+
+      def register_read_data
+        register_block.register_read_data[[register.index]]
+      end
+
+      def register_value
+        register_block.register_value[[register.index], 0, width]
+      end
+
+      def bit_field_valid
+        register.bit_field_valid
+      end
+
+      def bit_field_read_mask
+        register.bit_field_read_mask
+      end
+
+      def bit_field_write_mask
+        register.bit_field_write_mask
+      end
+
+      def bit_field_write_data
+        register.bit_field_write_data
+      end
+
+      def bit_field_read_data
+        register.bit_field_read_data
+      end
+
+      def bit_field_value
+        register.bit_field_value
+      end
+    end
+
+    default_feature do
+      main_code :register, from_template: File.join(__dir__, 'type', 'default.erb')
+    end
+
+    factory do
+      def target_feature_key(_configuration, register)
+        type = register.type
+        valid_type?(type) && type ||
+          (error "code generator for #{type} register type is not implemented")
+      end
+
+      private
+
+      def valid_type?(type)
+        target_features.key?(type) || type == :default
+      end
+    end
+  end
+end

data/lib/rggen/verilog/register/type/default.erb

@@ -0,0 +1,29 @@
+rggen_default_register #(
+  .READABLE       (<%= readable %>),
+  .WRITABLE       (<%= writable %>),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>),
+  .VALID_BITS     (<%= valid_bits %>),
+  .REGISTER_INDEX (<%= register_index %>)
+) u_register (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_register_valid       (<%= register_valid %>),
+  .i_register_access      (<%= register_access %>),
+  .i_register_address     (<%= register_address %>),
+  .i_register_write_data  (<%= register_write_data %>),
+  .i_register_strobe      (<%= register_strobe %>),
+  .o_register_active      (<%= register_active %>),
+  .o_register_ready       (<%= register_ready %>),
+  .o_register_status      (<%= register_status %>),
+  .o_register_read_data   (<%= register_read_data %>),
+  .o_register_value       (<%= register_value %>),
+  .o_bit_field_valid      (<%= bit_field_valid %>),
+  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .o_bit_field_write_data (<%= bit_field_write_data %>),
+  .i_bit_field_read_data  (<%= bit_field_read_data %>),
+  .i_bit_field_value      (<%= bit_field_value %>)
+);

data/lib/rggen/verilog/register/type/external.erb

@@ -0,0 +1,27 @@
+rggen_external_register #(
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .START_ADDRESS  (<%= start_address %>),
+  .END_ADDRESS    (<%= end_address %>)
+) u_register (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_register_valid       (<%= register_valid %>),
+  .i_register_access      (<%= register_access %>),
+  .i_register_address     (<%= register_address %>),
+  .i_register_write_data  (<%= register_write_data %>),
+  .i_register_strobe      (<%= register_strobe %>),
+  .o_register_active      (<%= register_active %>),
+  .o_register_ready       (<%= register_ready %>),
+  .o_register_status      (<%= register_status %>),
+  .o_register_read_data   (<%= register_read_data %>),
+  .o_register_value       (<%= register_value %>),
+  .o_external_valid       (<%= external_valid %>),
+  .o_external_access      (<%= external_access %>),
+  .o_external_address     (<%= external_address %>),
+  .o_external_data        (<%= external_write_data %>),
+  .o_external_strobe      (<%= external_strobe %>),
+  .i_external_ready       (<%= external_ready %>),
+  .i_external_status      (<%= external_status %>),
+  .i_external_data        (<%= external_read_data %>)
+);

data/lib/rggen/verilog/register/type/external.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :external) do
+  verilog do
+    build do
+      output :external_valid, {
+        name: "o_#{register.name}_valid", width: 1
+      }
+      output :external_access, {
+        name: "o_#{register.name}_access", width: 2
+      }
+      output :external_address, {
+        name: "o_#{register.name}_address", width: address_width
+      }
+      output :external_write_data, {
+        name: "o_#{register.name}_data", width: bus_width
+      }
+      output :external_strobe, {
+        name: "o_#{register.name}_strobe", width: bus_width / 8
+      }
+      input :external_ready, {
+        name: "i_#{register.name}_ready", width: 1
+      }
+      input :external_status, {
+        name: "i_#{register.name}_status", width: 2
+      }
+      input :external_read_data, {
+        name: "i_#{register.name}_data", width: bus_width
+      }
+    end
+
+    main_code :register, from_template: true
+
+    private
+
+    def start_address
+      hex(register.offset_address, address_width)
+    end
+
+    def end_address
+      address = register.offset_address + register.byte_size - 1
+      hex(address, address_width)
+    end
+  end
+end

data/lib/rggen/verilog/register/type/indirect.erb

@@ -0,0 +1,31 @@
+rggen_indirect_register #(
+  .READABLE             (<%= readable %>),
+  .WRITABLE             (<%= writable %>),
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .OFFSET_ADDRESS       (<%= offset_address %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .DATA_WIDTH           (<%= width %>),
+  .VALID_BITS           (<%= valid_bits %>),
+  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
+  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+) u_register (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_register_valid       (<%= register_valid %>),
+  .i_register_access      (<%= register_access %>),
+  .i_register_address     (<%= register_address %>),
+  .i_register_write_data  (<%= register_write_data %>),
+  .i_register_strobe      (<%= register_strobe %>),
+  .o_register_active      (<%= register_active %>),
+  .o_register_ready       (<%= register_ready %>),
+  .o_register_status      (<%= register_status %>),
+  .o_register_read_data   (<%= register_read_data %>),
+  .o_register_value       (<%= register_value %>),
+  .i_indirect_index       (<%= indirect_index %>),
+  .o_bit_field_valid      (<%= bit_field_valid %>),
+  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .o_bit_field_write_data (<%= bit_field_write_data %>),
+  .i_bit_field_read_data  (<%= bit_field_read_data %>),
+  .i_bit_field_value      (<%= bit_field_value %>)
+);

data/lib/rggen/verilog/register/type/indirect.rb

@@ -0,0 +1,18 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :indirect) do
+  verilog do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
+    build do
+      wire :indirect_index, {
+        name: 'w_indirect_index', width: index_width
+      }
+    end
+
+    main_code :register do |code|
+      code << indirect_index_assignment << nl
+      code << process_template
+    end
+  end
+end

data/lib/rggen/verilog/register/verilog_top.rb

@@ -0,0 +1,58 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :verilog_top) do
+  verilog do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    build do
+      unless register.bit_fields.empty?
+        wire :bit_field_valid, {
+          name: 'w_bit_field_valid', width: 1
+        }
+        wire :bit_field_read_mask, {
+          name: 'w_bit_field_read_mask', width: register.width
+        }
+        wire :bit_field_write_mask, {
+          name: 'w_bit_field_write_mask', width: register.width
+        }
+        wire :bit_field_write_data, {
+          name: 'w_bit_field_write_data', width: register.width
+        }
+        wire :bit_field_read_data, {
+          name: 'w_bit_field_read_data', width: register.width
+        }
+        wire :bit_field_value, {
+          name: 'w_bit_field_value', width: register.width
+        }
+      end
+    end
+
+    main_code :register_file do
+      local_scope("g_#{register.name}") do |scope|
+        scope.top_scope top_scope?
+        scope.loop_size loop_size
+        scope.variables variables
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def top_scope?
+      register_file.nil?
+    end
+
+    def loop_size
+      (register.array? || nil) &&
+        local_loop_variables.zip(register.array_size).to_h
+    end
+
+    def variables
+      register.declarations[:variable]
+    end
+
+    def body_code(code)
+      register.generate_code(code, :register, :top_down)
+    end
+  end
+end