rggen-verilog 0.1.0

checksums.yaml

@@ -0,0 +1,7 @@
+---
+SHA256:
+  metadata.gz: 7878131f03a9ff76e36b48e957c86b859c5ae3b7834689728c893d8105ff4be1
+  data.tar.gz: 13af428dc61822e225f563b15ca498605599791e06727bf591cbe977ac796a2c
+SHA512:
+  metadata.gz: df8e7976ebea90a57a0c0214bcf5e0e584fa42a6c45bb4ded678170320c6ecf01b346a1114960358ce179e36f25524b704d317d3ac75124ab2a2fa50a617b104
+  data.tar.gz: c6373a81a9a1affe34d8c2b7c1f933d34d9e4a88df93937bc735cb91df44625eaf456cf9c130888641173942afa52c27d62edcdb3342d8efe2fc241ce4b46af8

data/CODE_OF_CONDUCT.md

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+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+In the interest of fostering an open and welcoming environment, we as
+contributors and maintainers pledge to making participation in our project and
+our community a harassment-free experience for everyone, regardless of age, body
+size, disability, ethnicity, gender identity and expression, level of experience,
+nationality, personal appearance, race, religion, or sexual identity and
+orientation.
+
+## Our Standards
+
+Examples of behavior that contributes to creating a positive environment
+include:
+
+* Using welcoming and inclusive language
+* Being respectful of differing viewpoints and experiences
+* Gracefully accepting constructive criticism
+* Focusing on what is best for the community
+* Showing empathy towards other community members
+
+Examples of unacceptable behavior by participants include:
+
+* The use of sexualized language or imagery and unwelcome sexual attention or
+advances
+* Trolling, insulting/derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or electronic
+  address, without explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+## Our Responsibilities
+
+Project maintainers are responsible for clarifying the standards of acceptable
+behavior and are expected to take appropriate and fair corrective action in
+response to any instances of unacceptable behavior.
+
+Project maintainers have the right and responsibility to remove, edit, or
+reject comments, commits, code, wiki edits, issues, and other contributions
+that are not aligned to this Code of Conduct, or to ban temporarily or
+permanently any contributor for other behaviors that they deem inappropriate,
+threatening, offensive, or harmful.
+
+## Scope
+
+This Code of Conduct applies both within project spaces and in public spaces
+when an individual is representing the project or its community. Examples of
+representing a project or community include using an official project e-mail
+address, posting via an official social media account, or acting as an appointed
+representative at an online or offline event. Representation of a project may be
+further defined and clarified by project maintainers.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported by contacting the project team at taichi730@gmail.com. All
+complaints will be reviewed and investigated and will result in a response that
+is deemed necessary and appropriate to the circumstances. The project team is
+obligated to maintain confidentiality with regard to the reporter of an incident.
+Further details of specific enforcement policies may be posted separately.
+
+Project maintainers who do not follow or enforce the Code of Conduct in good
+faith may face temporary or permanent repercussions as determined by other
+members of the project's leadership.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
+available at [https://contributor-covenant.org/version/1/4][version]
+
+[homepage]: https://contributor-covenant.org
+[version]: https://contributor-covenant.org/version/1/4/

data/LICENSE

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+The MIT License (MIT)
+
+Copyright (c) 2020 Taichi Ishitani
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

data/README.md

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+[![Gem Version](https://badge.fury.io/rb/rggen-verilog.svg)](https://badge.fury.io/rb/rggen-verilog)
+[![CI](https://github.com/rggen/rggen-verilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-verilog/actions?query=workflow%3ACI)
+[![Maintainability](https://api.codeclimate.com/v1/badges/7a4090f4a7c21d29036c/maintainability)](https://codeclimate.com/github/rggen/rggen-verilog/maintainability)
+[![codecov](https://codecov.io/gh/rggen/rggen-verilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-verilog)
+[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
+
+# RgGen::Verilog
+
+RgGen::Verilog is a RgGen plugin to generate RTL written in Verilog.
+
+## Installation
+
+To install RgGen::Verilog, use the following command:
+
+```
+$ gem install rggen-verilog
+```
+
+## Usage
+
+You need to tell RgGen to load RgGen::Verilog plugin. There are two ways.
+
+### Using `--plugin` runtime option
+
+```
+$ rggen --plugin rggen-verilog your_register_map.yml
+```
+
+### Using `RGGEN_PLUGINS` environment variable
+
+```
+$ export RGGEN_PLUGINS=${RGGEN_PLUGINS}:rggen-verilog
+$ rggen your_register_map.yml
+```
+
+## Using Generated RTL
+
+Generated RTL files are constructed by using common Verilog modules.
+You need to get them from GitHub repository and set an environment variable to show their location.
+
+* GitHub repository
+    * https://github.com/rggen/rggen-verilog-rtl.git
+* Environment Variable
+    * RGGEN_VERILOG_RTL_ROOT
+
+```
+$ git clone https://github.com/rggen/rggen-verilog-rtl.git
+$ export RGGEN_VERILOG_RTL_ROOT=`pwd`/rggen-verilog-rtl
+```
+
+Then, you can use generated RTL files with your deisgn. This is an example command.
+
+```
+$ simulator \
+    -f ${RGGEN_VERILOG_RTL_ROOT}/compile.f
+    your_csr_0.v your_csr_1.v your_design.v
+```
+
+## Contact
+
+Feedbacks, bus reports, questions and etc. are welcome! You can post them bu using following ways:
+
+* [GitHub Issue Tracker](https://github.com/rggen/rggen-verilog/issues)
+* [Chat Room](https://gitter.im/rggen/rggen)
+* [Mailing List](https://groups.google.com/d/forum/rggen)
+* [Mail](mailto:rggen@googlegroups.com)
+
+## Copyright & License
+
+Copyright © 2020 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+
+## Code of Conduct
+
+Everyone interacting in the RgGen::Verilog project's codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen-verilog/blob/master/CODE_OF_CONDUCT.md).

data/lib/rggen/verilog.rb

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+# frozen_string_literal: true
+
+require 'rggen/systemverilog/rtl'
+require_relative 'verilog/version'
+require_relative 'verilog/utility/local_scope'
+require_relative 'verilog/utility'
+require_relative 'verilog/component'
+require_relative 'verilog/feature'
+require_relative 'verilog/factories'
+
+module RgGen
+  module Verilog
+    PLUGIN_NAME = :'rggen-verilog'
+
+    FEATURES = [
+      'verilog/bit_field/type',
+      'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
+      'verilog/bit_field/type/reserved',
+      'verilog/bit_field/type/ro',
+      'verilog/bit_field/type/rof',
+      'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
+      'verilog/bit_field/type/rw_w1_wo_wo1',
+      'verilog/bit_field/type/rwc',
+      'verilog/bit_field/type/rwe',
+      'verilog/bit_field/type/rwl',
+      'verilog/bit_field/type/rws',
+      'verilog/bit_field/type/w0crs_w1crs_wcrs',
+      'verilog/bit_field/type/w0src_w1src_wsrc',
+      'verilog/bit_field/type/w0t_w1t',
+      'verilog/bit_field/type/w0trg_w1trg',
+      'verilog/bit_field/type/wrc_wrs',
+      'verilog/bit_field/verilog_top',
+      'verilog/register/type',
+      'verilog/register/type/external',
+      'verilog/register/type/indirect',
+      'verilog/register/verilog_top',
+      'verilog/register_block/protocol',
+      'verilog/register_block/protocol/apb',
+      'verilog/register_block/protocol/axi4lite',
+      'verilog/register_block/verilog_top',
+      'verilog/register_file/verilog_top'
+    ].freeze
+
+    def self.register_component(builder)
+      builder.output_component_registry(:verilog) do
+        register_component [
+          :root, :register_block, :register_file, :register, :bit_field
+        ] do |layer|
+          component Component, ComponentFactory
+          feature Feature, FeatureFactory if layer != :root
+        end
+      end
+    end
+
+    def self.load_features
+      FEATURES.each { |feature| require_relative feature }
+    end
+
+    def self.default_setup(builder)
+      register_component(builder)
+      load_features
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_feature(:bit_field, :type) do
+  verilog do
+    base_feature do
+      private
+
+      def full_name
+        bit_field.full_name('_')
+      end
+
+      def lsb
+        bit_field.lsb(bit_field.local_index)
+      end
+
+      def width
+        bit_field.width
+      end
+
+      def array_size
+        bit_field.array_size
+      end
+
+      def initial_value
+        index = bit_field.initial_value_array? && bit_field.local_index || 0
+        macro_call('rggen_slice', [bit_field.initial_value, width, index])
+      end
+
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
+      def bit_field_valid
+        register.bit_field_valid
+      end
+
+      def bit_field_read_mask
+        register.bit_field_read_mask[lsb, width]
+      end
+
+      def bit_field_write_mask
+        register.bit_field_write_mask[lsb, width]
+      end
+
+      def bit_field_write_data
+        register.bit_field_write_data[lsb, width]
+      end
+
+      def bit_field_read_data
+        register.bit_field_read_data[lsb, width]
+      end
+
+      def bit_field_value
+        register.bit_field_value[lsb, width]
+      end
+
+      def mask
+        reference_bit_field || hex(2**width - 1, width)
+      end
+
+      def reference_bit_field
+        bit_field.reference? &&
+          bit_field
+            .find_reference(register_block.bit_fields)
+            .value(bit_field.local_indices, bit_field.reference_width)
+      end
+
+      def loop_variables
+        bit_field.loop_variables
+      end
+    end
+
+    factory do
+      def target_feature_key(_configuration, bit_field)
+        type = bit_field.type
+        target_features.key?(type) && type ||
+          (error "code generator for #{type} bit field type is not implemented")
+      end
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb

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+<%= module_name %> #(
+<% if bit_field.type != :rc %>
+  .CLEAR_VALUE    (<%= clear_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
+<% end %>
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset%>),
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_set                  (<%= set[loop_variables] %>),
+  .i_mask                 (<%= mask %>),
+  .o_value                (<%= value_out[loop_variables] %>),
+  .o_value_unmasked       (<%= value_out_unmasked %>)
+);

data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
+  verilog do
+    build do
+      input :set, {
+        name: "i_#{full_name}_set", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      if bit_field.reference?
+        output :value_unmasked, {
+          name: "o_#{full_name}_unmasked", width: width, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def module_name
+      bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
+    end
+
+    def clear_value
+      value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
+    end
+
+    def value_out_unmasked
+      (bit_field.reference? || nil) && value_unmasked[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/reserved.erb

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+rggen_bit_field_reserved #(
+  .WIDTH  (<%= width %>)
+) u_bit_field (
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>)
+);

data/lib/rggen/verilog/bit_field/type/reserved.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
+  verilog do
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/verilog/bit_field/type/ro.erb

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+rggen_bit_field_ro #(
+  .WIDTH  (<%= width %>)
+) u_bit_field (
+  .i_bit_field_valid      (<%= bit_field_valid %>),
+  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .i_bit_field_write_data (<%= bit_field_write_data %>),
+  .o_bit_field_read_data  (<%= bit_field_read_data %>),
+  .o_bit_field_value      (<%= bit_field_value %>),
+  .i_value                (<%= reference_or_value_in %>)
+);

data/lib/rggen/verilog/bit_field/type/ro.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :ro) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def reference_or_value_in
+      bit_field.reference? && reference_bit_field || value_in[loop_variables]
+    end
+  end
+end