rggen-verilog 0.1.0

data/lib/rggen/verilog/register_block/protocol.rb

@@ -0,0 +1,51 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register_block, :protocol) do
+  verilog do
+    shared_context.feature_registry(registry)
+
+    base_feature do
+      build do
+        parameter :address_width, {
+          name: 'ADDRESS_WIDTH', default: local_address_width
+        }
+        parameter :pre_decode, {
+          name: 'PRE_DECODE', default: 0
+        }
+        parameter :base_address, {
+          name: 'BASE_ADDRESS', width: address_width, default: 0
+        }
+        parameter :error_status, {
+          name: 'ERROR_STATUS', default: 0
+        }
+        parameter :default_read_data, {
+          name: 'DEFAULT_READ_DATA', width: bus_width, default: 0
+        }
+      end
+
+      private
+
+      def bus_width
+        configuration.bus_width
+      end
+
+      def local_address_width
+        register_block.local_address_width
+      end
+
+      def total_registers
+        register_block.files_and_registers.sum(&:count)
+      end
+
+      def byte_size
+        register_block.byte_size
+      end
+    end
+
+    factory do
+      def target_feature_key(configuration, _register_block)
+        configuration.protocol
+      end
+    end
+  end
+end

data/lib/rggen/verilog/register_block/protocol/apb.erb

@@ -0,0 +1,33 @@
+rggen_apb_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>)
+) u_adapter (
+  .i_clk                  (<%= register_block.clock %>),
+  .i_rst_n                (<%= register_block.reset %>),
+  .i_psel                 (<%= psel %>),
+  .i_penable              (<%= penable %>),
+  .i_paddr                (<%= paddr %>),
+  .i_pprot                (<%= pprot %>),
+  .i_pwrite               (<%= pwrite %>),
+  .i_pstrb                (<%= pstrb %>),
+  .i_pwdata               (<%= pwdata %>),
+  .o_pready               (<%= pready %>),
+  .o_prdata               (<%= prdata %>),
+  .o_pslverr              (<%= pslverr %>),
+  .o_register_valid       (<%= register_block.register_valid %>),
+  .o_register_access      (<%= register_block.register_access %>),
+  .o_register_address     (<%= register_block.register_address %>),
+  .o_register_write_data  (<%= register_block.register_write_data %>),
+  .o_register_strobe      (<%= register_block.register_strobe %>),
+  .i_register_active      (<%= register_block.register_active %>),
+  .i_register_ready       (<%= register_block.register_ready %>),
+  .i_register_status      (<%= register_block.register_status %>),
+  .i_register_read_data   (<%= register_block.register_read_data %>)
+);

data/lib/rggen/verilog/register_block/protocol/apb.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
+  verilog do
+    build do
+      input :psel, {
+        name: 'i_psel', width: 1
+      }
+      input :penable, {
+        name: 'i_penable', width: 1
+      }
+      input :paddr, {
+        name: 'i_paddr', width: address_width
+      }
+      input :pprot, {
+        name: 'i_pprot', width: 3
+      }
+      input :pwrite, {
+        name: 'i_pwrite', width: 1
+      }
+      input :pstrb, {
+        name: 'i_pstrb', width: bus_width / 8
+      }
+      input :pwdata, {
+        name: 'i_pwdata', width: bus_width
+      }
+      output :pready, {
+        name: 'o_pready', width: 1
+      }
+      output :prdata, {
+        name: 'o_prdata', width: bus_width
+      }
+      output :pslverr, {
+        name: 'o_pslverr', width: 1
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/verilog/register_block/protocol/axi4lite.erb

@@ -0,0 +1,48 @@
+rggen_axi4lite_adapter #(
+  .ID_WIDTH             (<%= id_width %>),
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .WRITE_FIRST          (<%= write_first %>)
+) u_adapter (
+  .i_clk                  (<%= register_block.clock %>),
+  .i_rst_n                (<%= register_block.reset %>),
+  .i_awvalid              (<%= awvalid %>),
+  .o_awready              (<%= awready %>),
+  .i_awid                 (<%= awid %>),
+  .i_awaddr               (<%= awaddr %>),
+  .i_awprot               (<%= awprot %>),
+  .i_wvalid               (<%= wvalid %>),
+  .o_wready               (<%= wready %>),
+  .i_wdata                (<%= wdata %>),
+  .i_wstrb                (<%= wstrb %>),
+  .o_bvalid               (<%= bvalid %>),
+  .i_bready               (<%= bready %>),
+  .o_bid                  (<%= bid %>),
+  .o_bresp                (<%= bresp %>),
+  .i_arvalid              (<%= arvalid %>),
+  .o_arready              (<%= arready %>),
+  .i_arid                 (<%= arid %>),
+  .i_araddr               (<%= araddr %>),
+  .i_arprot               (<%= arprot %>),
+  .o_rvalid               (<%= rvalid %>),
+  .i_rready               (<%= rready %>),
+  .o_rid                  (<%= rid %>),
+  .o_rdata                (<%= rdata %>),
+  .o_rresp                (<%= rresp %>),
+  .o_register_valid       (<%= register_block.register_valid %>),
+  .o_register_access      (<%= register_block.register_access %>),
+  .o_register_address     (<%= register_block.register_address %>),
+  .o_register_write_data  (<%= register_block.register_write_data %>),
+  .o_register_strobe      (<%= register_block.register_strobe %>),
+  .i_register_active      (<%= register_block.register_active %>),
+  .i_register_ready       (<%= register_block.register_ready %>),
+  .i_register_status      (<%= register_block.register_status %>),
+  .i_register_read_data   (<%= register_block.register_read_data %>)
+);

data/lib/rggen/verilog/register_block/protocol/axi4lite.rb

@@ -0,0 +1,92 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
+  verilog do
+    build do
+      parameter :id_width, {
+        name: 'ID_WIDTH', default: 0
+      }
+      parameter :write_first, {
+        name: 'WRITE_FIRST', default: 1
+      }
+
+      input :awvalid, {
+        name: 'i_awvalid', width: 1
+      }
+      output :awready, {
+        name: 'o_awready', width: 1
+      }
+      input :awid, {
+        name: 'i_awid', width: id_width_value
+      }
+      input :awaddr, {
+        name: 'i_awaddr', width: address_width
+      }
+      input :awprot, {
+        name: 'i_awprot', width: 3
+      }
+      input :wvalid, {
+        name: 'i_wvalid', width: 1
+      }
+      output :wready, {
+        name: 'o_wready', width: 1
+      }
+      input :wdata, {
+        name: 'i_wdata', width: bus_width
+      }
+      input :wstrb, {
+        name: 'i_wstrb', width: bus_width / 8
+      }
+      output :bvalid, {
+        name: 'o_bvalid', width: 1
+      }
+      input :bready, {
+        name: 'i_bready', width: 1
+      }
+      output :bid, {
+        name: 'o_bid', width: id_width_value
+      }
+      output :bresp, {
+        name: 'o_bresp', width: 2
+      }
+      input :arvalid, {
+        name: 'i_arvalid', width: 1
+      }
+      output :arready, {
+        name: 'o_arready', width: 1
+      }
+      input :arid, {
+        name: 'i_arid', width: id_width_value
+      }
+      input :araddr, {
+        name: 'i_araddr', width: address_width
+      }
+      input :arprot, {
+        name: 'i_arprot', width: 3
+      }
+      output :rvalid, {
+        name: 'o_rvalid', width: 1
+      }
+      input :rready, {
+        name: 'i_rready', width: 1
+      }
+      output :rid, {
+        name: 'o_rid', width: id_width_value
+      }
+      output :rdata, {
+        name: 'o_rdata', width: bus_width
+      }
+      output :rresp, {
+        name: 'o_rresp', width: 2
+      }
+    end
+
+    main_code :register_block, from_template: true
+
+    private
+
+    def id_width_value
+      "((#{id_width} == 0) ? 1 : #{id_width})"
+    end
+  end
+end

data/lib/rggen/verilog/register_block/verilog_macros.erb

@@ -0,0 +1,4 @@
+`ifndef rggen_slice
+  `define rggen_slice(EXPRESSION, WIDTH, INDEX) \
+  (((EXPRESSION) >> ((WIDTH) * (INDEX))) & {(WIDTH){1'b1}})
+`endif

data/lib/rggen/verilog/register_block/verilog_top.rb

@@ -0,0 +1,104 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :verilog_top) do
+  verilog do
+    build do
+      input :clock, {
+        name: 'i_clk', width: 1
+      }
+      input :reset, {
+        name: 'i_rst_n', width: 1
+      }
+
+      wire :register_valid, {
+        name: 'w_register_valid', width: 1
+      }
+      wire :register_access, {
+        name: 'w_register_access', width: 2
+      }
+      wire :register_address, {
+        name: 'w_register_address', width: address_width
+      }
+      wire :register_write_data, {
+        name: 'w_register_write_data', width: bus_width
+      }
+      wire :register_strobe, {
+        name: 'w_register_strobe', width: bus_width / 8
+      }
+      wire :register_active, {
+        name: 'w_register_active', width: 1, array_size: [total_registers]
+      }
+      wire :register_ready, {
+        name: 'w_register_ready', width: 1, array_size: [total_registers]
+      }
+      wire :register_status, {
+        name: 'w_register_status', width: 2, array_size: [total_registers]
+      }
+      wire :register_read_data, {
+        name: 'w_register_read_data', width: bus_width, array_size: [total_registers]
+      }
+      wire :register_value, {
+        name: 'w_register_value', width: value_width, array_size: [total_registers]
+      }
+    end
+
+    write_file '<%= register_block.name %>.v' do |file|
+      file.body(&method(:body_code))
+    end
+
+    private
+
+    def total_registers
+      register_block.files_and_registers.sum(&:count)
+    end
+
+    def address_width
+      register_block.local_address_width
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+
+    def value_width
+      register_block.registers.map(&:width).max
+    end
+
+    def body_code(code)
+      macro_definition(code)
+      verilog_module_definition(code)
+    end
+
+    def macro_definition(code)
+      template_path = File.join(__dir__, 'verilog_macros.erb')
+      code << process_template(template_path)
+    end
+
+    def verilog_module_definition(code)
+      code << module_definition(register_block.name) do |verilog_module|
+        verilog_module.parameters parameters
+        verilog_module.ports ports
+        verilog_module.variables variables
+        verilog_module.body(&method(:verilog_module_body))
+      end
+    end
+
+    def parameters
+      register_block.declarations[:parameter]
+    end
+
+    def ports
+      register_block.declarations[:port]
+    end
+
+    def variables
+      register_block.declarations[:variable]
+    end
+
+    def verilog_module_body(code)
+      { register_block: nil, register_file: 1 }.each do |kind, depth|
+        register_block.generate_code(code, kind, :top_down, depth)
+      end
+    end
+  end
+end

data/lib/rggen/verilog/register_file/verilog_top.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :verilog_top) do
+  verilog do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    main_code :register_file do
+      local_scope("g_#{register_file.name}") do |scope|
+        scope.top_scope top_scope?
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def top_scope?
+      register_file(:upper).nil?
+    end
+
+    def loop_size
+      (register_file.array? || nil) &&
+        local_loop_variables.zip(register_file.array_size).to_h
+    end
+
+    def body_code(code)
+      register_file.generate_code(code, :register_file, :top_down, 1)
+    end
+  end
+end

data/lib/rggen/verilog/setup.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+require 'rggen/verilog'
+require 'rggen/systemverilog/rtl/setup'
+
+RgGen.setup RgGen::Verilog do |builder|
+  builder.enable :register_block, [:verilog_top]
+  builder.enable :register_file, [:verilog_top]
+  builder.enable :register, [:verilog_top]
+  builder.enable :bit_field, [:verilog_top]
+end

data/lib/rggen/verilog/utility.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module Utility
+      private
+
+      def local_scope(name, attributes = {}, &block)
+        LocalScope.new(attributes.merge(name: name), &block).to_code
+      end
+    end
+  end
+end

data/lib/rggen/verilog/utility/local_scope.rb

@@ -0,0 +1,15 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module Utility
+      class LocalScope < SystemVerilog::Common::Utility::LocalScope
+        private
+
+        def generate_for(genvar, size)
+          "for (#{genvar} = 0;#{genvar} < #{size};#{genvar} = #{genvar} + 1) begin : g"
+        end
+      end
+    end
+  end
+end