rggen-systemverilog 0.11.1 → 0.13.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/README.md +2 -8
- data/lib/rggen/systemverilog.rb +3 -47
- data/lib/rggen/systemverilog/common.rb +44 -0
- data/lib/rggen/systemverilog/common/component.rb +25 -0
- data/lib/rggen/systemverilog/common/factories.rb +13 -0
- data/lib/rggen/systemverilog/common/feature.rb +78 -0
- data/lib/rggen/systemverilog/common/utility.rb +95 -0
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +45 -0
- data/lib/rggen/systemverilog/common/utility/data_object.rb +131 -0
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +47 -0
- data/lib/rggen/systemverilog/common/utility/identifier.rb +114 -0
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +57 -0
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +51 -0
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +64 -0
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +76 -0
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +61 -0
- data/lib/rggen/systemverilog/common/utility/source_file.rb +16 -0
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +39 -0
- data/lib/rggen/systemverilog/ral.rb +38 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +83 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb +23 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb +7 -0
- data/lib/rggen/systemverilog/ral/feature.rb +26 -0
- data/lib/rggen/systemverilog/ral/register/type.rb +154 -0
- data/lib/rggen/systemverilog/ral/register/type/default.erb +8 -0
- data/lib/rggen/systemverilog/ral/register/type/external.rb +27 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +13 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +35 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +11 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +65 -0
- data/lib/rggen/systemverilog/ral/setup.rb +7 -0
- data/lib/rggen/systemverilog/rtl.rb +50 -0
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +89 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +62 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +15 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +59 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +3 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +22 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +13 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +32 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +14 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb +16 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb +61 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +20 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +48 -0
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +19 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +24 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +82 -0
- data/lib/rggen/systemverilog/rtl/register/type.rb +65 -0
- data/lib/rggen/systemverilog/rtl/register/type/default.erb +15 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +91 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +40 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +100 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +10 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +89 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +125 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +9 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +86 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +13 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +70 -20
- data/lib/rggen/systemverilog/component.rb +0 -23
- data/lib/rggen/systemverilog/factories.rb +0 -11
- data/lib/rggen/systemverilog/feature.rb +0 -76
- data/lib/rggen/systemverilog/feature_ral.rb +0 -24
- data/lib/rggen/systemverilog/feature_rtl.rb +0 -46
- data/lib/rggen/systemverilog/utility.rb +0 -93
- data/lib/rggen/systemverilog/utility/class_definition.rb +0 -43
- data/lib/rggen/systemverilog/utility/data_object.rb +0 -129
- data/lib/rggen/systemverilog/utility/function_definition.rb +0 -45
- data/lib/rggen/systemverilog/utility/identifier.rb +0 -112
- data/lib/rggen/systemverilog/utility/interface_instance.rb +0 -55
- data/lib/rggen/systemverilog/utility/interface_port.rb +0 -49
- data/lib/rggen/systemverilog/utility/local_scope.rb +0 -62
- data/lib/rggen/systemverilog/utility/module_definition.rb +0 -74
- data/lib/rggen/systemverilog/utility/package_definition.rb +0 -59
- data/lib/rggen/systemverilog/utility/source_file.rb +0 -14
- data/lib/rggen/systemverilog/utility/structure_definition.rb +0 -37
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 8a3623823355599396aefd51ff1e23199edeadb01ec6a9c5a41e4c96795bd415
|
4
|
+
data.tar.gz: 9d64e7ed55d00af43bec20af3277fbc4236bb8c3a4839291de9c2e4ded5657ba
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: c4c9f664b3d0232e088126bc6d5a564cae08526960fa0c2ce53fea558487695e0585d9339548c22a2842d14b1caf1148f8a99c2bc069e1ffa0a817b81adaa765
|
7
|
+
data.tar.gz: aab9d80c62650db7bbae7ffe799aa3330cae974be7adecad9615e400576d472aa9e89ba043c653baa5c1d4aceb4d38b5677d8f996adbd6d1b191956f282ede6c
|
data/README.md
CHANGED
@@ -1,5 +1,5 @@
|
|
1
1
|
[![Gem Version](https://badge.fury.io/rb/rggen-systemverilog.svg)](https://badge.fury.io/rb/rggen-systemverilog)
|
2
|
-
[![Build Status](https://travis-ci.
|
2
|
+
[![Build Status](https://travis-ci.com/rggen/rggen-systemverilog.svg?branch=master)](https://travis-ci.com/rggen/rggen-systemverilog)
|
3
3
|
[![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
|
4
4
|
[![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
|
5
5
|
[![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
|
@@ -7,13 +7,7 @@
|
|
7
7
|
|
8
8
|
# RgGen::SystemVerilog
|
9
9
|
|
10
|
-
RgGen::SystemVerilog
|
11
|
-
|
12
|
-
* Structure for defining SystemVerilog RTL and UVM RAL model writers
|
13
|
-
* Convenience APIs for SystemVerilog code
|
14
|
-
* Declaring signals, ports and variables
|
15
|
-
* Generating code to define module, class and package
|
16
|
-
* Etc.
|
10
|
+
RgGen::SystemVerilog privides SystemVerilog RTL generator and UVM RAL model generator for RgGen.
|
17
11
|
|
18
12
|
## Installation
|
19
13
|
|
data/lib/rggen/systemverilog.rb
CHANGED
@@ -1,49 +1,5 @@
|
|
1
1
|
# frozen_string_literal: true
|
2
2
|
|
3
|
-
|
4
|
-
|
5
|
-
|
6
|
-
require_relative 'systemverilog/version'
|
7
|
-
|
8
|
-
require_relative 'systemverilog/utility/identifier'
|
9
|
-
require_relative 'systemverilog/utility/data_object'
|
10
|
-
require_relative 'systemverilog/utility/interface_port'
|
11
|
-
require_relative 'systemverilog/utility/interface_instance'
|
12
|
-
require_relative 'systemverilog/utility/structure_definition'
|
13
|
-
require_relative 'systemverilog/utility/class_definition'
|
14
|
-
require_relative 'systemverilog/utility/function_definition'
|
15
|
-
require_relative 'systemverilog/utility/local_scope'
|
16
|
-
require_relative 'systemverilog/utility/module_definition'
|
17
|
-
require_relative 'systemverilog/utility/package_definition'
|
18
|
-
require_relative 'systemverilog/utility/source_file'
|
19
|
-
require_relative 'systemverilog/utility'
|
20
|
-
|
21
|
-
require_relative 'systemverilog/component'
|
22
|
-
require_relative 'systemverilog/feature'
|
23
|
-
require_relative 'systemverilog/feature_rtl'
|
24
|
-
require_relative 'systemverilog/feature_ral'
|
25
|
-
require_relative 'systemverilog/factories'
|
26
|
-
|
27
|
-
module RgGen
|
28
|
-
module SystemVerilog
|
29
|
-
class << self
|
30
|
-
def setup_sv_component(builder, name, sv_feature)
|
31
|
-
builder.output_component_registry(name) do
|
32
|
-
register_component [
|
33
|
-
:register_map, :register_block, :register, :bit_field
|
34
|
-
] do |category|
|
35
|
-
component Component, ComponentFactory
|
36
|
-
feature sv_feature, FeatureFactory if category != :register_map
|
37
|
-
end
|
38
|
-
end
|
39
|
-
end
|
40
|
-
|
41
|
-
def setup(builder)
|
42
|
-
setup_sv_component(builder, :sv_rtl, FeatureRTL)
|
43
|
-
setup_sv_component(builder, :sv_ral, FeatureRAL)
|
44
|
-
end
|
45
|
-
end
|
46
|
-
end
|
47
|
-
|
48
|
-
setup :systemverilog, SystemVerilog
|
49
|
-
end
|
3
|
+
require_relative 'systemverilog/common'
|
4
|
+
require_relative 'systemverilog/rtl'
|
5
|
+
require_relative 'systemverilog/ral'
|
@@ -0,0 +1,44 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
require 'docile'
|
4
|
+
require 'facets/kernel/attr_singleton'
|
5
|
+
|
6
|
+
require_relative 'version'
|
7
|
+
|
8
|
+
require_relative 'common/utility/identifier'
|
9
|
+
require_relative 'common/utility/data_object'
|
10
|
+
require_relative 'common/utility/interface_instance'
|
11
|
+
require_relative 'common/utility/interface_port'
|
12
|
+
require_relative 'common/utility/structure_definition'
|
13
|
+
require_relative 'common/utility/class_definition'
|
14
|
+
require_relative 'common/utility/function_definition'
|
15
|
+
require_relative 'common/utility/local_scope'
|
16
|
+
require_relative 'common/utility/module_definition'
|
17
|
+
require_relative 'common/utility/package_definition'
|
18
|
+
require_relative 'common/utility/source_file'
|
19
|
+
require_relative 'common/utility'
|
20
|
+
|
21
|
+
require_relative 'common/component'
|
22
|
+
require_relative 'common/feature'
|
23
|
+
require_relative 'common/factories'
|
24
|
+
|
25
|
+
module RgGen
|
26
|
+
module SystemVerilog
|
27
|
+
module Common
|
28
|
+
def self.register_component(builder, name, feature_class)
|
29
|
+
builder.output_component_registry(name) do
|
30
|
+
register_component [
|
31
|
+
:register_map, :register_block, :register, :bit_field
|
32
|
+
] do |category|
|
33
|
+
component Component, ComponentFactory
|
34
|
+
feature feature_class, FeatureFactory if category != :register_map
|
35
|
+
end
|
36
|
+
end
|
37
|
+
end
|
38
|
+
|
39
|
+
def self.load_features(features, root)
|
40
|
+
features.each { |feature| require File.join(root, feature) }
|
41
|
+
end
|
42
|
+
end
|
43
|
+
end
|
44
|
+
end
|
@@ -0,0 +1,25 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
class Component < Core::OutputBase::Component
|
7
|
+
def declarations(domain, type)
|
8
|
+
body = ->(r) { r.declarations(domain, type) }
|
9
|
+
[
|
10
|
+
@features.each_value.map(&body),
|
11
|
+
@children.map(&body)
|
12
|
+
].flatten
|
13
|
+
end
|
14
|
+
|
15
|
+
def package_imports(domain)
|
16
|
+
body = ->(r) { r.package_imports(domain) }
|
17
|
+
[
|
18
|
+
@features.each_value.map(&body),
|
19
|
+
@children.map(&body)
|
20
|
+
].flatten.uniq
|
21
|
+
end
|
22
|
+
end
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
@@ -0,0 +1,78 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
class Feature < Core::OutputBase::Feature
|
7
|
+
include Common::Utility
|
8
|
+
template_engine Core::OutputBase::ERBEngine
|
9
|
+
|
10
|
+
EntityContext =
|
11
|
+
Struct.new(:entity_type, :creation_method, :declaration_type)
|
12
|
+
|
13
|
+
class << self
|
14
|
+
private
|
15
|
+
|
16
|
+
def define_entity(entity_type, creation_method, declaration_type)
|
17
|
+
context =
|
18
|
+
EntityContext.new(entity_type, creation_method, declaration_type)
|
19
|
+
define_method(entity_type) do |domain, name, **attributes, &block|
|
20
|
+
entity =
|
21
|
+
create_entity(context, { name: name }.merge(attributes), block)
|
22
|
+
add_entity(entity, context, domain, name)
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
|
27
|
+
def declarations(domain, type)
|
28
|
+
@declarations[domain][type]
|
29
|
+
end
|
30
|
+
|
31
|
+
def package_imports(domain)
|
32
|
+
@package_imports[domain]
|
33
|
+
end
|
34
|
+
|
35
|
+
private
|
36
|
+
|
37
|
+
def post_initialize
|
38
|
+
super
|
39
|
+
@declarations = Hash.new do |h0, k0|
|
40
|
+
h0[k0] = Hash.new { |h1, k1| h1[k1] = [] }
|
41
|
+
end
|
42
|
+
@package_imports = Hash.new { |h, k| h[k] = [] }
|
43
|
+
end
|
44
|
+
|
45
|
+
def create_entity(context, attributes, block)
|
46
|
+
creation_method = context.creation_method
|
47
|
+
entity_type = context.entity_type
|
48
|
+
__send__(creation_method, entity_type, attributes, block)
|
49
|
+
end
|
50
|
+
|
51
|
+
def add_entity(entity, context, domain, name)
|
52
|
+
add_declaration(context, domain, entity.declaration)
|
53
|
+
add_identifier(name, entity.identifier)
|
54
|
+
end
|
55
|
+
|
56
|
+
def add_declaration(context, domain, declaration)
|
57
|
+
declaration_type = context.declaration_type
|
58
|
+
@declarations[domain][declaration_type] << declaration
|
59
|
+
end
|
60
|
+
|
61
|
+
def add_identifier(name, identifier)
|
62
|
+
instance_variable_set("@#{name}", identifier)
|
63
|
+
attr_singleton_reader(name)
|
64
|
+
export(name)
|
65
|
+
end
|
66
|
+
|
67
|
+
def import_package(domain, package)
|
68
|
+
@package_imports[domain].include?(package) ||
|
69
|
+
(@package_imports[domain] << package)
|
70
|
+
end
|
71
|
+
|
72
|
+
def import_packages(domain, packages)
|
73
|
+
Array(packages).each { |package| import_package(domain, package) }
|
74
|
+
end
|
75
|
+
end
|
76
|
+
end
|
77
|
+
end
|
78
|
+
end
|
@@ -0,0 +1,95 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
include Core::Utility::CodeUtility
|
8
|
+
|
9
|
+
def create_blank_file(path)
|
10
|
+
SourceFile.new(path)
|
11
|
+
end
|
12
|
+
|
13
|
+
private
|
14
|
+
|
15
|
+
def create_identifier(name)
|
16
|
+
Identifier.new(name)
|
17
|
+
end
|
18
|
+
|
19
|
+
def assign(lhs, rhs)
|
20
|
+
"assign #{lhs} = #{rhs};"
|
21
|
+
end
|
22
|
+
|
23
|
+
def concat(expressions)
|
24
|
+
"{#{Array(expressions).join(', ')}}"
|
25
|
+
end
|
26
|
+
|
27
|
+
def array(expressions)
|
28
|
+
"'#{concat(expressions)}"
|
29
|
+
end
|
30
|
+
|
31
|
+
def function_call(name, expressions = nil)
|
32
|
+
"#{name}(#{Array(expressions).join(', ')})"
|
33
|
+
end
|
34
|
+
|
35
|
+
def macro_call(name, expressions = nil)
|
36
|
+
if (expression_array = Array(expressions)).empty?
|
37
|
+
"`#{name}"
|
38
|
+
else
|
39
|
+
"`#{name}(#{expression_array.join(', ')})"
|
40
|
+
end
|
41
|
+
end
|
42
|
+
|
43
|
+
def bin(value, width = nil)
|
44
|
+
if width
|
45
|
+
width = bit_width(value, width)
|
46
|
+
format("%d'b%0*b", width, width, value)
|
47
|
+
else
|
48
|
+
format("'b%b", value)
|
49
|
+
end
|
50
|
+
end
|
51
|
+
|
52
|
+
def dec(value, width = nil)
|
53
|
+
if width
|
54
|
+
width = bit_width(value, width)
|
55
|
+
format("%0d'd%d", width, value)
|
56
|
+
else
|
57
|
+
format("'d%d", value)
|
58
|
+
end
|
59
|
+
end
|
60
|
+
|
61
|
+
def hex(value, width = nil)
|
62
|
+
if width
|
63
|
+
width = bit_width(value, width)
|
64
|
+
print_width = (width + 3) / 4
|
65
|
+
format("%0d'h%0*x", width, print_width, value)
|
66
|
+
else
|
67
|
+
format("'h%x", value)
|
68
|
+
end
|
69
|
+
end
|
70
|
+
|
71
|
+
def bit_width(value, width)
|
72
|
+
bit_length = value.bit_length
|
73
|
+
bit_length = 1 if bit_length.zero?
|
74
|
+
[width, bit_length].max
|
75
|
+
end
|
76
|
+
|
77
|
+
def argument(name, **attribute)
|
78
|
+
DataObject.new(:argument, attribute.merge(name: name)).declaration
|
79
|
+
end
|
80
|
+
|
81
|
+
{
|
82
|
+
class_definition: ClassDefinition,
|
83
|
+
function_definition: FunctionDefinition,
|
84
|
+
local_scope: LocalScope,
|
85
|
+
module_definition: ModuleDefinition,
|
86
|
+
package_definition: PackageDefinition
|
87
|
+
}.each do |method_name, definition|
|
88
|
+
define_method(method_name) do |name, **attributes, &block|
|
89
|
+
definition.new(attributes.merge(name: name), &block).to_code
|
90
|
+
end
|
91
|
+
end
|
92
|
+
end
|
93
|
+
end
|
94
|
+
end
|
95
|
+
end
|
@@ -0,0 +1,45 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class ClassDefinition < StructureDefinition
|
8
|
+
define_attribute :name
|
9
|
+
define_attribute :base
|
10
|
+
define_attribute :parameters
|
11
|
+
define_attribute :variables
|
12
|
+
|
13
|
+
private
|
14
|
+
|
15
|
+
def header_code(code)
|
16
|
+
code << [:class, space, name]
|
17
|
+
parameter_declarations(code)
|
18
|
+
class_inheritance(code)
|
19
|
+
code << semicolon
|
20
|
+
end
|
21
|
+
|
22
|
+
def parameter_declarations(code)
|
23
|
+
declarations = Array(parameters)
|
24
|
+
declarations.empty? || wrap(code << space, '#(', ')') do
|
25
|
+
add_declarations_to_header(code, declarations)
|
26
|
+
end
|
27
|
+
end
|
28
|
+
|
29
|
+
def class_inheritance(code)
|
30
|
+
return unless base
|
31
|
+
code << [space, :extends, space, base]
|
32
|
+
end
|
33
|
+
|
34
|
+
def pre_body_code(code)
|
35
|
+
add_declarations_to_body(code, Array(variables))
|
36
|
+
end
|
37
|
+
|
38
|
+
def footer_code
|
39
|
+
:endclass
|
40
|
+
end
|
41
|
+
end
|
42
|
+
end
|
43
|
+
end
|
44
|
+
end
|
45
|
+
end
|
@@ -0,0 +1,131 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class DataObject
|
8
|
+
include Core::Utility::AttributeSetter
|
9
|
+
|
10
|
+
def initialize(object_type, **default_attributes)
|
11
|
+
@object_type = object_type
|
12
|
+
apply_attributes(default_attributes)
|
13
|
+
block_given? && yield(self)
|
14
|
+
end
|
15
|
+
|
16
|
+
define_attribute :name
|
17
|
+
define_attribute :direction
|
18
|
+
define_attribute :parameter_type
|
19
|
+
define_attribute :data_type
|
20
|
+
define_attribute :width
|
21
|
+
define_attribute :array_size
|
22
|
+
define_attribute :array_format, :packed
|
23
|
+
define_attribute :random
|
24
|
+
define_attribute :default
|
25
|
+
|
26
|
+
def declaration
|
27
|
+
declaration_snippets
|
28
|
+
.select(&:itself)
|
29
|
+
.reject(&:empty?)
|
30
|
+
.join(' ')
|
31
|
+
end
|
32
|
+
|
33
|
+
def identifier
|
34
|
+
Identifier.new(name) do |identifier|
|
35
|
+
identifier.__width__(width)
|
36
|
+
identifier.__array_size__(array_size)
|
37
|
+
identifier.__array_format__(array_format)
|
38
|
+
end
|
39
|
+
end
|
40
|
+
|
41
|
+
private
|
42
|
+
|
43
|
+
def declaration_snippets
|
44
|
+
[
|
45
|
+
rand_keyword,
|
46
|
+
argument_direction,
|
47
|
+
paraemter_keyword,
|
48
|
+
data_type,
|
49
|
+
packed_dimensions,
|
50
|
+
object_identifier,
|
51
|
+
default_value
|
52
|
+
]
|
53
|
+
end
|
54
|
+
|
55
|
+
def rand_keyword
|
56
|
+
return unless @object_type == :variable
|
57
|
+
return unless random
|
58
|
+
return :rand if random.equal?(true)
|
59
|
+
random
|
60
|
+
end
|
61
|
+
|
62
|
+
def argument_direction
|
63
|
+
@object_type == :argument && direction
|
64
|
+
end
|
65
|
+
|
66
|
+
def paraemter_keyword
|
67
|
+
@object_type == :parameter && parameter_type
|
68
|
+
end
|
69
|
+
|
70
|
+
def packed_dimensions
|
71
|
+
(serialized? ? serialized_array_size : packed_array_size)
|
72
|
+
.map { |size| "[#{msb(size)}:0]" }
|
73
|
+
.join
|
74
|
+
end
|
75
|
+
|
76
|
+
def msb(size)
|
77
|
+
(size.is_a?(Integer) && size - 1) || "#{size}-1"
|
78
|
+
end
|
79
|
+
|
80
|
+
def array?
|
81
|
+
return false unless array_size
|
82
|
+
!array_size.empty?
|
83
|
+
end
|
84
|
+
|
85
|
+
def serialized?
|
86
|
+
array? && array_format == :serialized
|
87
|
+
end
|
88
|
+
|
89
|
+
def serialized_array_size
|
90
|
+
size = [(width || 1), *array_size]
|
91
|
+
if size.all? { |s| s.is_a?(Integer) }
|
92
|
+
[size.inject(&:*)]
|
93
|
+
else
|
94
|
+
[size.join('*')]
|
95
|
+
end
|
96
|
+
end
|
97
|
+
|
98
|
+
def packed_array_size
|
99
|
+
size = []
|
100
|
+
size.concat(Array(array_size)) if array_format == :packed
|
101
|
+
size << width if valid_width?
|
102
|
+
size
|
103
|
+
end
|
104
|
+
|
105
|
+
def valid_width?
|
106
|
+
return false unless width
|
107
|
+
return true unless width.is_a?(Integer)
|
108
|
+
width > 1
|
109
|
+
end
|
110
|
+
|
111
|
+
def object_identifier
|
112
|
+
"#{name}#{unpacked_dimensions}"
|
113
|
+
end
|
114
|
+
|
115
|
+
def unpacked_array?
|
116
|
+
array? && array_format == :unpacked
|
117
|
+
end
|
118
|
+
|
119
|
+
def unpacked_dimensions
|
120
|
+
return unless unpacked_array?
|
121
|
+
array_size.map { |size| "[#{size}]" }.join
|
122
|
+
end
|
123
|
+
|
124
|
+
def default_value
|
125
|
+
default && "= #{default}"
|
126
|
+
end
|
127
|
+
end
|
128
|
+
end
|
129
|
+
end
|
130
|
+
end
|
131
|
+
end
|