rggen-systemverilog 0.11.1 → 0.13.0

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Files changed (89) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +2 -8
  3. data/lib/rggen/systemverilog.rb +3 -47
  4. data/lib/rggen/systemverilog/common.rb +44 -0
  5. data/lib/rggen/systemverilog/common/component.rb +25 -0
  6. data/lib/rggen/systemverilog/common/factories.rb +13 -0
  7. data/lib/rggen/systemverilog/common/feature.rb +78 -0
  8. data/lib/rggen/systemverilog/common/utility.rb +95 -0
  9. data/lib/rggen/systemverilog/common/utility/class_definition.rb +45 -0
  10. data/lib/rggen/systemverilog/common/utility/data_object.rb +131 -0
  11. data/lib/rggen/systemverilog/common/utility/function_definition.rb +47 -0
  12. data/lib/rggen/systemverilog/common/utility/identifier.rb +114 -0
  13. data/lib/rggen/systemverilog/common/utility/interface_instance.rb +57 -0
  14. data/lib/rggen/systemverilog/common/utility/interface_port.rb +51 -0
  15. data/lib/rggen/systemverilog/common/utility/local_scope.rb +64 -0
  16. data/lib/rggen/systemverilog/common/utility/module_definition.rb +76 -0
  17. data/lib/rggen/systemverilog/common/utility/package_definition.rb +61 -0
  18. data/lib/rggen/systemverilog/common/utility/source_file.rb +16 -0
  19. data/lib/rggen/systemverilog/common/utility/structure_definition.rb +39 -0
  20. data/lib/rggen/systemverilog/ral.rb +38 -0
  21. data/lib/rggen/systemverilog/ral/bit_field/type.rb +83 -0
  22. data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +5 -0
  23. data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb +23 -0
  24. data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb +7 -0
  25. data/lib/rggen/systemverilog/ral/feature.rb +26 -0
  26. data/lib/rggen/systemverilog/ral/register/type.rb +154 -0
  27. data/lib/rggen/systemverilog/ral/register/type/default.erb +8 -0
  28. data/lib/rggen/systemverilog/ral/register/type/external.rb +27 -0
  29. data/lib/rggen/systemverilog/ral/register/type/indirect.erb +13 -0
  30. data/lib/rggen/systemverilog/ral/register/type/indirect.rb +35 -0
  31. data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +11 -0
  32. data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +65 -0
  33. data/lib/rggen/systemverilog/ral/setup.rb +7 -0
  34. data/lib/rggen/systemverilog/rtl.rb +50 -0
  35. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +89 -0
  36. data/lib/rggen/systemverilog/rtl/bit_field/type.rb +62 -0
  37. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +15 -0
  38. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +59 -0
  39. data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +3 -0
  40. data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +7 -0
  41. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +6 -0
  42. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +22 -0
  43. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +6 -0
  44. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb +7 -0
  45. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +13 -0
  46. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +32 -0
  47. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb +9 -0
  48. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +14 -0
  49. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb +16 -0
  50. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb +61 -0
  51. data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +9 -0
  52. data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +20 -0
  53. data/lib/rggen/systemverilog/rtl/feature.rb +48 -0
  54. data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +19 -0
  55. data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +24 -0
  56. data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +82 -0
  57. data/lib/rggen/systemverilog/rtl/register/type.rb +65 -0
  58. data/lib/rggen/systemverilog/rtl/register/type/default.erb +15 -0
  59. data/lib/rggen/systemverilog/rtl/register/type/external.erb +11 -0
  60. data/lib/rggen/systemverilog/rtl/register/type/external.rb +91 -0
  61. data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +17 -0
  62. data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +40 -0
  63. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +100 -0
  64. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +10 -0
  65. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +89 -0
  66. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -0
  67. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +125 -0
  68. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +9 -0
  69. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +86 -0
  70. data/lib/rggen/systemverilog/rtl/setup.rb +13 -0
  71. data/lib/rggen/systemverilog/version.rb +1 -1
  72. metadata +70 -20
  73. data/lib/rggen/systemverilog/component.rb +0 -23
  74. data/lib/rggen/systemverilog/factories.rb +0 -11
  75. data/lib/rggen/systemverilog/feature.rb +0 -76
  76. data/lib/rggen/systemverilog/feature_ral.rb +0 -24
  77. data/lib/rggen/systemverilog/feature_rtl.rb +0 -46
  78. data/lib/rggen/systemverilog/utility.rb +0 -93
  79. data/lib/rggen/systemverilog/utility/class_definition.rb +0 -43
  80. data/lib/rggen/systemverilog/utility/data_object.rb +0 -129
  81. data/lib/rggen/systemverilog/utility/function_definition.rb +0 -45
  82. data/lib/rggen/systemverilog/utility/identifier.rb +0 -112
  83. data/lib/rggen/systemverilog/utility/interface_instance.rb +0 -55
  84. data/lib/rggen/systemverilog/utility/interface_port.rb +0 -49
  85. data/lib/rggen/systemverilog/utility/local_scope.rb +0 -62
  86. data/lib/rggen/systemverilog/utility/module_definition.rb +0 -74
  87. data/lib/rggen/systemverilog/utility/package_definition.rb +0 -59
  88. data/lib/rggen/systemverilog/utility/source_file.rb +0 -14
  89. data/lib/rggen/systemverilog/utility/structure_definition.rb +0 -37
@@ -1,43 +0,0 @@
1
- # frozen_string_literal: true
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-
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- module RgGen
4
- module SystemVerilog
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- module Utility
6
- class ClassDefinition < StructureDefinition
7
- define_attribute :name
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- define_attribute :base
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- define_attribute :parameters
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- define_attribute :variables
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-
12
- private
13
-
14
- def header_code(code)
15
- code << [:class, space, name]
16
- parameter_declarations(code)
17
- class_inheritance(code)
18
- code << semicolon
19
- end
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-
21
- def parameter_declarations(code)
22
- declarations = Array(parameters)
23
- declarations.empty? || wrap(code << space, '#(', ')') do
24
- add_declarations_to_header(code, declarations)
25
- end
26
- end
27
-
28
- def class_inheritance(code)
29
- return unless base
30
- code << [space, :extends, space, base]
31
- end
32
-
33
- def pre_body_code(code)
34
- add_declarations_to_body(code, Array(variables))
35
- end
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-
37
- def footer_code
38
- :endclass
39
- end
40
- end
41
- end
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- end
43
- end
@@ -1,129 +0,0 @@
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- # frozen_string_literal: true
2
-
3
- module RgGen
4
- module SystemVerilog
5
- module Utility
6
- class DataObject
7
- include Core::Utility::AttributeSetter
8
-
9
- def initialize(object_type, **default_attributes)
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- @object_type = object_type
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- apply_attributes(default_attributes)
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- block_given? && yield(self)
13
- end
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-
15
- define_attribute :name
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- define_attribute :direction
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- define_attribute :parameter_type
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- define_attribute :data_type
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- define_attribute :width
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- define_attribute :array_size
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- define_attribute :array_format, :packed
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- define_attribute :random
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- define_attribute :default
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-
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- def declaration
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- declaration_snippets
27
- .select(&:itself)
28
- .reject(&:empty?)
29
- .join(' ')
30
- end
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-
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- def identifier
33
- Identifier.new(name) do |identifier|
34
- identifier.__width__(width)
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- identifier.__array_size__(array_size)
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- identifier.__array_format__(array_format)
37
- end
38
- end
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-
40
- private
41
-
42
- def declaration_snippets
43
- [
44
- rand_keyword,
45
- argument_direction,
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- paraemter_keyword,
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- data_type,
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- packed_dimensions,
49
- object_identifier,
50
- default_value
51
- ]
52
- end
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-
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- def rand_keyword
55
- return unless @object_type == :variable
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- return unless random
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- return :rand if random.equal?(true)
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- random
59
- end
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-
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- def argument_direction
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- @object_type == :argument && direction
63
- end
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-
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- def paraemter_keyword
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- @object_type == :parameter && parameter_type
67
- end
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-
69
- def packed_dimensions
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- (serialized? ? serialized_array_size : packed_array_size)
71
- .map { |size| "[#{msb(size)}:0]" }
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- .join
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- end
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-
75
- def msb(size)
76
- (size.is_a?(Integer) && size - 1) || "#{size}-1"
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- end
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-
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- def array?
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- return false unless array_size
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- !array_size.empty?
82
- end
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-
84
- def serialized?
85
- array? && array_format == :serialized
86
- end
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-
88
- def serialized_array_size
89
- size = [(width || 1), *array_size]
90
- if size.all? { |s| s.is_a?(Integer) }
91
- [size.inject(&:*)]
92
- else
93
- [size.join('*')]
94
- end
95
- end
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-
97
- def packed_array_size
98
- size = []
99
- size.concat(Array(array_size)) if array_format == :packed
100
- size << width if valid_width?
101
- size
102
- end
103
-
104
- def valid_width?
105
- return false unless width
106
- return true unless width.is_a?(Integer)
107
- width > 1
108
- end
109
-
110
- def object_identifier
111
- "#{name}#{unpacked_dimensions}"
112
- end
113
-
114
- def unpacked_array?
115
- array? && array_format == :unpacked
116
- end
117
-
118
- def unpacked_dimensions
119
- return unless unpacked_array?
120
- array_size.map { |size| "[#{size}]" }.join
121
- end
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-
123
- def default_value
124
- default && "= #{default}"
125
- end
126
- end
127
- end
128
- end
129
- end
@@ -1,45 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module RgGen
4
- module SystemVerilog
5
- module Utility
6
- class FunctionDefinition < StructureDefinition
7
- define_attribute :name
8
- define_attribute :return_type
9
- define_attribute :arguments
10
-
11
- def return_type(**attributes)
12
- attributes.size.zero? || (
13
- @return_type = DataObject.new(:variable, **attributes)
14
- )
15
- @return_type
16
- end
17
-
18
- private
19
-
20
- def header_code(code)
21
- code << :function
22
- return_type_declaration(code)
23
- code << [space, name]
24
- argument_declarations(code)
25
- code << semicolon
26
- end
27
-
28
- def return_type_declaration(code)
29
- return unless @return_type
30
- code << [space, return_type.declaration]
31
- end
32
-
33
- def argument_declarations(code)
34
- wrap(code, '(', ')') do
35
- add_declarations_to_header(code, Array(arguments))
36
- end
37
- end
38
-
39
- def footer_code
40
- :endfunction
41
- end
42
- end
43
- end
44
- end
45
- end
@@ -1,112 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module RgGen
4
- module SystemVerilog
5
- module Utility
6
- class Identifier
7
- def initialize(name)
8
- @name = name
9
- block_given? && yield(self)
10
- end
11
-
12
- def __width__(width)
13
- @width = width
14
- end
15
-
16
- def __array_size__(array_size)
17
- @array_size = array_size
18
- end
19
-
20
- def __array_format__(array_format)
21
- @array_format = array_format
22
- end
23
-
24
- def __sub_identifiers__(sub_identifiers)
25
- Array(sub_identifiers).each do |sub_identifier|
26
- (@sub_identifiers ||= []) << sub_identifier
27
- define_singleton_method(sub_identifier) do
28
- Identifier.new("#{@name}.#{__method__}")
29
- end
30
- end
31
- end
32
-
33
- def to_s
34
- @name.to_s
35
- end
36
-
37
- def [](array_index_or_lsb, width = nil)
38
- if array_index_or_lsb
39
- __create_new_identifier__(array_index_or_lsb, width)
40
- else
41
- self
42
- end
43
- end
44
-
45
- private
46
-
47
- def __create_new_identifier__(array_index_or_lsb, width)
48
- select = __create_select__(array_index_or_lsb, width)
49
- Identifier.new("#{@name}#{select}") do |identifier|
50
- identifier.__sub_identifiers__(@sub_identifiers)
51
- end
52
- end
53
-
54
- def __create_select__(array_index_or_lsb, width)
55
- if array_index_or_lsb.is_a?(::Array)
56
- __array_select__(array_index_or_lsb)
57
- elsif width
58
- "[#{array_index_or_lsb}+:#{width}]"
59
- else
60
- "[#{array_index_or_lsb}]"
61
- end
62
- end
63
-
64
- def __array_select__(array_index)
65
- if @array_format == :serialized
66
- "[#{__serialized_lsb__(array_index)}+:#{@width}]"
67
- else
68
- array_index
69
- .map { |index| "[#{index}]" }
70
- .join
71
- end
72
- end
73
-
74
- def __serialized_lsb__(array_index)
75
- __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
76
- end
77
-
78
- def __serialized_index__(array_index)
79
- index_values =
80
- array_index
81
- .reverse
82
- .zip(__index_factors__)
83
- .map { |i, f| __calc_index_value__(i, f) }
84
- index = __reduce_array__(index_values.reverse, :+, 0)
85
- integer?(index) ? index : "(#{index})"
86
- end
87
-
88
- def __index_factors__
89
- Array.new(@array_size.size) do |i|
90
- i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
91
- end
92
- end
93
-
94
- def __calc_index_value__(index, factor)
95
- __reduce_array__([factor, index].compact, :*, 1)
96
- end
97
-
98
- def __reduce_array__(array, operator, initial_value)
99
- if array.all?(&method(:integer?))
100
- array.reduce(initial_value, &operator)
101
- else
102
- array.join(operator.to_s)
103
- end
104
- end
105
-
106
- def integer?(value)
107
- value.is_a?(Integer)
108
- end
109
- end
110
- end
111
- end
112
- end
@@ -1,55 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module RgGen
4
- module SystemVerilog
5
- module Utility
6
- class InterfaceInstance
7
- include Core::Utility::AttributeSetter
8
-
9
- def initialize(**default_attributes)
10
- apply_attributes(default_attributes)
11
- block_given? && yield(self)
12
- end
13
-
14
- define_attribute :name
15
- define_attribute :interface_type
16
- define_attribute :parameter_values
17
- define_attribute :port_connections
18
- define_attribute :array_size
19
- define_attribute :variables
20
-
21
- def instantiation
22
- [
23
- interface_type,
24
- parameter_value_assignments,
25
- instance_identifier
26
- ].select(&:itself).join(' ')
27
- end
28
-
29
- alias_method :declaration, :instantiation
30
-
31
- def identifier
32
- Identifier.new(name) do |identifier|
33
- identifier.__array_size__(array_size)
34
- identifier.__sub_identifiers__(variables)
35
- end
36
- end
37
-
38
- private
39
-
40
- def parameter_value_assignments
41
- values = Array(parameter_values)
42
- values.size.positive? && "#(#{values.join(', ')})"
43
- end
44
-
45
- def instance_identifier
46
- [
47
- name,
48
- *Array(array_size).map { |size| "[#{size}]" },
49
- "(#{Array(port_connections).join(', ')})"
50
- ].join
51
- end
52
- end
53
- end
54
- end
55
- end
@@ -1,49 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module RgGen
4
- module SystemVerilog
5
- module Utility
6
- class InterfacePort
7
- include Core::Utility::AttributeSetter
8
-
9
- def initialize(**default_attributes)
10
- apply_attributes(default_attributes)
11
- block_given? && yield(self)
12
- end
13
-
14
- define_attribute :name
15
- define_attribute :interface_type
16
- define_attribute :modport
17
- define_attribute :array_size
18
-
19
- def modport(name, ports = nil)
20
- @modport_name = name
21
- @modport_ports = ports
22
- end
23
-
24
- def declaration
25
- "#{port_type} #{port_identifier}"
26
- end
27
-
28
- def identifier
29
- Identifier.new(name) do |identifier|
30
- identifier.__array_size__(array_size)
31
- identifier.__sub_identifiers__(@modport_ports)
32
- end
33
- end
34
-
35
- private
36
-
37
- def port_type
38
- [@interface_type, @modport_name].compact.join('.')
39
- end
40
-
41
- def port_identifier
42
- [
43
- name, *Array(array_size).map { |size| "[#{size}]" }
44
- ].join
45
- end
46
- end
47
- end
48
- end
49
- end
@@ -1,62 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module RgGen
4
- module SystemVerilog
5
- module Utility
6
- class LocalScope < StructureDefinition
7
- define_attribute :name
8
- define_attribute :variables
9
- define_attribute :loop_size
10
-
11
- def top_scope
12
- @top_scope = true
13
- end
14
-
15
- private
16
-
17
- def header_code(code)
18
- code << [:generate, space] if @top_scope
19
- code << "if (1) begin : #{name}" << nl
20
- end
21
-
22
- def footer_code(code)
23
- code << :end
24
- code << [space, :endgenerate] if @top_scope
25
- end
26
-
27
- def pre_body_code(code)
28
- genvar_declarations(code)
29
- generate_for_header(code)
30
- variable_declarations(code)
31
- end
32
-
33
- def genvar_declarations(code)
34
- genvars = Array(loop_size&.keys).map { |genvar| "genvar #{genvar}" }
35
- add_declarations_to_body(code, genvars)
36
- end
37
-
38
- def generate_for_header(code)
39
- loop_size&.each do |genvar, size|
40
- code << generate_for(genvar, size) << nl
41
- code.indent += 2
42
- end
43
- end
44
-
45
- def generate_for(genvar, size)
46
- "for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
47
- end
48
-
49
- def variable_declarations(code)
50
- add_declarations_to_body(code, Array(variables))
51
- end
52
-
53
- def post_body_code(code)
54
- (loop_size&.size || 0).times do
55
- code.indent -= 2
56
- code << :end << nl
57
- end
58
- end
59
- end
60
- end
61
- end
62
- end