rggen-systemverilog 0.11.1 → 0.13.0
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- checksums.yaml +4 -4
- data/README.md +2 -8
- data/lib/rggen/systemverilog.rb +3 -47
- data/lib/rggen/systemverilog/common.rb +44 -0
- data/lib/rggen/systemverilog/common/component.rb +25 -0
- data/lib/rggen/systemverilog/common/factories.rb +13 -0
- data/lib/rggen/systemverilog/common/feature.rb +78 -0
- data/lib/rggen/systemverilog/common/utility.rb +95 -0
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +45 -0
- data/lib/rggen/systemverilog/common/utility/data_object.rb +131 -0
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +47 -0
- data/lib/rggen/systemverilog/common/utility/identifier.rb +114 -0
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +57 -0
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +51 -0
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +64 -0
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +76 -0
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +61 -0
- data/lib/rggen/systemverilog/common/utility/source_file.rb +16 -0
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +39 -0
- data/lib/rggen/systemverilog/ral.rb +38 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +83 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb +23 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb +7 -0
- data/lib/rggen/systemverilog/ral/feature.rb +26 -0
- data/lib/rggen/systemverilog/ral/register/type.rb +154 -0
- data/lib/rggen/systemverilog/ral/register/type/default.erb +8 -0
- data/lib/rggen/systemverilog/ral/register/type/external.rb +27 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +13 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +35 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +11 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +65 -0
- data/lib/rggen/systemverilog/ral/setup.rb +7 -0
- data/lib/rggen/systemverilog/rtl.rb +50 -0
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +89 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +62 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +15 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +59 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +3 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +22 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +13 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +32 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +14 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb +16 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb +61 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +20 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +48 -0
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +19 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +24 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +82 -0
- data/lib/rggen/systemverilog/rtl/register/type.rb +65 -0
- data/lib/rggen/systemverilog/rtl/register/type/default.erb +15 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +91 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +40 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +100 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +10 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +89 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +125 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +9 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +86 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +13 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +70 -20
- data/lib/rggen/systemverilog/component.rb +0 -23
- data/lib/rggen/systemverilog/factories.rb +0 -11
- data/lib/rggen/systemverilog/feature.rb +0 -76
- data/lib/rggen/systemverilog/feature_ral.rb +0 -24
- data/lib/rggen/systemverilog/feature_rtl.rb +0 -46
- data/lib/rggen/systemverilog/utility.rb +0 -93
- data/lib/rggen/systemverilog/utility/class_definition.rb +0 -43
- data/lib/rggen/systemverilog/utility/data_object.rb +0 -129
- data/lib/rggen/systemverilog/utility/function_definition.rb +0 -45
- data/lib/rggen/systemverilog/utility/identifier.rb +0 -112
- data/lib/rggen/systemverilog/utility/interface_instance.rb +0 -55
- data/lib/rggen/systemverilog/utility/interface_port.rb +0 -49
- data/lib/rggen/systemverilog/utility/local_scope.rb +0 -62
- data/lib/rggen/systemverilog/utility/module_definition.rb +0 -74
- data/lib/rggen/systemverilog/utility/package_definition.rb +0 -59
- data/lib/rggen/systemverilog/utility/source_file.rb +0 -14
- data/lib/rggen/systemverilog/utility/structure_definition.rb +0 -37
@@ -1,43 +0,0 @@
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class ClassDefinition < StructureDefinition
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define_attribute :name
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define_attribute :base
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define_attribute :parameters
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define_attribute :variables
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private
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def header_code(code)
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code << [:class, space, name]
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parameter_declarations(code)
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class_inheritance(code)
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code << semicolon
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end
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def parameter_declarations(code)
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declarations = Array(parameters)
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declarations.empty? || wrap(code << space, '#(', ')') do
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add_declarations_to_header(code, declarations)
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end
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end
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def class_inheritance(code)
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return unless base
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code << [space, :extends, space, base]
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end
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def pre_body_code(code)
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add_declarations_to_body(code, Array(variables))
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end
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def footer_code
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:endclass
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end
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class DataObject
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include Core::Utility::AttributeSetter
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def initialize(object_type, **default_attributes)
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@object_type = object_type
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apply_attributes(default_attributes)
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block_given? && yield(self)
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end
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define_attribute :name
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define_attribute :direction
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define_attribute :parameter_type
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define_attribute :data_type
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define_attribute :width
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define_attribute :array_size
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define_attribute :array_format, :packed
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define_attribute :random
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define_attribute :default
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def declaration
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declaration_snippets
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.select(&:itself)
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.reject(&:empty?)
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.join(' ')
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end
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def identifier
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Identifier.new(name) do |identifier|
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identifier.__width__(width)
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identifier.__array_size__(array_size)
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identifier.__array_format__(array_format)
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end
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end
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private
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def declaration_snippets
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[
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rand_keyword,
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argument_direction,
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paraemter_keyword,
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data_type,
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packed_dimensions,
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object_identifier,
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default_value
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]
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end
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def rand_keyword
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return unless @object_type == :variable
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return unless random
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return :rand if random.equal?(true)
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random
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end
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def argument_direction
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@object_type == :argument && direction
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end
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def paraemter_keyword
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end
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def packed_dimensions
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(serialized? ? serialized_array_size : packed_array_size)
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.map { |size| "[#{msb(size)}:0]" }
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.join
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end
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def msb(size)
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(size.is_a?(Integer) && size - 1) || "#{size}-1"
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end
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def array?
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end
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def serialized?
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array? && array_format == :serialized
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end
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def serialized_array_size
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size = [(width || 1), *array_size]
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if size.all? { |s| s.is_a?(Integer) }
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[size.inject(&:*)]
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else
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[size.join('*')]
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end
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end
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def packed_array_size
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size = []
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size.concat(Array(array_size)) if array_format == :packed
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size << width if valid_width?
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size
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end
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def valid_width?
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return false unless width
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return true unless width.is_a?(Integer)
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width > 1
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end
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def object_identifier
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"#{name}#{unpacked_dimensions}"
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end
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def unpacked_array?
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array? && array_format == :unpacked
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end
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def unpacked_dimensions
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return unless unpacked_array?
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array_size.map { |size| "[#{size}]" }.join
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end
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def default_value
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default && "= #{default}"
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end
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class FunctionDefinition < StructureDefinition
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define_attribute :name
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define_attribute :return_type
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define_attribute :arguments
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def return_type(**attributes)
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attributes.size.zero? || (
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@return_type = DataObject.new(:variable, **attributes)
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)
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@return_type
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end
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private
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def header_code(code)
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code << :function
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return_type_declaration(code)
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code << [space, name]
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argument_declarations(code)
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code << semicolon
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end
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def return_type_declaration(code)
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return unless @return_type
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code << [space, return_type.declaration]
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end
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def argument_declarations(code)
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wrap(code, '(', ')') do
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add_declarations_to_header(code, Array(arguments))
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end
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end
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def footer_code
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:endfunction
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end
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class Identifier
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def initialize(name)
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@name = name
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block_given? && yield(self)
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end
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def __width__(width)
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@width = width
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end
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def __array_size__(array_size)
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@array_size = array_size
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end
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def __array_format__(array_format)
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@array_format = array_format
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end
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def __sub_identifiers__(sub_identifiers)
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Array(sub_identifiers).each do |sub_identifier|
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(@sub_identifiers ||= []) << sub_identifier
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define_singleton_method(sub_identifier) do
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Identifier.new("#{@name}.#{__method__}")
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end
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end
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end
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def to_s
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@name.to_s
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end
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def [](array_index_or_lsb, width = nil)
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if array_index_or_lsb
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__create_new_identifier__(array_index_or_lsb, width)
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else
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self
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end
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end
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private
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def __create_new_identifier__(array_index_or_lsb, width)
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select = __create_select__(array_index_or_lsb, width)
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Identifier.new("#{@name}#{select}") do |identifier|
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identifier.__sub_identifiers__(@sub_identifiers)
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end
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end
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def __create_select__(array_index_or_lsb, width)
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if array_index_or_lsb.is_a?(::Array)
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__array_select__(array_index_or_lsb)
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elsif width
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"[#{array_index_or_lsb}+:#{width}]"
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else
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"[#{array_index_or_lsb}]"
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end
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end
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def __array_select__(array_index)
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if @array_format == :serialized
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"[#{__serialized_lsb__(array_index)}+:#{@width}]"
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else
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array_index
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.map { |index| "[#{index}]" }
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.join
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end
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end
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def __serialized_lsb__(array_index)
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__reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
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end
|
77
|
-
|
78
|
-
def __serialized_index__(array_index)
|
79
|
-
index_values =
|
80
|
-
array_index
|
81
|
-
.reverse
|
82
|
-
.zip(__index_factors__)
|
83
|
-
.map { |i, f| __calc_index_value__(i, f) }
|
84
|
-
index = __reduce_array__(index_values.reverse, :+, 0)
|
85
|
-
integer?(index) ? index : "(#{index})"
|
86
|
-
end
|
87
|
-
|
88
|
-
def __index_factors__
|
89
|
-
Array.new(@array_size.size) do |i|
|
90
|
-
i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
|
91
|
-
end
|
92
|
-
end
|
93
|
-
|
94
|
-
def __calc_index_value__(index, factor)
|
95
|
-
__reduce_array__([factor, index].compact, :*, 1)
|
96
|
-
end
|
97
|
-
|
98
|
-
def __reduce_array__(array, operator, initial_value)
|
99
|
-
if array.all?(&method(:integer?))
|
100
|
-
array.reduce(initial_value, &operator)
|
101
|
-
else
|
102
|
-
array.join(operator.to_s)
|
103
|
-
end
|
104
|
-
end
|
105
|
-
|
106
|
-
def integer?(value)
|
107
|
-
value.is_a?(Integer)
|
108
|
-
end
|
109
|
-
end
|
110
|
-
end
|
111
|
-
end
|
112
|
-
end
|
@@ -1,55 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
module RgGen
|
4
|
-
module SystemVerilog
|
5
|
-
module Utility
|
6
|
-
class InterfaceInstance
|
7
|
-
include Core::Utility::AttributeSetter
|
8
|
-
|
9
|
-
def initialize(**default_attributes)
|
10
|
-
apply_attributes(default_attributes)
|
11
|
-
block_given? && yield(self)
|
12
|
-
end
|
13
|
-
|
14
|
-
define_attribute :name
|
15
|
-
define_attribute :interface_type
|
16
|
-
define_attribute :parameter_values
|
17
|
-
define_attribute :port_connections
|
18
|
-
define_attribute :array_size
|
19
|
-
define_attribute :variables
|
20
|
-
|
21
|
-
def instantiation
|
22
|
-
[
|
23
|
-
interface_type,
|
24
|
-
parameter_value_assignments,
|
25
|
-
instance_identifier
|
26
|
-
].select(&:itself).join(' ')
|
27
|
-
end
|
28
|
-
|
29
|
-
alias_method :declaration, :instantiation
|
30
|
-
|
31
|
-
def identifier
|
32
|
-
Identifier.new(name) do |identifier|
|
33
|
-
identifier.__array_size__(array_size)
|
34
|
-
identifier.__sub_identifiers__(variables)
|
35
|
-
end
|
36
|
-
end
|
37
|
-
|
38
|
-
private
|
39
|
-
|
40
|
-
def parameter_value_assignments
|
41
|
-
values = Array(parameter_values)
|
42
|
-
values.size.positive? && "#(#{values.join(', ')})"
|
43
|
-
end
|
44
|
-
|
45
|
-
def instance_identifier
|
46
|
-
[
|
47
|
-
name,
|
48
|
-
*Array(array_size).map { |size| "[#{size}]" },
|
49
|
-
"(#{Array(port_connections).join(', ')})"
|
50
|
-
].join
|
51
|
-
end
|
52
|
-
end
|
53
|
-
end
|
54
|
-
end
|
55
|
-
end
|
@@ -1,49 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
module RgGen
|
4
|
-
module SystemVerilog
|
5
|
-
module Utility
|
6
|
-
class InterfacePort
|
7
|
-
include Core::Utility::AttributeSetter
|
8
|
-
|
9
|
-
def initialize(**default_attributes)
|
10
|
-
apply_attributes(default_attributes)
|
11
|
-
block_given? && yield(self)
|
12
|
-
end
|
13
|
-
|
14
|
-
define_attribute :name
|
15
|
-
define_attribute :interface_type
|
16
|
-
define_attribute :modport
|
17
|
-
define_attribute :array_size
|
18
|
-
|
19
|
-
def modport(name, ports = nil)
|
20
|
-
@modport_name = name
|
21
|
-
@modport_ports = ports
|
22
|
-
end
|
23
|
-
|
24
|
-
def declaration
|
25
|
-
"#{port_type} #{port_identifier}"
|
26
|
-
end
|
27
|
-
|
28
|
-
def identifier
|
29
|
-
Identifier.new(name) do |identifier|
|
30
|
-
identifier.__array_size__(array_size)
|
31
|
-
identifier.__sub_identifiers__(@modport_ports)
|
32
|
-
end
|
33
|
-
end
|
34
|
-
|
35
|
-
private
|
36
|
-
|
37
|
-
def port_type
|
38
|
-
[@interface_type, @modport_name].compact.join('.')
|
39
|
-
end
|
40
|
-
|
41
|
-
def port_identifier
|
42
|
-
[
|
43
|
-
name, *Array(array_size).map { |size| "[#{size}]" }
|
44
|
-
].join
|
45
|
-
end
|
46
|
-
end
|
47
|
-
end
|
48
|
-
end
|
49
|
-
end
|
@@ -1,62 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
module RgGen
|
4
|
-
module SystemVerilog
|
5
|
-
module Utility
|
6
|
-
class LocalScope < StructureDefinition
|
7
|
-
define_attribute :name
|
8
|
-
define_attribute :variables
|
9
|
-
define_attribute :loop_size
|
10
|
-
|
11
|
-
def top_scope
|
12
|
-
@top_scope = true
|
13
|
-
end
|
14
|
-
|
15
|
-
private
|
16
|
-
|
17
|
-
def header_code(code)
|
18
|
-
code << [:generate, space] if @top_scope
|
19
|
-
code << "if (1) begin : #{name}" << nl
|
20
|
-
end
|
21
|
-
|
22
|
-
def footer_code(code)
|
23
|
-
code << :end
|
24
|
-
code << [space, :endgenerate] if @top_scope
|
25
|
-
end
|
26
|
-
|
27
|
-
def pre_body_code(code)
|
28
|
-
genvar_declarations(code)
|
29
|
-
generate_for_header(code)
|
30
|
-
variable_declarations(code)
|
31
|
-
end
|
32
|
-
|
33
|
-
def genvar_declarations(code)
|
34
|
-
genvars = Array(loop_size&.keys).map { |genvar| "genvar #{genvar}" }
|
35
|
-
add_declarations_to_body(code, genvars)
|
36
|
-
end
|
37
|
-
|
38
|
-
def generate_for_header(code)
|
39
|
-
loop_size&.each do |genvar, size|
|
40
|
-
code << generate_for(genvar, size) << nl
|
41
|
-
code.indent += 2
|
42
|
-
end
|
43
|
-
end
|
44
|
-
|
45
|
-
def generate_for(genvar, size)
|
46
|
-
"for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
|
47
|
-
end
|
48
|
-
|
49
|
-
def variable_declarations(code)
|
50
|
-
add_declarations_to_body(code, Array(variables))
|
51
|
-
end
|
52
|
-
|
53
|
-
def post_body_code(code)
|
54
|
-
(loop_size&.size || 0).times do
|
55
|
-
code.indent -= 2
|
56
|
-
code << :end << nl
|
57
|
-
end
|
58
|
-
end
|
59
|
-
end
|
60
|
-
end
|
61
|
-
end
|
62
|
-
end
|