rggen-systemverilog 0.11.1 → 0.13.0

data/lib/rggen/systemverilog/common/utility/source_file.rb

@@ -0,0 +1,16 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Common
+      module Utility
+        class SourceFile < Core::Utility::CodeUtility::SourceFile
+          ifndef_keyword :'`ifndef'
+          endif_keyword :'`endif'
+          define_keyword :'`define'
+          include_keyword :'`include'
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/common/utility/structure_definition.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Common
+      module Utility
+        class StructureDefinition <
+          Core::Utility::CodeUtility::StructureDefinition
+
+          include Core::Utility::AttributeSetter
+
+          def initialize(**default_attributes, &block)
+            apply_attributes(default_attributes)
+            super(&block)
+          end
+
+          private
+
+          def add_declarations_to_header(code, declarations, terminator = '')
+            declarations.empty? || indent(code, 2) do
+              declarations.each_with_index do |d, i|
+                code <<
+                  if i < (declarations.size - 1)
+                    [d, comma, nl]
+                  else
+                    [d, terminator]
+                  end
+              end
+            end
+          end
+
+          def add_declarations_to_body(code, declarations, terminator = ';')
+            declarations.each { |d| code << d << terminator << nl }
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+require_relative 'common'
+require_relative 'ral/feature'
+
+module RgGen
+  module SystemVerilog
+    module RAL
+      FEATURES = [
+        'ral/bit_field/type',
+        'ral/bit_field/type/reserved_rof',
+        'ral/bit_field/type/rwc_rwe_rwl',
+        'ral/bit_field/type/w0trg_w1trg',
+        'ral/register/type',
+        'ral/register/type/external',
+        'ral/register/type/indirect',
+        'ral/register_block/sv_ral_package'
+      ].freeze
+
+      def self.version
+        SystemVerilog::VERSION
+      end
+
+      def self.register_component(builder)
+        Common.register_component(builder, :sv_ral, Feature)
+      end
+
+      def self.load_features
+        Common.load_features(FEATURES, __dir__)
+      end
+
+      def self.default_setup(builder)
+        register_component(builder)
+        load_features
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -0,0 +1,83 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:bit_field, :type) do
+  sv_ral do
+    base_feature do
+      define_helpers do
+        attr_setter :access
+
+        def model_name(name = nil, &block)
+          @model_name = name || block || @model_name
+          @model_name
+        end
+      end
+
+      export :access
+      export :model_name
+      export :constructors
+
+      build do
+        variable :register, :ral_model, {
+          name: bit_field.name,
+          data_type: model_name,
+          array_size: array_size,
+          random: true
+        }
+      end
+
+      def access
+        (helper.access || bit_field.type).to_s.upcase
+      end
+
+      def model_name
+        if helper.model_name&.is_a?(Proc)
+          instance_eval(&helper.model_name)
+        else
+          helper.model_name || :rggen_ral_field
+        end
+      end
+
+      def constructors
+        (bit_field.sequence_size&.times || [nil]).map do |index|
+          macro_call(
+            :rggen_ral_create_field_model, arguments(index)
+          )
+        end
+      end
+
+      private
+
+      def array_size
+        Array(bit_field.sequence_size)
+      end
+
+      def arguments(index)
+        [
+          ral_model[index], bit_field.lsb(index), bit_field.width,
+          access, volatile, reset_value, valid_reset
+        ]
+      end
+
+      def volatile
+        bit_field.volatile? && 1 || 0
+      end
+
+      def reset_value
+        hex(bit_field.initial_value, bit_field.width)
+      end
+
+      def valid_reset
+        bit_field.initial_value? && 1 || 0
+      end
+    end
+
+    default_feature do
+    end
+
+    factory do
+      def select_feature(_configuration, bit_field)
+        target_features[bit_field.type]
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:reserved, :rof]) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
+  sv_ral { access 'RW' }
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  sv_ral do
+    model_name do
+      "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
+    end
+
+    private
+
+    def reference_names
+      reference = bit_field.reference
+      register = reference&.register
+      [register&.name, reference&.name]
+        .map { |name| string(name) }
+        .join(', ')
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+  sv_ral do
+    model_name { "rggen_ral_#{bit_field.type}_field" }
+  end
+end

data/lib/rggen/systemverilog/ral/feature.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RAL
+      class Feature < Common::Feature
+        private
+
+        def create_variable(_, attributes, block)
+          DataObject.new(
+            :variable, attributes.merge(array_format: :unpacked), &block
+          )
+        end
+
+        def create_parameter(_, attributes, block)
+          DataObject.new(
+            :parameter, attributes, &block
+          )
+        end
+
+        define_entity :variable, :create_variable, :variable
+        define_entity :parameter, :create_parameter, :parameter
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register/type.rb

@@ -0,0 +1,154 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register, :type) do
+  sv_ral do
+    base_feature do
+      define_helpers do
+        def model_name(&body)
+          @model_name = body if block_given?
+          @model_name
+        end
+
+        def offset_address(&body)
+          @offset_address = body if block_given?
+          @offset_address
+        end
+
+        def unmapped
+          @unmapped = true
+        end
+
+        def unmapped?
+          !@unmapped.nil?
+        end
+
+        def constructor(&body)
+          @constructor = body if block_given?
+          @constructor
+        end
+      end
+
+      export :constructors
+
+      build do
+        variable :register_block, :ral_model, {
+          name: register.name,
+          data_type: model_name,
+          array_size: register.array_size,
+          random: true
+        }
+      end
+
+      def constructors
+        (array_index_list || [nil]).map.with_index do |array_index, i|
+          constructor_code(array_index, i)
+        end
+      end
+
+      private
+
+      def model_name
+        if helper.model_name
+          instance_eval(&helper.model_name)
+        else
+          "#{register.name}_reg_model"
+        end
+      end
+
+      def array_index_list
+        (register.array? || nil) &&
+          begin
+            index_table = register.array_size.map { |size| (0...size).to_a }
+            index_table[0].product(*index_table[1..-1])
+          end
+      end
+
+      def constructor_code(array_index, index)
+        if helper.constructor
+          instance_exec(array_index, index, &helper.constructor)
+        else
+          macro_call(
+            :rggen_ral_create_reg_model, arguments(array_index, index)
+          )
+        end
+      end
+
+      def arguments(array_index, index)
+        [
+          ral_model[array_index], array(array_index), offset_address(index),
+          access_rights, unmapped, hdl_path(array_index)
+        ]
+      end
+
+      def offset_address(index = 0)
+        address =
+          if helper.offset_address
+            instance_exec(index, &helper.offset_address)
+          else
+            register.offset_address + register.byte_width * index
+          end
+        hex(address, register_block.local_address_width)
+      end
+
+      def access_rights
+        if read_only?
+          'RO'
+        elsif write_only?
+          'WO'
+        else
+          'RW'
+        end
+      end
+
+      def read_only?
+        !register.writable?
+      end
+
+      def write_only?
+        register.writable? && !register.readable?
+      end
+
+      def unmapped
+        helper.unmapped? && 1 || 0
+      end
+
+      def hdl_path(array_index)
+        [
+          "g_#{register.name}",
+          *Array(array_index).map { |i| "g[#{i}]" },
+          'u_register'
+        ].join('.')
+      end
+
+      def variables
+        register.declarations(:register, :variable)
+      end
+
+      def field_model_constructors
+        register.bit_fields.flat_map(&:constructors)
+      end
+    end
+
+    default_feature do
+      main_code :ral_package do
+        class_definition(model_name) do |sv_class|
+          sv_class.base 'rggen_ral_reg'
+          sv_class.variables variables
+          sv_class.body { model_body }
+        end
+      end
+
+      private
+
+      def model_body
+        process_template(File.join(__dir__, 'type', 'default.erb'))
+      end
+    end
+
+    factory do
+      def select_feature(_configuration, register)
+        target_features[register.type]
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register/type/default.erb

@@ -0,0 +1,8 @@
+function new(string name);
+  super.new(name, <%= register.width%>, 0);
+endfunction
+function void build();
+<% field_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end%>
+endfunction

data/lib/rggen/systemverilog/ral/register/type/external.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :external) do
+  sv_ral do
+    build do
+      parameter :register_block, :model_type, {
+        name: model_name,
+        data_type: 'type',
+        default: 'rggen_ral_block'
+      }
+      parameter :register_block, :integrate_model, {
+        name: "INTEGRATE_#{model_name}",
+        data_type: 'bit',
+        default: 1
+      }
+    end
+
+    model_name { register.name.upcase }
+
+    constructor do
+      macro_call(
+        'rggen_ral_create_block_model',
+        [ral_model, offset_address, 'this', integrate_model]
+      )
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register/type/indirect.erb

@@ -0,0 +1,13 @@
+function new(string name);
+  super.new(name, <%= register.width%>, 0);
+endfunction
+function void build();
+<% field_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end%>
+endfunction
+function void setup_index_fields();
+<% index_properties.each do |reg_name, field_name, value| %>
+  setup_index_field("<%= reg_name %>", "<%= field_name%>", <%= value %>);
+<% end %>
+endfunction