rggen-systemverilog 0.11.1 → 0.13.0
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- checksums.yaml +4 -4
- data/README.md +2 -8
- data/lib/rggen/systemverilog.rb +3 -47
- data/lib/rggen/systemverilog/common.rb +44 -0
- data/lib/rggen/systemverilog/common/component.rb +25 -0
- data/lib/rggen/systemverilog/common/factories.rb +13 -0
- data/lib/rggen/systemverilog/common/feature.rb +78 -0
- data/lib/rggen/systemverilog/common/utility.rb +95 -0
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +45 -0
- data/lib/rggen/systemverilog/common/utility/data_object.rb +131 -0
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +47 -0
- data/lib/rggen/systemverilog/common/utility/identifier.rb +114 -0
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +57 -0
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +51 -0
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +64 -0
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +76 -0
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +61 -0
- data/lib/rggen/systemverilog/common/utility/source_file.rb +16 -0
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +39 -0
- data/lib/rggen/systemverilog/ral.rb +38 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +83 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb +23 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb +7 -0
- data/lib/rggen/systemverilog/ral/feature.rb +26 -0
- data/lib/rggen/systemverilog/ral/register/type.rb +154 -0
- data/lib/rggen/systemverilog/ral/register/type/default.erb +8 -0
- data/lib/rggen/systemverilog/ral/register/type/external.rb +27 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +13 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +35 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +11 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +65 -0
- data/lib/rggen/systemverilog/ral/setup.rb +7 -0
- data/lib/rggen/systemverilog/rtl.rb +50 -0
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +89 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +62 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +15 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +59 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +3 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +22 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +13 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +32 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +14 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb +16 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb +61 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +20 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +48 -0
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +19 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +24 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +82 -0
- data/lib/rggen/systemverilog/rtl/register/type.rb +65 -0
- data/lib/rggen/systemverilog/rtl/register/type/default.erb +15 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +91 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +40 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +100 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +10 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +89 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +125 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +9 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +86 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +13 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +70 -20
- data/lib/rggen/systemverilog/component.rb +0 -23
- data/lib/rggen/systemverilog/factories.rb +0 -11
- data/lib/rggen/systemverilog/feature.rb +0 -76
- data/lib/rggen/systemverilog/feature_ral.rb +0 -24
- data/lib/rggen/systemverilog/feature_rtl.rb +0 -46
- data/lib/rggen/systemverilog/utility.rb +0 -93
- data/lib/rggen/systemverilog/utility/class_definition.rb +0 -43
- data/lib/rggen/systemverilog/utility/data_object.rb +0 -129
- data/lib/rggen/systemverilog/utility/function_definition.rb +0 -45
- data/lib/rggen/systemverilog/utility/identifier.rb +0 -112
- data/lib/rggen/systemverilog/utility/interface_instance.rb +0 -55
- data/lib/rggen/systemverilog/utility/interface_port.rb +0 -49
- data/lib/rggen/systemverilog/utility/local_scope.rb +0 -62
- data/lib/rggen/systemverilog/utility/module_definition.rb +0 -74
- data/lib/rggen/systemverilog/utility/package_definition.rb +0 -59
- data/lib/rggen/systemverilog/utility/source_file.rb +0 -14
- data/lib/rggen/systemverilog/utility/structure_definition.rb +0 -37
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class ModuleDefinition < StructureDefinition
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define_attribute :name
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define_attribute :package_imports
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define_attribute :parameters
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define_attribute :ports
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define_attribute :variables
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def package_imports(packages)
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@package_imports ||= []
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@package_imports.concat(Array(packages))
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end
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def package_import(package)
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package_imports([package])
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end
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private
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def header_code(code)
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code << [:module, space, name]
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package_import_declaration(code)
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parameter_declarations(code)
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port_declarations(code)
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code << semicolon
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end
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def package_import_declaration(code)
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if (items = pacakge_import_items).empty?
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code << space
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return
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end
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add_declarations_to_header(code, items, semicolon)
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end
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def pacakge_import_items
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Array(@package_imports).map.with_index do |package, i|
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if i.zero?
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[:import, "#{package}::*"].join(space)
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else
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[space(6), "#{package}::*"].join(space)
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end
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end
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end
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def parameter_declarations(code)
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declarations = Array(parameters)
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declarations.empty? || wrap(code, '#(', ')') do
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add_declarations_to_header(code, declarations)
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end
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end
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def port_declarations(code)
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declarations = Array(ports)
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wrap(code, '(', ')') do
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add_declarations_to_header(code, declarations)
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end
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end
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def pre_body_code(code)
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add_declarations_to_body(code, Array(variables))
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end
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def footer_code
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:endmodule
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end
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class PackageDefinition < StructureDefinition
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define_attribute :name
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define_attribute :package_imports
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define_attribute :include_files
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def package_imports(packages)
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@package_imports ||= []
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@package_imports.concat(Array(packages))
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end
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def package_import(package)
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package_imports([package])
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end
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def include_files(files)
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@include_files ||= []
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@include_files.concat(Array(files))
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end
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def include_file(file)
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include_files([file])
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end
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private
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def header_code(code)
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code << [:package, space, name, semicolon]
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end
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def pre_body_code(code)
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package_import_declaration(code)
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file_include_directives(code)
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end
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def package_import_declaration(code)
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declarations =
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Array(@package_imports)
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.map { |package| [:import, space, package, '::*'] }
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add_declarations_to_body(code, declarations)
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end
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def file_include_directives(code)
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Array(@include_files).each do |file|
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code << [:'`include', space, string(file), nl]
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end
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end
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def footer_code
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:endpackage
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end
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class SourceFile < Core::Utility::CodeUtility::SourceFile
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ifndef_keyword :'`ifndef'
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endif_keyword :'`endif'
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define_keyword :'`define'
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include_keyword :'`include'
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemVerilog
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module Utility
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class StructureDefinition <
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Core::Utility::CodeUtility::StructureDefinition
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include Core::Utility::AttributeSetter
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def initialize(**default_attributes, &block)
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apply_attributes(default_attributes)
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super(&block)
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end
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private
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def add_declarations_to_header(code, declarations, end_charactor = '')
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declarations.empty? || indent(code, 2) do
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declarations.each_with_index do |d, i|
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code <<
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if i < (declarations.size - 1)
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[d, comma, nl]
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else
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[d, end_charactor]
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end
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end
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end
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end
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def add_declarations_to_body(code, declarations, end_charactor = ';')
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declarations.each { |d| code << d << end_charactor << nl }
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end
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end
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end
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end
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end
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