rggen-systemverilog 0.11.1 → 0.13.0

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -0,0 +1,9 @@
+`ifndef rggen_connect_bit_field_if
+  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
+  assign  FIF.valid                 = RIF.valid; \
+  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
+  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
+  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
+  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
+  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
+`endif

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -0,0 +1,86 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
+  sv_rtl do
+    export :total_registers
+
+    build do
+      input :register_block, :clock, {
+        name: 'i_clk', data_type: :logic, width: 1
+      }
+      input :register_block, :reset, {
+        name: 'i_rst_n', data_type: :logic, width: 1
+      }
+      interface :register_block, :register_if, {
+        name: 'register_if', interface_type: 'rggen_register_if',
+        parameter_values: [address_width, bus_width, value_width],
+        array_size: [total_registers],
+        variables: ['value']
+      }
+    end
+
+    write_file '<%= register_block.name %>.sv' do |file|
+      file.body(&method(:body_code))
+    end
+
+    def total_registers
+      register_block
+        .registers
+        .map(&:count)
+        .inject(:+)
+    end
+
+    private
+
+    def address_width
+      register_block.local_address_width
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+
+    def value_width
+      register_block.registers.map(&:width).max
+    end
+
+    def body_code(code)
+      macro_definition(code)
+      sv_module_definition(code)
+    end
+
+    def macro_definition(code)
+      code << process_template(File.join(__dir__, 'sv_rtl_macros.erb'))
+    end
+
+    def sv_module_definition(code)
+      code << module_definition(register_block.name) do |sv_module|
+        sv_module.package_imports packages
+        sv_module.parameters parameters
+        sv_module.ports ports
+        sv_module.variables variables
+        sv_module.body(&method(:sv_module_body))
+      end
+    end
+
+    def packages
+      ['rggen_rtl_pkg', *register_block.package_imports(:register_block)]
+    end
+
+    def parameters
+      register_block.declarations(:register_block, :parameter)
+    end
+
+    def ports
+      register_block.declarations(:register_block, :port)
+    end
+
+    def variables
+      register_block.declarations(:register_block, :variable)
+    end
+
+    def sv_module_body(code)
+      register_block.generate_code(:register_block, :top_down, code)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+require 'rggen/systemverilog/rtl'
+
+RgGen.setup :'sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+  builder.enable :global, [
+    :array_port_format, :fold_sv_interface_port
+  ]
+  builder.enable :register_block, [:sv_rtl_top, :protocol]
+  builder.enable :register_block, :protocol, [:apb, :axi4lite]
+  builder.enable :register, [:sv_rtl_top]
+  builder.enable :bit_field, [:sv_rtl_top]
+end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.11.1'
+    VERSION = '0.13.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.11.1
+  version: 0.13.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-08-19 00:00:00.000000000 Z
+date: 2019-08-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -65,23 +65,73 @@ files:
 - LICENSE
 - README.md
 - lib/rggen/systemverilog.rb
-- lib/rggen/systemverilog/component.rb
-- lib/rggen/systemverilog/factories.rb
-- lib/rggen/systemverilog/feature.rb
-- lib/rggen/systemverilog/feature_ral.rb
-- lib/rggen/systemverilog/feature_rtl.rb
-- lib/rggen/systemverilog/utility.rb
-- lib/rggen/systemverilog/utility/class_definition.rb
-- lib/rggen/systemverilog/utility/data_object.rb
-- lib/rggen/systemverilog/utility/function_definition.rb
-- lib/rggen/systemverilog/utility/identifier.rb
-- lib/rggen/systemverilog/utility/interface_instance.rb
-- lib/rggen/systemverilog/utility/interface_port.rb
-- lib/rggen/systemverilog/utility/local_scope.rb
-- lib/rggen/systemverilog/utility/module_definition.rb
-- lib/rggen/systemverilog/utility/package_definition.rb
-- lib/rggen/systemverilog/utility/source_file.rb
-- lib/rggen/systemverilog/utility/structure_definition.rb
+- lib/rggen/systemverilog/common.rb
+- lib/rggen/systemverilog/common/component.rb
+- lib/rggen/systemverilog/common/factories.rb
+- lib/rggen/systemverilog/common/feature.rb
+- lib/rggen/systemverilog/common/utility.rb
+- lib/rggen/systemverilog/common/utility/class_definition.rb
+- lib/rggen/systemverilog/common/utility/data_object.rb
+- lib/rggen/systemverilog/common/utility/function_definition.rb
+- lib/rggen/systemverilog/common/utility/identifier.rb
+- lib/rggen/systemverilog/common/utility/interface_instance.rb
+- lib/rggen/systemverilog/common/utility/interface_port.rb
+- lib/rggen/systemverilog/common/utility/local_scope.rb
+- lib/rggen/systemverilog/common/utility/module_definition.rb
+- lib/rggen/systemverilog/common/utility/package_definition.rb
+- lib/rggen/systemverilog/common/utility/source_file.rb
+- lib/rggen/systemverilog/common/utility/structure_definition.rb
+- lib/rggen/systemverilog/ral.rb
+- lib/rggen/systemverilog/ral/bit_field/type.rb
+- lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb
+- lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/ral/feature.rb
+- lib/rggen/systemverilog/ral/register/type.rb
+- lib/rggen/systemverilog/ral/register/type/default.erb
+- lib/rggen/systemverilog/ral/register/type/external.rb
+- lib/rggen/systemverilog/ral/register/type/indirect.erb
+- lib/rggen/systemverilog/ral/register/type/indirect.rb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
+- lib/rggen/systemverilog/ral/setup.rb
+- lib/rggen/systemverilog/rtl.rb
+- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/bit_field/type.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/feature.rb
+- lib/rggen/systemverilog/rtl/global/array_port_format.rb
+- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register/type.rb
+- lib/rggen/systemverilog/rtl/register/type/default.erb
+- lib/rggen/systemverilog/rtl/register/type/external.erb
+- lib/rggen/systemverilog/rtl/register/type/external.rb
+- lib/rggen/systemverilog/rtl/register/type/indirect.erb
+- lib/rggen/systemverilog/rtl/register/type/indirect.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
+- lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
 licenses:
@@ -109,5 +159,5 @@ requirements: []
 rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.11.1
+summary: rggen-systemverilog-0.13.0
 test_files: []

data/lib/rggen/systemverilog/component.rb

@@ -1,23 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module SystemVerilog
-    class Component < Core::OutputBase::Component
-      def declarations(domain, type)
-        body = ->(r) { r.declarations(domain, type) }
-        [
-          @features.each_value.map(&body),
-          @children.map(&body)
-        ].flatten
-      end
-
-      def package_imports(domain)
-        body = ->(r) { r.package_imports(domain) }
-        [
-          @features.each_value.map(&body),
-          @children.map(&body)
-        ].flatten.uniq
-      end
-    end
-  end
-end

data/lib/rggen/systemverilog/factories.rb

@@ -1,11 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module SystemVerilog
-    class ComponentFactory < Core::OutputBase::ComponentFactory
-    end
-
-    class FeatureFactory < Core::OutputBase::FeatureFactory
-    end
-  end
-end

data/lib/rggen/systemverilog/feature.rb

@@ -1,76 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module SystemVerilog
-    class Feature < Core::OutputBase::Feature
-      include Utility
-      template_engine Core::OutputBase::ERBEngine
-
-      EntityContext =
-        Struct.new(:entity_type, :creation_method, :declaration_type)
-
-      class << self
-        private
-
-        def define_entity(entity_type, creation_method, declaration_type)
-          context =
-            EntityContext.new(entity_type, creation_method, declaration_type)
-          define_method(entity_type) do |domain, name, **attributes, &block|
-            entity =
-              create_entity(context, { name: name }.merge(attributes), block)
-            add_entity(entity, context, domain, name)
-          end
-        end
-      end
-
-      def declarations(domain, type)
-        @declarations[domain][type]
-      end
-
-      def package_imports(domain)
-        @package_imports[domain]
-      end
-
-      private
-
-      def post_initialize
-        super
-        @declarations = Hash.new do |h0, k0|
-          h0[k0] = Hash.new { |h1, k1| h1[k1] = [] }
-        end
-        @package_imports = Hash.new { |h, k| h[k] = [] }
-      end
-
-      def create_entity(context, attributes, block)
-        creation_method = context.creation_method
-        entity_type = context.entity_type
-        __send__(creation_method, entity_type, attributes, block)
-      end
-
-      def add_entity(entity, context, domain, name)
-        add_declaration(context, domain, entity.declaration)
-        add_identifier(name, entity.identifier)
-      end
-
-      def add_declaration(context, domain, declaration)
-        declaration_type = context.declaration_type
-        @declarations[domain][declaration_type] << declaration
-      end
-
-      def add_identifier(name, identifier)
-        instance_variable_set("@#{name}", identifier)
-        attr_singleton_reader(name)
-        export(name)
-      end
-
-      def import_package(domain, package)
-        @package_imports[domain].include?(package) ||
-          (@package_imports[domain] << package)
-      end
-
-      def import_packages(domain, packages)
-        Array(packages).each { |package| import_package(domain, package) }
-      end
-    end
-  end
-end

data/lib/rggen/systemverilog/feature_ral.rb

@@ -1,24 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module SystemVerilog
-    class FeatureRAL < Feature
-      private
-
-      def create_variable(_, attributes, block)
-        DataObject.new(
-          :variable, attributes.merge(array_format: :unpacked), &block
-        )
-      end
-
-      def create_parameter(_, attributes, block)
-        DataObject.new(
-          :parameter, attributes, &block
-        )
-      end
-
-      define_entity :variable, :create_variable, :variable
-      define_entity :parameter, :create_parameter, :parameter
-    end
-  end
-end

data/lib/rggen/systemverilog/feature_rtl.rb

@@ -1,46 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module SystemVerilog
-    class FeatureRTL < Feature
-      private
-
-      def create_variable(data_type, attributes, block)
-        DataObject.new(
-          :variable, attributes.merge(data_type: data_type), &block
-        )
-      end
-
-      def create_interface(_, attributes, block)
-        InterfaceInstance.new(attributes, &block)
-      end
-
-      def create_argument(direction, attributes, block)
-        DataObject.new(
-          :argument, attributes.merge(direction: direction), &block
-        )
-      end
-
-      def create_interface_port(_, attributes, block)
-        InterfacePort.new(attributes, &block)
-      end
-
-      def create_parameter(_, attributes, block)
-        DataObject.new(
-          :parameter, attributes.merge(parameter_type: :parameter), &block
-        )
-      end
-
-      [
-        [:logic, :create_variable, :variable],
-        [:interface, :create_interface, :variable],
-        [:input, :create_argument, :port],
-        [:output, :create_argument, :port],
-        [:interface_port, :create_interface_port, :port],
-        [:parameter, :create_parameter, :parameter]
-      ].each do |entity, creation_method, declaration_type|
-        define_entity(entity, creation_method, declaration_type)
-      end
-    end
-  end
-end

data/lib/rggen/systemverilog/utility.rb

@@ -1,93 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module SystemVerilog
-    module Utility
-      include Core::Utility::CodeUtility
-
-      def create_blank_file(path)
-        SourceFile.new(path)
-      end
-
-      private
-
-      def create_identifier(name)
-        Identifier.new(name)
-      end
-
-      def assign(lhs, rhs)
-        "assign #{lhs} = #{rhs};"
-      end
-
-      def concat(expressions)
-        "{#{Array(expressions).join(', ')}}"
-      end
-
-      def array(expressions)
-        "'#{concat(expressions)}"
-      end
-
-      def function_call(name, expressions = nil)
-        "#{name}(#{Array(expressions).join(', ')})"
-      end
-
-      def macro_call(name, expressions = nil)
-        if (expression_array = Array(expressions)).empty?
-          "`#{name}"
-        else
-          "`#{name}(#{expression_array.join(', ')})"
-        end
-      end
-
-      def bin(value, width = nil)
-        if width
-          width = bit_width(value, width)
-          format("%d'b%0*b", width, width, value)
-        else
-          format("'b%b", value)
-        end
-      end
-
-      def dec(value, width = nil)
-        if width
-          width = bit_width(value, width)
-          format("%0d'd%d", width, value)
-        else
-          format("'d%d", value)
-        end
-      end
-
-      def hex(value, width = nil)
-        if width
-          width = bit_width(value, width)
-          print_width = (width + 3) / 4
-          format("%0d'h%0*x", width, print_width, value)
-        else
-          format("'h%x", value)
-        end
-      end
-
-      def bit_width(value, width)
-        bit_length = value.bit_length
-        bit_length = 1 if bit_length.zero?
-        [width, bit_length].max
-      end
-
-      def argument(name, **attribute)
-        DataObject.new(:argument, attribute.merge(name: name)).declaration
-      end
-
-      {
-        class_definition: ClassDefinition,
-        function_definition: FunctionDefinition,
-        local_scope: LocalScope,
-        module_definition: ModuleDefinition,
-        package_definition: PackageDefinition
-      }.each do |method_name, definition|
-        define_method(method_name) do |name, **attributes, &block|
-          definition.new(attributes.merge(name: name), &block).to_code
-        end
-      end
-    end
-  end
-end