rggen-systemverilog 0.11.1 → 0.13.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/README.md +2 -8
- data/lib/rggen/systemverilog.rb +3 -47
- data/lib/rggen/systemverilog/common.rb +44 -0
- data/lib/rggen/systemverilog/common/component.rb +25 -0
- data/lib/rggen/systemverilog/common/factories.rb +13 -0
- data/lib/rggen/systemverilog/common/feature.rb +78 -0
- data/lib/rggen/systemverilog/common/utility.rb +95 -0
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +45 -0
- data/lib/rggen/systemverilog/common/utility/data_object.rb +131 -0
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +47 -0
- data/lib/rggen/systemverilog/common/utility/identifier.rb +114 -0
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +57 -0
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +51 -0
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +64 -0
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +76 -0
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +61 -0
- data/lib/rggen/systemverilog/common/utility/source_file.rb +16 -0
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +39 -0
- data/lib/rggen/systemverilog/ral.rb +38 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +83 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb +23 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb +7 -0
- data/lib/rggen/systemverilog/ral/feature.rb +26 -0
- data/lib/rggen/systemverilog/ral/register/type.rb +154 -0
- data/lib/rggen/systemverilog/ral/register/type/default.erb +8 -0
- data/lib/rggen/systemverilog/ral/register/type/external.rb +27 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +13 -0
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +35 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +11 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +65 -0
- data/lib/rggen/systemverilog/ral/setup.rb +7 -0
- data/lib/rggen/systemverilog/rtl.rb +50 -0
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +89 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +62 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +15 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +59 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +3 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +22 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +6 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb +7 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +13 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +32 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +14 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb +16 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb +61 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +9 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +20 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +48 -0
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +19 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +24 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +82 -0
- data/lib/rggen/systemverilog/rtl/register/type.rb +65 -0
- data/lib/rggen/systemverilog/rtl/register/type/default.erb +15 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +91 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +40 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +100 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +10 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +89 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +125 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +9 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +86 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +13 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +70 -20
- data/lib/rggen/systemverilog/component.rb +0 -23
- data/lib/rggen/systemverilog/factories.rb +0 -11
- data/lib/rggen/systemverilog/feature.rb +0 -76
- data/lib/rggen/systemverilog/feature_ral.rb +0 -24
- data/lib/rggen/systemverilog/feature_rtl.rb +0 -46
- data/lib/rggen/systemverilog/utility.rb +0 -93
- data/lib/rggen/systemverilog/utility/class_definition.rb +0 -43
- data/lib/rggen/systemverilog/utility/data_object.rb +0 -129
- data/lib/rggen/systemverilog/utility/function_definition.rb +0 -45
- data/lib/rggen/systemverilog/utility/identifier.rb +0 -112
- data/lib/rggen/systemverilog/utility/interface_instance.rb +0 -55
- data/lib/rggen/systemverilog/utility/interface_port.rb +0 -49
- data/lib/rggen/systemverilog/utility/local_scope.rb +0 -62
- data/lib/rggen/systemverilog/utility/module_definition.rb +0 -74
- data/lib/rggen/systemverilog/utility/package_definition.rb +0 -59
- data/lib/rggen/systemverilog/utility/source_file.rb +0 -14
- data/lib/rggen/systemverilog/utility/structure_definition.rb +0 -37
@@ -0,0 +1,47 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class FunctionDefinition < StructureDefinition
|
8
|
+
define_attribute :name
|
9
|
+
define_attribute :return_type
|
10
|
+
define_attribute :arguments
|
11
|
+
|
12
|
+
def return_type(**attributes)
|
13
|
+
attributes.size.zero? || (
|
14
|
+
@return_type = DataObject.new(:variable, **attributes)
|
15
|
+
)
|
16
|
+
@return_type
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def header_code(code)
|
22
|
+
code << :function
|
23
|
+
return_type_declaration(code)
|
24
|
+
code << [space, name]
|
25
|
+
argument_declarations(code)
|
26
|
+
code << semicolon
|
27
|
+
end
|
28
|
+
|
29
|
+
def return_type_declaration(code)
|
30
|
+
return unless @return_type
|
31
|
+
code << [space, return_type.declaration]
|
32
|
+
end
|
33
|
+
|
34
|
+
def argument_declarations(code)
|
35
|
+
wrap(code, '(', ')') do
|
36
|
+
add_declarations_to_header(code, Array(arguments))
|
37
|
+
end
|
38
|
+
end
|
39
|
+
|
40
|
+
def footer_code
|
41
|
+
:endfunction
|
42
|
+
end
|
43
|
+
end
|
44
|
+
end
|
45
|
+
end
|
46
|
+
end
|
47
|
+
end
|
@@ -0,0 +1,114 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class Identifier
|
8
|
+
def initialize(name)
|
9
|
+
@name = name
|
10
|
+
block_given? && yield(self)
|
11
|
+
end
|
12
|
+
|
13
|
+
def __width__(width)
|
14
|
+
@width = width
|
15
|
+
end
|
16
|
+
|
17
|
+
def __array_size__(array_size)
|
18
|
+
@array_size = array_size
|
19
|
+
end
|
20
|
+
|
21
|
+
def __array_format__(array_format)
|
22
|
+
@array_format = array_format
|
23
|
+
end
|
24
|
+
|
25
|
+
def __sub_identifiers__(sub_identifiers)
|
26
|
+
Array(sub_identifiers).each do |sub_identifier|
|
27
|
+
(@sub_identifiers ||= []) << sub_identifier
|
28
|
+
define_singleton_method(sub_identifier) do
|
29
|
+
Identifier.new("#{@name}.#{__method__}")
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
|
34
|
+
def to_s
|
35
|
+
@name.to_s
|
36
|
+
end
|
37
|
+
|
38
|
+
def [](array_index_or_lsb, width = nil)
|
39
|
+
if array_index_or_lsb
|
40
|
+
__create_new_identifier__(array_index_or_lsb, width)
|
41
|
+
else
|
42
|
+
self
|
43
|
+
end
|
44
|
+
end
|
45
|
+
|
46
|
+
private
|
47
|
+
|
48
|
+
def __create_new_identifier__(array_index_or_lsb, width)
|
49
|
+
select = __create_select__(array_index_or_lsb, width)
|
50
|
+
Identifier.new("#{@name}#{select}") do |identifier|
|
51
|
+
identifier.__sub_identifiers__(@sub_identifiers)
|
52
|
+
end
|
53
|
+
end
|
54
|
+
|
55
|
+
def __create_select__(array_index_or_lsb, width)
|
56
|
+
if array_index_or_lsb.is_a?(::Array)
|
57
|
+
__array_select__(array_index_or_lsb)
|
58
|
+
elsif width
|
59
|
+
"[#{array_index_or_lsb}+:#{width}]"
|
60
|
+
else
|
61
|
+
"[#{array_index_or_lsb}]"
|
62
|
+
end
|
63
|
+
end
|
64
|
+
|
65
|
+
def __array_select__(array_index)
|
66
|
+
if @array_format == :serialized
|
67
|
+
"[#{__serialized_lsb__(array_index)}+:#{@width}]"
|
68
|
+
else
|
69
|
+
array_index
|
70
|
+
.map { |index| "[#{index}]" }
|
71
|
+
.join
|
72
|
+
end
|
73
|
+
end
|
74
|
+
|
75
|
+
def __serialized_lsb__(array_index)
|
76
|
+
__reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
|
77
|
+
end
|
78
|
+
|
79
|
+
def __serialized_index__(array_index)
|
80
|
+
index_values =
|
81
|
+
array_index
|
82
|
+
.reverse
|
83
|
+
.zip(__index_factors__)
|
84
|
+
.map { |i, f| __calc_index_value__(i, f) }
|
85
|
+
index = __reduce_array__(index_values.reverse, :+, 0)
|
86
|
+
integer?(index) ? index : "(#{index})"
|
87
|
+
end
|
88
|
+
|
89
|
+
def __index_factors__
|
90
|
+
Array.new(@array_size.size) do |i|
|
91
|
+
i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
|
92
|
+
end
|
93
|
+
end
|
94
|
+
|
95
|
+
def __calc_index_value__(index, factor)
|
96
|
+
__reduce_array__([factor, index].compact, :*, 1)
|
97
|
+
end
|
98
|
+
|
99
|
+
def __reduce_array__(array, operator, initial_value)
|
100
|
+
if array.all?(&method(:integer?))
|
101
|
+
array.reduce(initial_value, &operator)
|
102
|
+
else
|
103
|
+
array.join(operator.to_s)
|
104
|
+
end
|
105
|
+
end
|
106
|
+
|
107
|
+
def integer?(value)
|
108
|
+
value.is_a?(Integer)
|
109
|
+
end
|
110
|
+
end
|
111
|
+
end
|
112
|
+
end
|
113
|
+
end
|
114
|
+
end
|
@@ -0,0 +1,57 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class InterfaceInstance
|
8
|
+
include Core::Utility::AttributeSetter
|
9
|
+
|
10
|
+
def initialize(**default_attributes)
|
11
|
+
apply_attributes(default_attributes)
|
12
|
+
block_given? && yield(self)
|
13
|
+
end
|
14
|
+
|
15
|
+
define_attribute :name
|
16
|
+
define_attribute :interface_type
|
17
|
+
define_attribute :parameter_values
|
18
|
+
define_attribute :port_connections
|
19
|
+
define_attribute :array_size
|
20
|
+
define_attribute :variables
|
21
|
+
|
22
|
+
def instantiation
|
23
|
+
[
|
24
|
+
interface_type,
|
25
|
+
parameter_value_assignments,
|
26
|
+
instance_identifier
|
27
|
+
].select(&:itself).join(' ')
|
28
|
+
end
|
29
|
+
|
30
|
+
alias_method :declaration, :instantiation
|
31
|
+
|
32
|
+
def identifier
|
33
|
+
Identifier.new(name) do |identifier|
|
34
|
+
identifier.__array_size__(array_size)
|
35
|
+
identifier.__sub_identifiers__(variables)
|
36
|
+
end
|
37
|
+
end
|
38
|
+
|
39
|
+
private
|
40
|
+
|
41
|
+
def parameter_value_assignments
|
42
|
+
values = Array(parameter_values)
|
43
|
+
values.size.positive? && "#(#{values.join(', ')})"
|
44
|
+
end
|
45
|
+
|
46
|
+
def instance_identifier
|
47
|
+
[
|
48
|
+
name,
|
49
|
+
*Array(array_size).map { |size| "[#{size}]" },
|
50
|
+
"(#{Array(port_connections).join(', ')})"
|
51
|
+
].join
|
52
|
+
end
|
53
|
+
end
|
54
|
+
end
|
55
|
+
end
|
56
|
+
end
|
57
|
+
end
|
@@ -0,0 +1,51 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class InterfacePort
|
8
|
+
include Core::Utility::AttributeSetter
|
9
|
+
|
10
|
+
def initialize(**default_attributes)
|
11
|
+
apply_attributes(default_attributes)
|
12
|
+
block_given? && yield(self)
|
13
|
+
end
|
14
|
+
|
15
|
+
define_attribute :name
|
16
|
+
define_attribute :interface_type
|
17
|
+
define_attribute :modport
|
18
|
+
define_attribute :array_size
|
19
|
+
|
20
|
+
def modport(name, ports = nil)
|
21
|
+
@modport_name = name
|
22
|
+
@modport_ports = ports
|
23
|
+
end
|
24
|
+
|
25
|
+
def declaration
|
26
|
+
"#{port_type} #{port_identifier}"
|
27
|
+
end
|
28
|
+
|
29
|
+
def identifier
|
30
|
+
Identifier.new(name) do |identifier|
|
31
|
+
identifier.__array_size__(array_size)
|
32
|
+
identifier.__sub_identifiers__(@modport_ports)
|
33
|
+
end
|
34
|
+
end
|
35
|
+
|
36
|
+
private
|
37
|
+
|
38
|
+
def port_type
|
39
|
+
[@interface_type, @modport_name].compact.join('.')
|
40
|
+
end
|
41
|
+
|
42
|
+
def port_identifier
|
43
|
+
[
|
44
|
+
name, *Array(array_size).map { |size| "[#{size}]" }
|
45
|
+
].join
|
46
|
+
end
|
47
|
+
end
|
48
|
+
end
|
49
|
+
end
|
50
|
+
end
|
51
|
+
end
|
@@ -0,0 +1,64 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class LocalScope < StructureDefinition
|
8
|
+
define_attribute :name
|
9
|
+
define_attribute :variables
|
10
|
+
define_attribute :loop_size
|
11
|
+
|
12
|
+
def top_scope
|
13
|
+
@top_scope = true
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def header_code(code)
|
19
|
+
code << [:generate, space] if @top_scope
|
20
|
+
code << "if (1) begin : #{name}" << nl
|
21
|
+
end
|
22
|
+
|
23
|
+
def footer_code(code)
|
24
|
+
code << :end
|
25
|
+
code << [space, :endgenerate] if @top_scope
|
26
|
+
end
|
27
|
+
|
28
|
+
def pre_body_code(code)
|
29
|
+
genvar_declarations(code)
|
30
|
+
generate_for_header(code)
|
31
|
+
variable_declarations(code)
|
32
|
+
end
|
33
|
+
|
34
|
+
def genvar_declarations(code)
|
35
|
+
genvars = Array(loop_size&.keys).map { |genvar| "genvar #{genvar}" }
|
36
|
+
add_declarations_to_body(code, genvars)
|
37
|
+
end
|
38
|
+
|
39
|
+
def generate_for_header(code)
|
40
|
+
loop_size&.each do |genvar, size|
|
41
|
+
code << generate_for(genvar, size) << nl
|
42
|
+
code.indent += 2
|
43
|
+
end
|
44
|
+
end
|
45
|
+
|
46
|
+
def generate_for(genvar, size)
|
47
|
+
"for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
|
48
|
+
end
|
49
|
+
|
50
|
+
def variable_declarations(code)
|
51
|
+
add_declarations_to_body(code, Array(variables))
|
52
|
+
end
|
53
|
+
|
54
|
+
def post_body_code(code)
|
55
|
+
(loop_size&.size || 0).times do
|
56
|
+
code.indent -= 2
|
57
|
+
code << :end << nl
|
58
|
+
end
|
59
|
+
end
|
60
|
+
end
|
61
|
+
end
|
62
|
+
end
|
63
|
+
end
|
64
|
+
end
|
@@ -0,0 +1,76 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class ModuleDefinition < StructureDefinition
|
8
|
+
define_attribute :name
|
9
|
+
define_attribute :package_imports
|
10
|
+
define_attribute :parameters
|
11
|
+
define_attribute :ports
|
12
|
+
define_attribute :variables
|
13
|
+
|
14
|
+
def package_imports(packages)
|
15
|
+
@package_imports ||= []
|
16
|
+
@package_imports.concat(Array(packages))
|
17
|
+
end
|
18
|
+
|
19
|
+
def package_import(package)
|
20
|
+
package_imports([package])
|
21
|
+
end
|
22
|
+
|
23
|
+
private
|
24
|
+
|
25
|
+
def header_code(code)
|
26
|
+
code << [:module, space, name]
|
27
|
+
package_import_declaration(code)
|
28
|
+
parameter_declarations(code)
|
29
|
+
port_declarations(code)
|
30
|
+
code << semicolon
|
31
|
+
end
|
32
|
+
|
33
|
+
def package_import_declaration(code)
|
34
|
+
if (items = pacakge_import_items).empty?
|
35
|
+
code << space
|
36
|
+
return
|
37
|
+
end
|
38
|
+
add_declarations_to_header(code, items, semicolon)
|
39
|
+
end
|
40
|
+
|
41
|
+
def pacakge_import_items
|
42
|
+
Array(@package_imports).map.with_index do |package, i|
|
43
|
+
if i.zero?
|
44
|
+
[:import, "#{package}::*"].join(space)
|
45
|
+
else
|
46
|
+
[space(6), "#{package}::*"].join(space)
|
47
|
+
end
|
48
|
+
end
|
49
|
+
end
|
50
|
+
|
51
|
+
def parameter_declarations(code)
|
52
|
+
declarations = Array(parameters)
|
53
|
+
declarations.empty? || wrap(code, '#(', ')') do
|
54
|
+
add_declarations_to_header(code, declarations)
|
55
|
+
end
|
56
|
+
end
|
57
|
+
|
58
|
+
def port_declarations(code)
|
59
|
+
declarations = Array(ports)
|
60
|
+
wrap(code, '(', ')') do
|
61
|
+
add_declarations_to_header(code, declarations)
|
62
|
+
end
|
63
|
+
end
|
64
|
+
|
65
|
+
def pre_body_code(code)
|
66
|
+
add_declarations_to_body(code, Array(variables))
|
67
|
+
end
|
68
|
+
|
69
|
+
def footer_code
|
70
|
+
:endmodule
|
71
|
+
end
|
72
|
+
end
|
73
|
+
end
|
74
|
+
end
|
75
|
+
end
|
76
|
+
end
|
@@ -0,0 +1,61 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module Common
|
6
|
+
module Utility
|
7
|
+
class PackageDefinition < StructureDefinition
|
8
|
+
define_attribute :name
|
9
|
+
define_attribute :package_imports
|
10
|
+
define_attribute :include_files
|
11
|
+
|
12
|
+
def package_imports(packages)
|
13
|
+
@package_imports ||= []
|
14
|
+
@package_imports.concat(Array(packages))
|
15
|
+
end
|
16
|
+
|
17
|
+
def package_import(package)
|
18
|
+
package_imports([package])
|
19
|
+
end
|
20
|
+
|
21
|
+
def include_files(files)
|
22
|
+
@include_files ||= []
|
23
|
+
@include_files.concat(Array(files))
|
24
|
+
end
|
25
|
+
|
26
|
+
def include_file(file)
|
27
|
+
include_files([file])
|
28
|
+
end
|
29
|
+
|
30
|
+
private
|
31
|
+
|
32
|
+
def header_code(code)
|
33
|
+
code << [:package, space, name, semicolon]
|
34
|
+
end
|
35
|
+
|
36
|
+
def pre_body_code(code)
|
37
|
+
package_import_declaration(code)
|
38
|
+
file_include_directives(code)
|
39
|
+
end
|
40
|
+
|
41
|
+
def package_import_declaration(code)
|
42
|
+
declarations =
|
43
|
+
Array(@package_imports)
|
44
|
+
.map { |package| [:import, space, package, '::*'] }
|
45
|
+
add_declarations_to_body(code, declarations)
|
46
|
+
end
|
47
|
+
|
48
|
+
def file_include_directives(code)
|
49
|
+
Array(@include_files).each do |file|
|
50
|
+
code << [:'`include', space, string(file), nl]
|
51
|
+
end
|
52
|
+
end
|
53
|
+
|
54
|
+
def footer_code
|
55
|
+
:endpackage
|
56
|
+
end
|
57
|
+
end
|
58
|
+
end
|
59
|
+
end
|
60
|
+
end
|
61
|
+
end
|