rggen-systemverilog 0.11.1 → 0.13.0

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Files changed (89) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +2 -8
  3. data/lib/rggen/systemverilog.rb +3 -47
  4. data/lib/rggen/systemverilog/common.rb +44 -0
  5. data/lib/rggen/systemverilog/common/component.rb +25 -0
  6. data/lib/rggen/systemverilog/common/factories.rb +13 -0
  7. data/lib/rggen/systemverilog/common/feature.rb +78 -0
  8. data/lib/rggen/systemverilog/common/utility.rb +95 -0
  9. data/lib/rggen/systemverilog/common/utility/class_definition.rb +45 -0
  10. data/lib/rggen/systemverilog/common/utility/data_object.rb +131 -0
  11. data/lib/rggen/systemverilog/common/utility/function_definition.rb +47 -0
  12. data/lib/rggen/systemverilog/common/utility/identifier.rb +114 -0
  13. data/lib/rggen/systemverilog/common/utility/interface_instance.rb +57 -0
  14. data/lib/rggen/systemverilog/common/utility/interface_port.rb +51 -0
  15. data/lib/rggen/systemverilog/common/utility/local_scope.rb +64 -0
  16. data/lib/rggen/systemverilog/common/utility/module_definition.rb +76 -0
  17. data/lib/rggen/systemverilog/common/utility/package_definition.rb +61 -0
  18. data/lib/rggen/systemverilog/common/utility/source_file.rb +16 -0
  19. data/lib/rggen/systemverilog/common/utility/structure_definition.rb +39 -0
  20. data/lib/rggen/systemverilog/ral.rb +38 -0
  21. data/lib/rggen/systemverilog/ral/bit_field/type.rb +83 -0
  22. data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +5 -0
  23. data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb +23 -0
  24. data/lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb +7 -0
  25. data/lib/rggen/systemverilog/ral/feature.rb +26 -0
  26. data/lib/rggen/systemverilog/ral/register/type.rb +154 -0
  27. data/lib/rggen/systemverilog/ral/register/type/default.erb +8 -0
  28. data/lib/rggen/systemverilog/ral/register/type/external.rb +27 -0
  29. data/lib/rggen/systemverilog/ral/register/type/indirect.erb +13 -0
  30. data/lib/rggen/systemverilog/ral/register/type/indirect.rb +35 -0
  31. data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +11 -0
  32. data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +65 -0
  33. data/lib/rggen/systemverilog/ral/setup.rb +7 -0
  34. data/lib/rggen/systemverilog/rtl.rb +50 -0
  35. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +89 -0
  36. data/lib/rggen/systemverilog/rtl/bit_field/type.rb +62 -0
  37. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +15 -0
  38. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +59 -0
  39. data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +3 -0
  40. data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +7 -0
  41. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +6 -0
  42. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +22 -0
  43. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +6 -0
  44. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb +7 -0
  45. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +13 -0
  46. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +32 -0
  47. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb +9 -0
  48. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +14 -0
  49. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb +16 -0
  50. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb +61 -0
  51. data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +9 -0
  52. data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +20 -0
  53. data/lib/rggen/systemverilog/rtl/feature.rb +48 -0
  54. data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +19 -0
  55. data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +24 -0
  56. data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +82 -0
  57. data/lib/rggen/systemverilog/rtl/register/type.rb +65 -0
  58. data/lib/rggen/systemverilog/rtl/register/type/default.erb +15 -0
  59. data/lib/rggen/systemverilog/rtl/register/type/external.erb +11 -0
  60. data/lib/rggen/systemverilog/rtl/register/type/external.rb +91 -0
  61. data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +17 -0
  62. data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +40 -0
  63. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +100 -0
  64. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +10 -0
  65. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +89 -0
  66. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -0
  67. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +125 -0
  68. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +9 -0
  69. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +86 -0
  70. data/lib/rggen/systemverilog/rtl/setup.rb +13 -0
  71. data/lib/rggen/systemverilog/version.rb +1 -1
  72. metadata +70 -20
  73. data/lib/rggen/systemverilog/component.rb +0 -23
  74. data/lib/rggen/systemverilog/factories.rb +0 -11
  75. data/lib/rggen/systemverilog/feature.rb +0 -76
  76. data/lib/rggen/systemverilog/feature_ral.rb +0 -24
  77. data/lib/rggen/systemverilog/feature_rtl.rb +0 -46
  78. data/lib/rggen/systemverilog/utility.rb +0 -93
  79. data/lib/rggen/systemverilog/utility/class_definition.rb +0 -43
  80. data/lib/rggen/systemverilog/utility/data_object.rb +0 -129
  81. data/lib/rggen/systemverilog/utility/function_definition.rb +0 -45
  82. data/lib/rggen/systemverilog/utility/identifier.rb +0 -112
  83. data/lib/rggen/systemverilog/utility/interface_instance.rb +0 -55
  84. data/lib/rggen/systemverilog/utility/interface_port.rb +0 -49
  85. data/lib/rggen/systemverilog/utility/local_scope.rb +0 -62
  86. data/lib/rggen/systemverilog/utility/module_definition.rb +0 -74
  87. data/lib/rggen/systemverilog/utility/package_definition.rb +0 -59
  88. data/lib/rggen/systemverilog/utility/source_file.rb +0 -14
  89. data/lib/rggen/systemverilog/utility/structure_definition.rb +0 -37
@@ -0,0 +1,47 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
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+ module SystemVerilog
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+ module Common
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+ module Utility
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+ class FunctionDefinition < StructureDefinition
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+ define_attribute :name
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+ define_attribute :return_type
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+ define_attribute :arguments
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+
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+ def return_type(**attributes)
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+ attributes.size.zero? || (
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+ @return_type = DataObject.new(:variable, **attributes)
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+ )
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+ @return_type
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+ end
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+
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+ private
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+
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+ def header_code(code)
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+ code << :function
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+ return_type_declaration(code)
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+ code << [space, name]
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+ argument_declarations(code)
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+ code << semicolon
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+ end
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+
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+ def return_type_declaration(code)
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+ return unless @return_type
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+ code << [space, return_type.declaration]
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+ end
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+
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+ def argument_declarations(code)
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+ wrap(code, '(', ')') do
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+ add_declarations_to_header(code, Array(arguments))
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+ end
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+ end
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+
40
+ def footer_code
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+ :endfunction
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+ end
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+ end
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,114 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
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+ module SystemVerilog
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+ module Common
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+ module Utility
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+ class Identifier
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+ def initialize(name)
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+ @name = name
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+ block_given? && yield(self)
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+ end
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+
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+ def __width__(width)
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+ @width = width
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+ end
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+
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+ def __array_size__(array_size)
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+ @array_size = array_size
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+ end
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+
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+ def __array_format__(array_format)
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+ @array_format = array_format
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+ end
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+
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+ def __sub_identifiers__(sub_identifiers)
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+ Array(sub_identifiers).each do |sub_identifier|
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+ (@sub_identifiers ||= []) << sub_identifier
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+ define_singleton_method(sub_identifier) do
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+ Identifier.new("#{@name}.#{__method__}")
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+ end
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+ end
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+ end
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+
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+ def to_s
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+ @name.to_s
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+ end
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+
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+ def [](array_index_or_lsb, width = nil)
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+ if array_index_or_lsb
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+ __create_new_identifier__(array_index_or_lsb, width)
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+ else
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+ self
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+ end
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+ end
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+
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+ private
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+
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+ def __create_new_identifier__(array_index_or_lsb, width)
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+ select = __create_select__(array_index_or_lsb, width)
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+ Identifier.new("#{@name}#{select}") do |identifier|
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+ identifier.__sub_identifiers__(@sub_identifiers)
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+ end
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+ end
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+
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+ def __create_select__(array_index_or_lsb, width)
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+ if array_index_or_lsb.is_a?(::Array)
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+ __array_select__(array_index_or_lsb)
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+ elsif width
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+ "[#{array_index_or_lsb}+:#{width}]"
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+ else
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+ "[#{array_index_or_lsb}]"
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+ end
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+ end
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+
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+ def __array_select__(array_index)
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+ if @array_format == :serialized
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+ "[#{__serialized_lsb__(array_index)}+:#{@width}]"
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+ else
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+ array_index
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+ .map { |index| "[#{index}]" }
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+ .join
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+ end
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+ end
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+
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+ def __serialized_lsb__(array_index)
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+ __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
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+ end
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+
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+ def __serialized_index__(array_index)
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+ index_values =
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+ array_index
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+ .reverse
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+ .zip(__index_factors__)
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+ .map { |i, f| __calc_index_value__(i, f) }
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+ index = __reduce_array__(index_values.reverse, :+, 0)
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+ integer?(index) ? index : "(#{index})"
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+ end
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+
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+ def __index_factors__
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+ Array.new(@array_size.size) do |i|
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+ i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
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+ end
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+ end
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+
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+ def __calc_index_value__(index, factor)
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+ __reduce_array__([factor, index].compact, :*, 1)
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+ end
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+
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+ def __reduce_array__(array, operator, initial_value)
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+ if array.all?(&method(:integer?))
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+ array.reduce(initial_value, &operator)
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+ else
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+ array.join(operator.to_s)
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+ end
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+ end
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+
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+ def integer?(value)
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+ value.is_a?(Integer)
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+ end
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+ end
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,57 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
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+ module SystemVerilog
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+ module Common
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+ module Utility
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+ class InterfaceInstance
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+ include Core::Utility::AttributeSetter
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+
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+ def initialize(**default_attributes)
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+ apply_attributes(default_attributes)
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+ block_given? && yield(self)
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+ end
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+
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+ define_attribute :name
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+ define_attribute :interface_type
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+ define_attribute :parameter_values
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+ define_attribute :port_connections
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+ define_attribute :array_size
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+ define_attribute :variables
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+
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+ def instantiation
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+ [
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+ interface_type,
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+ parameter_value_assignments,
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+ instance_identifier
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+ ].select(&:itself).join(' ')
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+ end
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+
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+ alias_method :declaration, :instantiation
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+
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+ def identifier
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+ Identifier.new(name) do |identifier|
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+ identifier.__array_size__(array_size)
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+ identifier.__sub_identifiers__(variables)
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+ end
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+ end
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+
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+ private
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+
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+ def parameter_value_assignments
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+ values = Array(parameter_values)
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+ values.size.positive? && "#(#{values.join(', ')})"
44
+ end
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+
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+ def instance_identifier
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+ [
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+ name,
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+ *Array(array_size).map { |size| "[#{size}]" },
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+ "(#{Array(port_connections).join(', ')})"
51
+ ].join
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+ end
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+ end
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,51 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
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+ module SystemVerilog
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+ module Common
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+ module Utility
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+ class InterfacePort
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+ include Core::Utility::AttributeSetter
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+
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+ def initialize(**default_attributes)
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+ apply_attributes(default_attributes)
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+ block_given? && yield(self)
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+ end
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+
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+ define_attribute :name
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+ define_attribute :interface_type
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+ define_attribute :modport
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+ define_attribute :array_size
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+
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+ def modport(name, ports = nil)
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+ @modport_name = name
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+ @modport_ports = ports
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+ end
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+
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+ def declaration
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+ "#{port_type} #{port_identifier}"
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+ end
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+
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+ def identifier
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+ Identifier.new(name) do |identifier|
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+ identifier.__array_size__(array_size)
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+ identifier.__sub_identifiers__(@modport_ports)
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+ end
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+ end
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+
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+ private
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+
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+ def port_type
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+ [@interface_type, @modport_name].compact.join('.')
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+ end
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+
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+ def port_identifier
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+ [
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+ name, *Array(array_size).map { |size| "[#{size}]" }
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+ ].join
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+ end
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+ end
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,64 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
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+ module SystemVerilog
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+ module Common
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+ module Utility
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+ class LocalScope < StructureDefinition
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+ define_attribute :name
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+ define_attribute :variables
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+ define_attribute :loop_size
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+
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+ def top_scope
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+ @top_scope = true
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+ end
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+
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+ private
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+
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+ def header_code(code)
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+ code << [:generate, space] if @top_scope
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+ code << "if (1) begin : #{name}" << nl
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+ end
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+
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+ def footer_code(code)
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+ code << :end
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+ code << [space, :endgenerate] if @top_scope
26
+ end
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+
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+ def pre_body_code(code)
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+ genvar_declarations(code)
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+ generate_for_header(code)
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+ variable_declarations(code)
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+ end
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+
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+ def genvar_declarations(code)
35
+ genvars = Array(loop_size&.keys).map { |genvar| "genvar #{genvar}" }
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+ add_declarations_to_body(code, genvars)
37
+ end
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+
39
+ def generate_for_header(code)
40
+ loop_size&.each do |genvar, size|
41
+ code << generate_for(genvar, size) << nl
42
+ code.indent += 2
43
+ end
44
+ end
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+
46
+ def generate_for(genvar, size)
47
+ "for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
48
+ end
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+
50
+ def variable_declarations(code)
51
+ add_declarations_to_body(code, Array(variables))
52
+ end
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+
54
+ def post_body_code(code)
55
+ (loop_size&.size || 0).times do
56
+ code.indent -= 2
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+ code << :end << nl
58
+ end
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+ end
60
+ end
61
+ end
62
+ end
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+ end
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+ end
@@ -0,0 +1,76 @@
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+ # frozen_string_literal: true
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+
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+ module RgGen
4
+ module SystemVerilog
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+ module Common
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+ module Utility
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+ class ModuleDefinition < StructureDefinition
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+ define_attribute :name
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+ define_attribute :package_imports
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+ define_attribute :parameters
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+ define_attribute :ports
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+ define_attribute :variables
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+
14
+ def package_imports(packages)
15
+ @package_imports ||= []
16
+ @package_imports.concat(Array(packages))
17
+ end
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+
19
+ def package_import(package)
20
+ package_imports([package])
21
+ end
22
+
23
+ private
24
+
25
+ def header_code(code)
26
+ code << [:module, space, name]
27
+ package_import_declaration(code)
28
+ parameter_declarations(code)
29
+ port_declarations(code)
30
+ code << semicolon
31
+ end
32
+
33
+ def package_import_declaration(code)
34
+ if (items = pacakge_import_items).empty?
35
+ code << space
36
+ return
37
+ end
38
+ add_declarations_to_header(code, items, semicolon)
39
+ end
40
+
41
+ def pacakge_import_items
42
+ Array(@package_imports).map.with_index do |package, i|
43
+ if i.zero?
44
+ [:import, "#{package}::*"].join(space)
45
+ else
46
+ [space(6), "#{package}::*"].join(space)
47
+ end
48
+ end
49
+ end
50
+
51
+ def parameter_declarations(code)
52
+ declarations = Array(parameters)
53
+ declarations.empty? || wrap(code, '#(', ')') do
54
+ add_declarations_to_header(code, declarations)
55
+ end
56
+ end
57
+
58
+ def port_declarations(code)
59
+ declarations = Array(ports)
60
+ wrap(code, '(', ')') do
61
+ add_declarations_to_header(code, declarations)
62
+ end
63
+ end
64
+
65
+ def pre_body_code(code)
66
+ add_declarations_to_body(code, Array(variables))
67
+ end
68
+
69
+ def footer_code
70
+ :endmodule
71
+ end
72
+ end
73
+ end
74
+ end
75
+ end
76
+ end
@@ -0,0 +1,61 @@
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+ # frozen_string_literal: true
2
+
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+ module RgGen
4
+ module SystemVerilog
5
+ module Common
6
+ module Utility
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+ class PackageDefinition < StructureDefinition
8
+ define_attribute :name
9
+ define_attribute :package_imports
10
+ define_attribute :include_files
11
+
12
+ def package_imports(packages)
13
+ @package_imports ||= []
14
+ @package_imports.concat(Array(packages))
15
+ end
16
+
17
+ def package_import(package)
18
+ package_imports([package])
19
+ end
20
+
21
+ def include_files(files)
22
+ @include_files ||= []
23
+ @include_files.concat(Array(files))
24
+ end
25
+
26
+ def include_file(file)
27
+ include_files([file])
28
+ end
29
+
30
+ private
31
+
32
+ def header_code(code)
33
+ code << [:package, space, name, semicolon]
34
+ end
35
+
36
+ def pre_body_code(code)
37
+ package_import_declaration(code)
38
+ file_include_directives(code)
39
+ end
40
+
41
+ def package_import_declaration(code)
42
+ declarations =
43
+ Array(@package_imports)
44
+ .map { |package| [:import, space, package, '::*'] }
45
+ add_declarations_to_body(code, declarations)
46
+ end
47
+
48
+ def file_include_directives(code)
49
+ Array(@include_files).each do |file|
50
+ code << [:'`include', space, string(file), nl]
51
+ end
52
+ end
53
+
54
+ def footer_code
55
+ :endpackage
56
+ end
57
+ end
58
+ end
59
+ end
60
+ end
61
+ end