rggen-systemverilog 0.11.1 → 0.13.0

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -0,0 +1,6 @@
+rggen_bit_field_ro #(
+  .WIDTH  (<%= width %>)
+) u_bit_field (
+  .bit_field_if (<%= bit_field_if %>),
+  .i_value      (<%= initial_value %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  sv_rtl do
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb

@@ -0,0 +1,13 @@
+<%= module_name %> #(
+<% if [:w0s, :w1s].include?(bit_field.type) %>
+  .SET_VALUE      (<%= set_value %>),
+<% end %>
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_clear      (<%= clear[loop_variables] %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
+  sv_rtl do
+    build do
+      input :register_block, :clear, {
+        name: "i_#{full_name}_clear", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def module_name
+      if bit_field.type == :rs
+        'rggen_bit_field_rs'
+      else
+        'rggen_bit_field_w01s'
+      end
+    end
+
+    def set_value
+      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
+  sv_rtl do
+    build do
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb

@@ -0,0 +1,16 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+<% if bit_field.type == :rwc %>
+  .i_clear      (<%= control_signal %>),
+<% elsif bit_field.type == :rwe %>
+  .i_enable     (<%= control_signal %>),
+<% else %>
+  .i_lock       (<%= control_signal %>),
+<% end %>
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb

@@ -0,0 +1,61 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwe, :rwl]) do
+  sv_rtl do
+    build do
+      if clear_port?
+        input :register_block, :clear, {
+          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if enable_port?
+        input :register_block, :enable, {
+          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if lock_port?
+        input :register_block, :lock, {
+          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_port?
+      bit_field.type == :rwc && !bit_field.reference?
+    end
+
+    def enable_port?
+      bit_field.type == :rwe && !bit_field.reference?
+    end
+
+    def lock_port?
+      bit_field.type == :rwl && !bit_field.reference?
+    end
+
+    def control_signal
+      reference_bit_field || control_port[loop_variables]
+    end
+
+    def control_port
+      case bit_field.type
+      when :rwc
+        clear
+      when :rwe
+        enable
+      when :rwl
+        lock
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_w01trg #(
+  .TRIGGER_VALUE  (<%= trigger_value %>),
+  .WIDTH          (<%= width %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_trigger    (<%= trigger[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+  sv_rtl do
+    build do
+      output :register_block, :trigger, {
+        name: "o_#{full_name}_trigger", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def trigger_value
+      bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      class Feature < Common::Feature
+        private
+
+        def create_variable(data_type, attributes, block)
+          DataObject.new(
+            :variable, attributes.merge(data_type: data_type), &block
+          )
+        end
+
+        def create_interface(_, attributes, block)
+          InterfaceInstance.new(attributes, &block)
+        end
+
+        def create_argument(direction, attributes, block)
+          DataObject.new(
+            :argument, attributes.merge(direction: direction), &block
+          )
+        end
+
+        def create_interface_port(_, attributes, block)
+          InterfacePort.new(attributes, &block)
+        end
+
+        def create_parameter(_, attributes, block)
+          DataObject.new(
+            :parameter, attributes.merge(parameter_type: :parameter), &block
+          )
+        end
+
+        [
+          [:logic, :create_variable, :variable],
+          [:interface, :create_interface, :variable],
+          [:input, :create_argument, :port],
+          [:output, :create_argument, :port],
+          [:interface_port, :create_interface_port, :port],
+          [:parameter, :create_parameter, :parameter]
+        ].each do |entity, creation_method, declaration_type|
+          define_entity(entity, creation_method, declaration_type)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/global/array_port_format.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :array_port_format) do
+  configuration do
+    property :array_port_format, default: :packed
+
+    input_pattern /(packed|unpacked|serialized)/i
+    ignore_empty_value false
+
+    build do |value|
+      @array_port_format =
+        if pattern_matched?
+          match_data[1].downcase.to_sym
+        else
+          error "illegal input value for array port format: #{value.inspect}"
+        end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
+  configuration do
+    property :fold_sv_interface_port?, default: true
+
+    input_pattern [
+      /true|on|yes/i, /false|off|no/i
+    ], match_automatically: false
+
+    ignore_empty_value false
+
+    build do |value|
+      @fold_sv_interface_port =
+        if [true, false].include?(value)
+          value
+        elsif match_pattern(value)
+          [true, false][match_index]
+        else
+          error "cannot convert #{value.inspect} into boolean"
+        end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :sv_rtl_top) do
+  sv_rtl do
+    export :index
+    export :local_index
+    export :loop_variables
+
+    pre_build do
+      @base_index =
+        register_block.registers.map(&:count).inject(0, :+)
+    end
+
+    build do
+      if register.bit_fields?
+        interface :register, :bit_field_if, {
+          name: 'bit_field_if',
+          interface_type: 'rggen_bit_field_if',
+          parameter_values: [register.width]
+        }
+      end
+    end
+
+    main_code :register_block do
+      local_scope("g_#{register.name}") do |scope|
+        scope.top_scope
+        scope.loop_size loop_size
+        scope.variables variables
+        scope.body(&method(:body_code))
+      end
+    end
+
+    def index(offset = nil)
+      operands =
+        register.array? ? [@base_index, offset || local_index] : [@base_index]
+      if operands.all? { |operand| operand.is_a?(Integer) }
+        operands.inject(:+)
+      else
+        operands.join('+')
+      end
+    end
+
+    def local_index
+      (register.array? || nil) &&
+        loop_variables
+          .zip(local_index_coefficients)
+          .map { |v, c| [c, v].compact.join('*') }
+          .join('+')
+    end
+
+    def loop_variables
+      (register.array? || nil) &&
+        register.array_size.map.with_index(1) do |_size, i|
+          create_identifier(loop_index(i))
+        end
+    end
+
+    private
+
+    def local_index_coefficients
+      coefficients = []
+      register.array_size.reverse.inject(1) do |total, size|
+        coefficients.unshift(coefficients.size.zero? ? nil : total)
+        total * size
+      end
+      coefficients
+    end
+
+    def loop_size
+      (register.array? || nil) &&
+        loop_variables.zip(register.array_size).to_h
+    end
+
+    def variables
+      register.declarations(:register, :variable)
+    end
+
+    def body_code(code)
+      register.generate_code(:register, :top_down, code)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -0,0 +1,65 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register, :type) do
+  sv_rtl do
+    base_feature do
+      private
+
+      def readable
+        register.readable? && 1 || 0
+      end
+
+      def writable
+        register.writable? && 1 || 0
+      end
+
+      def bus_width
+        configuration.bus_width
+      end
+
+      def address_width
+        register_block.local_address_width
+      end
+
+      def offset_address
+        hex(register.offset_address, address_width)
+      end
+
+      def width
+        register.width
+      end
+
+      def valid_bits
+        bits = register.bit_fields.map(&:bit_map).inject(:|)
+        hex(bits, register.width)
+      end
+
+      def register_index
+        register.local_index || 0
+      end
+
+      def register_if
+        register_block.register_if[register.index]
+      end
+
+      def bit_field_if
+        register.bit_field_if
+      end
+    end
+
+    default_feature do
+      template_path = File.join(__dir__, 'type', 'default.erb')
+      main_code :register, from_template: template_path
+    end
+
+    factory do
+      def select_feature(_configuration, register)
+        target_features[register.type] ||
+          unless register.type == :default
+            error "code generator for #{register.type} register type " \
+                  'is not implemented'
+          end
+      end
+    end
+  end
+end