libv8 3.3.10.2

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (700) hide show
  1. data/.gitignore +8 -0
  2. data/.gitmodules +3 -0
  3. data/Gemfile +4 -0
  4. data/README.md +44 -0
  5. data/Rakefile +73 -0
  6. data/ext/libv8/extconf.rb +9 -0
  7. data/lib/libv8.rb +15 -0
  8. data/lib/libv8/Makefile +38 -0
  9. data/lib/libv8/detect_cpu.rb +27 -0
  10. data/lib/libv8/fpic-on-linux-amd64.patch +13 -0
  11. data/lib/libv8/scons/CHANGES.txt +5334 -0
  12. data/lib/libv8/scons/LICENSE.txt +20 -0
  13. data/lib/libv8/scons/MANIFEST +199 -0
  14. data/lib/libv8/scons/PKG-INFO +13 -0
  15. data/lib/libv8/scons/README.txt +243 -0
  16. data/lib/libv8/scons/RELEASE.txt +98 -0
  17. data/lib/libv8/scons/engine/SCons/Action.py +1241 -0
  18. data/lib/libv8/scons/engine/SCons/Builder.py +877 -0
  19. data/lib/libv8/scons/engine/SCons/CacheDir.py +216 -0
  20. data/lib/libv8/scons/engine/SCons/Conftest.py +793 -0
  21. data/lib/libv8/scons/engine/SCons/Debug.py +220 -0
  22. data/lib/libv8/scons/engine/SCons/Defaults.py +480 -0
  23. data/lib/libv8/scons/engine/SCons/Environment.py +2318 -0
  24. data/lib/libv8/scons/engine/SCons/Errors.py +205 -0
  25. data/lib/libv8/scons/engine/SCons/Executor.py +633 -0
  26. data/lib/libv8/scons/engine/SCons/Job.py +435 -0
  27. data/lib/libv8/scons/engine/SCons/Memoize.py +244 -0
  28. data/lib/libv8/scons/engine/SCons/Node/Alias.py +152 -0
  29. data/lib/libv8/scons/engine/SCons/Node/FS.py +3142 -0
  30. data/lib/libv8/scons/engine/SCons/Node/Python.py +128 -0
  31. data/lib/libv8/scons/engine/SCons/Node/__init__.py +1328 -0
  32. data/lib/libv8/scons/engine/SCons/Options/BoolOption.py +50 -0
  33. data/lib/libv8/scons/engine/SCons/Options/EnumOption.py +50 -0
  34. data/lib/libv8/scons/engine/SCons/Options/ListOption.py +50 -0
  35. data/lib/libv8/scons/engine/SCons/Options/PackageOption.py +50 -0
  36. data/lib/libv8/scons/engine/SCons/Options/PathOption.py +76 -0
  37. data/lib/libv8/scons/engine/SCons/Options/__init__.py +67 -0
  38. data/lib/libv8/scons/engine/SCons/PathList.py +231 -0
  39. data/lib/libv8/scons/engine/SCons/Platform/__init__.py +241 -0
  40. data/lib/libv8/scons/engine/SCons/Platform/aix.py +69 -0
  41. data/lib/libv8/scons/engine/SCons/Platform/cygwin.py +55 -0
  42. data/lib/libv8/scons/engine/SCons/Platform/darwin.py +46 -0
  43. data/lib/libv8/scons/engine/SCons/Platform/hpux.py +46 -0
  44. data/lib/libv8/scons/engine/SCons/Platform/irix.py +44 -0
  45. data/lib/libv8/scons/engine/SCons/Platform/os2.py +58 -0
  46. data/lib/libv8/scons/engine/SCons/Platform/posix.py +263 -0
  47. data/lib/libv8/scons/engine/SCons/Platform/sunos.py +50 -0
  48. data/lib/libv8/scons/engine/SCons/Platform/win32.py +385 -0
  49. data/lib/libv8/scons/engine/SCons/SConf.py +1030 -0
  50. data/lib/libv8/scons/engine/SCons/SConsign.py +383 -0
  51. data/lib/libv8/scons/engine/SCons/Scanner/C.py +132 -0
  52. data/lib/libv8/scons/engine/SCons/Scanner/D.py +73 -0
  53. data/lib/libv8/scons/engine/SCons/Scanner/Dir.py +109 -0
  54. data/lib/libv8/scons/engine/SCons/Scanner/Fortran.py +316 -0
  55. data/lib/libv8/scons/engine/SCons/Scanner/IDL.py +48 -0
  56. data/lib/libv8/scons/engine/SCons/Scanner/LaTeX.py +384 -0
  57. data/lib/libv8/scons/engine/SCons/Scanner/Prog.py +101 -0
  58. data/lib/libv8/scons/engine/SCons/Scanner/RC.py +55 -0
  59. data/lib/libv8/scons/engine/SCons/Scanner/__init__.py +413 -0
  60. data/lib/libv8/scons/engine/SCons/Script/Interactive.py +384 -0
  61. data/lib/libv8/scons/engine/SCons/Script/Main.py +1334 -0
  62. data/lib/libv8/scons/engine/SCons/Script/SConsOptions.py +939 -0
  63. data/lib/libv8/scons/engine/SCons/Script/SConscript.py +640 -0
  64. data/lib/libv8/scons/engine/SCons/Script/__init__.py +412 -0
  65. data/lib/libv8/scons/engine/SCons/Sig.py +63 -0
  66. data/lib/libv8/scons/engine/SCons/Subst.py +904 -0
  67. data/lib/libv8/scons/engine/SCons/Taskmaster.py +1017 -0
  68. data/lib/libv8/scons/engine/SCons/Tool/386asm.py +61 -0
  69. data/lib/libv8/scons/engine/SCons/Tool/BitKeeper.py +67 -0
  70. data/lib/libv8/scons/engine/SCons/Tool/CVS.py +73 -0
  71. data/lib/libv8/scons/engine/SCons/Tool/FortranCommon.py +246 -0
  72. data/lib/libv8/scons/engine/SCons/Tool/JavaCommon.py +323 -0
  73. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/__init__.py +56 -0
  74. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/arch.py +61 -0
  75. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/common.py +240 -0
  76. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/netframework.py +82 -0
  77. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/sdk.py +391 -0
  78. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/vc.py +456 -0
  79. data/lib/libv8/scons/engine/SCons/Tool/MSCommon/vs.py +499 -0
  80. data/lib/libv8/scons/engine/SCons/Tool/Perforce.py +103 -0
  81. data/lib/libv8/scons/engine/SCons/Tool/PharLapCommon.py +137 -0
  82. data/lib/libv8/scons/engine/SCons/Tool/RCS.py +64 -0
  83. data/lib/libv8/scons/engine/SCons/Tool/SCCS.py +64 -0
  84. data/lib/libv8/scons/engine/SCons/Tool/Subversion.py +71 -0
  85. data/lib/libv8/scons/engine/SCons/Tool/__init__.py +681 -0
  86. data/lib/libv8/scons/engine/SCons/Tool/aixc++.py +82 -0
  87. data/lib/libv8/scons/engine/SCons/Tool/aixcc.py +74 -0
  88. data/lib/libv8/scons/engine/SCons/Tool/aixf77.py +80 -0
  89. data/lib/libv8/scons/engine/SCons/Tool/aixlink.py +76 -0
  90. data/lib/libv8/scons/engine/SCons/Tool/applelink.py +71 -0
  91. data/lib/libv8/scons/engine/SCons/Tool/ar.py +63 -0
  92. data/lib/libv8/scons/engine/SCons/Tool/as.py +78 -0
  93. data/lib/libv8/scons/engine/SCons/Tool/bcc32.py +81 -0
  94. data/lib/libv8/scons/engine/SCons/Tool/c++.py +99 -0
  95. data/lib/libv8/scons/engine/SCons/Tool/cc.py +102 -0
  96. data/lib/libv8/scons/engine/SCons/Tool/cvf.py +58 -0
  97. data/lib/libv8/scons/engine/SCons/Tool/default.py +50 -0
  98. data/lib/libv8/scons/engine/SCons/Tool/dmd.py +223 -0
  99. data/lib/libv8/scons/engine/SCons/Tool/dvi.py +64 -0
  100. data/lib/libv8/scons/engine/SCons/Tool/dvipdf.py +124 -0
  101. data/lib/libv8/scons/engine/SCons/Tool/dvips.py +94 -0
  102. data/lib/libv8/scons/engine/SCons/Tool/f77.py +62 -0
  103. data/lib/libv8/scons/engine/SCons/Tool/f90.py +62 -0
  104. data/lib/libv8/scons/engine/SCons/Tool/f95.py +63 -0
  105. data/lib/libv8/scons/engine/SCons/Tool/filesystem.py +98 -0
  106. data/lib/libv8/scons/engine/SCons/Tool/fortran.py +62 -0
  107. data/lib/libv8/scons/engine/SCons/Tool/g++.py +90 -0
  108. data/lib/libv8/scons/engine/SCons/Tool/g77.py +73 -0
  109. data/lib/libv8/scons/engine/SCons/Tool/gas.py +53 -0
  110. data/lib/libv8/scons/engine/SCons/Tool/gcc.py +80 -0
  111. data/lib/libv8/scons/engine/SCons/Tool/gfortran.py +64 -0
  112. data/lib/libv8/scons/engine/SCons/Tool/gnulink.py +63 -0
  113. data/lib/libv8/scons/engine/SCons/Tool/gs.py +81 -0
  114. data/lib/libv8/scons/engine/SCons/Tool/hpc++.py +84 -0
  115. data/lib/libv8/scons/engine/SCons/Tool/hpcc.py +53 -0
  116. data/lib/libv8/scons/engine/SCons/Tool/hplink.py +77 -0
  117. data/lib/libv8/scons/engine/SCons/Tool/icc.py +59 -0
  118. data/lib/libv8/scons/engine/SCons/Tool/icl.py +52 -0
  119. data/lib/libv8/scons/engine/SCons/Tool/ifl.py +72 -0
  120. data/lib/libv8/scons/engine/SCons/Tool/ifort.py +88 -0
  121. data/lib/libv8/scons/engine/SCons/Tool/ilink.py +59 -0
  122. data/lib/libv8/scons/engine/SCons/Tool/ilink32.py +60 -0
  123. data/lib/libv8/scons/engine/SCons/Tool/install.py +229 -0
  124. data/lib/libv8/scons/engine/SCons/Tool/intelc.py +482 -0
  125. data/lib/libv8/scons/engine/SCons/Tool/ipkg.py +67 -0
  126. data/lib/libv8/scons/engine/SCons/Tool/jar.py +110 -0
  127. data/lib/libv8/scons/engine/SCons/Tool/javac.py +230 -0
  128. data/lib/libv8/scons/engine/SCons/Tool/javah.py +137 -0
  129. data/lib/libv8/scons/engine/SCons/Tool/latex.py +79 -0
  130. data/lib/libv8/scons/engine/SCons/Tool/lex.py +97 -0
  131. data/lib/libv8/scons/engine/SCons/Tool/link.py +121 -0
  132. data/lib/libv8/scons/engine/SCons/Tool/linkloc.py +112 -0
  133. data/lib/libv8/scons/engine/SCons/Tool/m4.py +63 -0
  134. data/lib/libv8/scons/engine/SCons/Tool/masm.py +77 -0
  135. data/lib/libv8/scons/engine/SCons/Tool/midl.py +88 -0
  136. data/lib/libv8/scons/engine/SCons/Tool/mingw.py +158 -0
  137. data/lib/libv8/scons/engine/SCons/Tool/mslib.py +64 -0
  138. data/lib/libv8/scons/engine/SCons/Tool/mslink.py +266 -0
  139. data/lib/libv8/scons/engine/SCons/Tool/mssdk.py +50 -0
  140. data/lib/libv8/scons/engine/SCons/Tool/msvc.py +268 -0
  141. data/lib/libv8/scons/engine/SCons/Tool/msvs.py +1388 -0
  142. data/lib/libv8/scons/engine/SCons/Tool/mwcc.py +207 -0
  143. data/lib/libv8/scons/engine/SCons/Tool/mwld.py +107 -0
  144. data/lib/libv8/scons/engine/SCons/Tool/nasm.py +72 -0
  145. data/lib/libv8/scons/engine/SCons/Tool/packaging/__init__.py +312 -0
  146. data/lib/libv8/scons/engine/SCons/Tool/packaging/ipk.py +185 -0
  147. data/lib/libv8/scons/engine/SCons/Tool/packaging/msi.py +527 -0
  148. data/lib/libv8/scons/engine/SCons/Tool/packaging/rpm.py +365 -0
  149. data/lib/libv8/scons/engine/SCons/Tool/packaging/src_tarbz2.py +43 -0
  150. data/lib/libv8/scons/engine/SCons/Tool/packaging/src_targz.py +43 -0
  151. data/lib/libv8/scons/engine/SCons/Tool/packaging/src_zip.py +43 -0
  152. data/lib/libv8/scons/engine/SCons/Tool/packaging/tarbz2.py +44 -0
  153. data/lib/libv8/scons/engine/SCons/Tool/packaging/targz.py +44 -0
  154. data/lib/libv8/scons/engine/SCons/Tool/packaging/zip.py +44 -0
  155. data/lib/libv8/scons/engine/SCons/Tool/pdf.py +78 -0
  156. data/lib/libv8/scons/engine/SCons/Tool/pdflatex.py +83 -0
  157. data/lib/libv8/scons/engine/SCons/Tool/pdftex.py +108 -0
  158. data/lib/libv8/scons/engine/SCons/Tool/qt.py +336 -0
  159. data/lib/libv8/scons/engine/SCons/Tool/rmic.py +120 -0
  160. data/lib/libv8/scons/engine/SCons/Tool/rpcgen.py +70 -0
  161. data/lib/libv8/scons/engine/SCons/Tool/rpm.py +132 -0
  162. data/lib/libv8/scons/engine/SCons/Tool/sgiar.py +68 -0
  163. data/lib/libv8/scons/engine/SCons/Tool/sgic++.py +58 -0
  164. data/lib/libv8/scons/engine/SCons/Tool/sgicc.py +53 -0
  165. data/lib/libv8/scons/engine/SCons/Tool/sgilink.py +63 -0
  166. data/lib/libv8/scons/engine/SCons/Tool/sunar.py +67 -0
  167. data/lib/libv8/scons/engine/SCons/Tool/sunc++.py +142 -0
  168. data/lib/libv8/scons/engine/SCons/Tool/suncc.py +58 -0
  169. data/lib/libv8/scons/engine/SCons/Tool/sunf77.py +63 -0
  170. data/lib/libv8/scons/engine/SCons/Tool/sunf90.py +64 -0
  171. data/lib/libv8/scons/engine/SCons/Tool/sunf95.py +64 -0
  172. data/lib/libv8/scons/engine/SCons/Tool/sunlink.py +77 -0
  173. data/lib/libv8/scons/engine/SCons/Tool/swig.py +182 -0
  174. data/lib/libv8/scons/engine/SCons/Tool/tar.py +73 -0
  175. data/lib/libv8/scons/engine/SCons/Tool/tex.py +813 -0
  176. data/lib/libv8/scons/engine/SCons/Tool/textfile.py +175 -0
  177. data/lib/libv8/scons/engine/SCons/Tool/tlib.py +53 -0
  178. data/lib/libv8/scons/engine/SCons/Tool/wix.py +99 -0
  179. data/lib/libv8/scons/engine/SCons/Tool/yacc.py +130 -0
  180. data/lib/libv8/scons/engine/SCons/Tool/zip.py +99 -0
  181. data/lib/libv8/scons/engine/SCons/Util.py +1492 -0
  182. data/lib/libv8/scons/engine/SCons/Variables/BoolVariable.py +89 -0
  183. data/lib/libv8/scons/engine/SCons/Variables/EnumVariable.py +103 -0
  184. data/lib/libv8/scons/engine/SCons/Variables/ListVariable.py +135 -0
  185. data/lib/libv8/scons/engine/SCons/Variables/PackageVariable.py +106 -0
  186. data/lib/libv8/scons/engine/SCons/Variables/PathVariable.py +147 -0
  187. data/lib/libv8/scons/engine/SCons/Variables/__init__.py +312 -0
  188. data/lib/libv8/scons/engine/SCons/Warnings.py +246 -0
  189. data/lib/libv8/scons/engine/SCons/__init__.py +49 -0
  190. data/lib/libv8/scons/engine/SCons/compat/__init__.py +237 -0
  191. data/lib/libv8/scons/engine/SCons/compat/_scons_builtins.py +150 -0
  192. data/lib/libv8/scons/engine/SCons/compat/_scons_collections.py +45 -0
  193. data/lib/libv8/scons/engine/SCons/compat/_scons_dbm.py +45 -0
  194. data/lib/libv8/scons/engine/SCons/compat/_scons_hashlib.py +76 -0
  195. data/lib/libv8/scons/engine/SCons/compat/_scons_io.py +45 -0
  196. data/lib/libv8/scons/engine/SCons/compat/_scons_sets.py +563 -0
  197. data/lib/libv8/scons/engine/SCons/compat/_scons_subprocess.py +1281 -0
  198. data/lib/libv8/scons/engine/SCons/cpp.py +589 -0
  199. data/lib/libv8/scons/engine/SCons/dblite.py +251 -0
  200. data/lib/libv8/scons/engine/SCons/exitfuncs.py +77 -0
  201. data/lib/libv8/scons/os_spawnv_fix.diff +83 -0
  202. data/lib/libv8/scons/scons-time.1 +1017 -0
  203. data/lib/libv8/scons/scons.1 +15219 -0
  204. data/lib/libv8/scons/sconsign.1 +208 -0
  205. data/lib/libv8/scons/script/scons +196 -0
  206. data/lib/libv8/scons/script/scons-time +1544 -0
  207. data/lib/libv8/scons/script/scons.bat +31 -0
  208. data/lib/libv8/scons/script/sconsign +513 -0
  209. data/lib/libv8/scons/setup.cfg +6 -0
  210. data/lib/libv8/scons/setup.py +425 -0
  211. data/lib/libv8/v8/.gitignore +35 -0
  212. data/lib/libv8/v8/AUTHORS +44 -0
  213. data/lib/libv8/v8/ChangeLog +2839 -0
  214. data/lib/libv8/v8/LICENSE +52 -0
  215. data/lib/libv8/v8/LICENSE.strongtalk +29 -0
  216. data/lib/libv8/v8/LICENSE.v8 +26 -0
  217. data/lib/libv8/v8/LICENSE.valgrind +45 -0
  218. data/lib/libv8/v8/SConstruct +1478 -0
  219. data/lib/libv8/v8/build/README.txt +49 -0
  220. data/lib/libv8/v8/build/all.gyp +18 -0
  221. data/lib/libv8/v8/build/armu.gypi +32 -0
  222. data/lib/libv8/v8/build/common.gypi +144 -0
  223. data/lib/libv8/v8/build/gyp_v8 +145 -0
  224. data/lib/libv8/v8/include/v8-debug.h +395 -0
  225. data/lib/libv8/v8/include/v8-preparser.h +117 -0
  226. data/lib/libv8/v8/include/v8-profiler.h +505 -0
  227. data/lib/libv8/v8/include/v8-testing.h +104 -0
  228. data/lib/libv8/v8/include/v8.h +4124 -0
  229. data/lib/libv8/v8/include/v8stdint.h +53 -0
  230. data/lib/libv8/v8/preparser/SConscript +38 -0
  231. data/lib/libv8/v8/preparser/preparser-process.cc +379 -0
  232. data/lib/libv8/v8/src/SConscript +368 -0
  233. data/lib/libv8/v8/src/accessors.cc +767 -0
  234. data/lib/libv8/v8/src/accessors.h +123 -0
  235. data/lib/libv8/v8/src/allocation-inl.h +49 -0
  236. data/lib/libv8/v8/src/allocation.cc +122 -0
  237. data/lib/libv8/v8/src/allocation.h +143 -0
  238. data/lib/libv8/v8/src/api.cc +5845 -0
  239. data/lib/libv8/v8/src/api.h +574 -0
  240. data/lib/libv8/v8/src/apinatives.js +110 -0
  241. data/lib/libv8/v8/src/apiutils.h +73 -0
  242. data/lib/libv8/v8/src/arguments.h +118 -0
  243. data/lib/libv8/v8/src/arm/assembler-arm-inl.h +353 -0
  244. data/lib/libv8/v8/src/arm/assembler-arm.cc +2661 -0
  245. data/lib/libv8/v8/src/arm/assembler-arm.h +1375 -0
  246. data/lib/libv8/v8/src/arm/builtins-arm.cc +1658 -0
  247. data/lib/libv8/v8/src/arm/code-stubs-arm.cc +6398 -0
  248. data/lib/libv8/v8/src/arm/code-stubs-arm.h +673 -0
  249. data/lib/libv8/v8/src/arm/codegen-arm.cc +52 -0
  250. data/lib/libv8/v8/src/arm/codegen-arm.h +91 -0
  251. data/lib/libv8/v8/src/arm/constants-arm.cc +152 -0
  252. data/lib/libv8/v8/src/arm/constants-arm.h +775 -0
  253. data/lib/libv8/v8/src/arm/cpu-arm.cc +120 -0
  254. data/lib/libv8/v8/src/arm/debug-arm.cc +317 -0
  255. data/lib/libv8/v8/src/arm/deoptimizer-arm.cc +754 -0
  256. data/lib/libv8/v8/src/arm/disasm-arm.cc +1506 -0
  257. data/lib/libv8/v8/src/arm/frames-arm.cc +45 -0
  258. data/lib/libv8/v8/src/arm/frames-arm.h +168 -0
  259. data/lib/libv8/v8/src/arm/full-codegen-arm.cc +4375 -0
  260. data/lib/libv8/v8/src/arm/ic-arm.cc +1562 -0
  261. data/lib/libv8/v8/src/arm/lithium-arm.cc +2206 -0
  262. data/lib/libv8/v8/src/arm/lithium-arm.h +2348 -0
  263. data/lib/libv8/v8/src/arm/lithium-codegen-arm.cc +4526 -0
  264. data/lib/libv8/v8/src/arm/lithium-codegen-arm.h +403 -0
  265. data/lib/libv8/v8/src/arm/lithium-gap-resolver-arm.cc +305 -0
  266. data/lib/libv8/v8/src/arm/lithium-gap-resolver-arm.h +84 -0
  267. data/lib/libv8/v8/src/arm/macro-assembler-arm.cc +3163 -0
  268. data/lib/libv8/v8/src/arm/macro-assembler-arm.h +1126 -0
  269. data/lib/libv8/v8/src/arm/regexp-macro-assembler-arm.cc +1287 -0
  270. data/lib/libv8/v8/src/arm/regexp-macro-assembler-arm.h +253 -0
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@@ -0,0 +1,1138 @@
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+ // Copyright (c) 1994-2006 Sun Microsystems Inc.
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+ // All Rights Reserved.
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+ //
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+ // Redistribution and use in source and binary forms, with or without
5
+ // modification, are permitted provided that the following conditions are
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+ // met:
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+ //
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+ // - Redistributions of source code must retain the above copyright notice,
9
+ // this list of conditions and the following disclaimer.
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+ //
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+ // - Redistribution in binary form must reproduce the above copyright
12
+ // notice, this list of conditions and the following disclaimer in the
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+ // documentation and/or other materials provided with the distribution.
14
+ //
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+ // - Neither the name of Sun Microsystems or the names of contributors may
16
+ // be used to endorse or promote products derived from this software without
17
+ // specific prior written permission.
18
+ //
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+ // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20
+ // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21
+ // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22
+ // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23
+ // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24
+ // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25
+ // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26
+ // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27
+ // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28
+ // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29
+ // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+
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+ // The original source code covered by the above license above has been
32
+ // modified significantly by Google Inc.
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+ // Copyright 2011 the V8 project authors. All rights reserved.
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+
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+
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+ #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
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+ #define V8_MIPS_ASSEMBLER_MIPS_H_
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+
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+ #include <stdio.h>
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+ #include "assembler.h"
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+ #include "constants-mips.h"
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+ #include "serialize.h"
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+
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+ namespace v8 {
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+ namespace internal {
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+
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+ // CPU Registers.
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+ //
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+ // 1) We would prefer to use an enum, but enum values are assignment-
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+ // compatible with int, which has caused code-generation bugs.
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+ //
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+ // 2) We would prefer to use a class instead of a struct but we don't like
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+ // the register initialization to depend on the particular initialization
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+ // order (which appears to be different on OS X, Linux, and Windows for the
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+ // installed versions of C++ we tried). Using a struct permits C-style
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+ // "initialization". Also, the Register objects cannot be const as this
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+ // forces initialization stubs in MSVC, making us dependent on initialization
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+ // order.
59
+ //
60
+ // 3) By not using an enum, we are possibly preventing the compiler from
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+ // doing certain constant folds, which may significantly reduce the
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+ // code generated for some assembly instructions (because they boil down
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+ // to a few constants). If this is a problem, we could change the code
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+ // such that we use an enum in optimized mode, and the struct in debug
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+ // mode. This way we get the compile-time error checking in debug mode
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+ // and best performance in optimized code.
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+
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+
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+ // -----------------------------------------------------------------------------
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+ // Implementation of Register and FPURegister.
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+
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+ // Core register.
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+ struct Register {
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+ static const int kNumRegisters = v8::internal::kNumRegisters;
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+ static const int kNumAllocatableRegisters = 14; // v0 through t7.
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+ static const int kSizeInBytes = 4;
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+
78
+ static int ToAllocationIndex(Register reg) {
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+ return reg.code() - 2; // zero_reg and 'at' are skipped.
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+ }
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+
82
+ static Register FromAllocationIndex(int index) {
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+ ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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+ return from_code(index + 2); // zero_reg and 'at' are skipped.
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+ }
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+
87
+ static const char* AllocationIndexToString(int index) {
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+ ASSERT(index >= 0 && index < kNumAllocatableRegisters);
89
+ const char* const names[] = {
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+ "v0",
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+ "v1",
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+ "a0",
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+ "a1",
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+ "a2",
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+ "a3",
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+ "t0",
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+ "t1",
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+ "t2",
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+ "t3",
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+ "t4",
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+ "t5",
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+ "t6",
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+ "t7",
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+ };
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+ return names[index];
106
+ }
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+
108
+ static Register from_code(int code) {
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+ Register r = { code };
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+ return r;
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+ }
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+
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+ bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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+ bool is(Register reg) const { return code_ == reg.code_; }
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+ int code() const {
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+ ASSERT(is_valid());
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+ return code_;
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+ }
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+ int bit() const {
120
+ ASSERT(is_valid());
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+ return 1 << code_;
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+ }
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+
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+ // Unfortunately we can't make this private in a struct.
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+ int code_;
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+ };
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+
128
+ const Register no_reg = { -1 };
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+
130
+ const Register zero_reg = { 0 };
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+ const Register at = { 1 };
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+ const Register v0 = { 2 };
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+ const Register v1 = { 3 };
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+ const Register a0 = { 4 };
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+ const Register a1 = { 5 };
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+ const Register a2 = { 6 };
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+ const Register a3 = { 7 };
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+ const Register t0 = { 8 };
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+ const Register t1 = { 9 };
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+ const Register t2 = { 10 };
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+ const Register t3 = { 11 };
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+ const Register t4 = { 12 };
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+ const Register t5 = { 13 };
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+ const Register t6 = { 14 };
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+ const Register t7 = { 15 };
146
+ const Register s0 = { 16 };
147
+ const Register s1 = { 17 };
148
+ const Register s2 = { 18 };
149
+ const Register s3 = { 19 };
150
+ const Register s4 = { 20 };
151
+ const Register s5 = { 21 };
152
+ const Register s6 = { 22 };
153
+ const Register s7 = { 23 };
154
+ const Register t8 = { 24 };
155
+ const Register t9 = { 25 };
156
+ const Register k0 = { 26 };
157
+ const Register k1 = { 27 };
158
+ const Register gp = { 28 };
159
+ const Register sp = { 29 };
160
+ const Register s8_fp = { 30 };
161
+ const Register ra = { 31 };
162
+
163
+
164
+ int ToNumber(Register reg);
165
+
166
+ Register ToRegister(int num);
167
+
168
+ // Coprocessor register.
169
+ struct FPURegister {
170
+ static const int kNumRegisters = v8::internal::kNumFPURegisters;
171
+ // f0 has been excluded from allocation. This is following ia32
172
+ // where xmm0 is excluded.
173
+ static const int kNumAllocatableRegisters = 15;
174
+
175
+ static int ToAllocationIndex(FPURegister reg) {
176
+ ASSERT(reg.code() != 0);
177
+ ASSERT(reg.code() % 2 == 0);
178
+ return (reg.code() / 2) - 1;
179
+ }
180
+
181
+ static FPURegister FromAllocationIndex(int index) {
182
+ ASSERT(index >= 0 && index < kNumAllocatableRegisters);
183
+ return from_code((index + 1) * 2);
184
+ }
185
+
186
+ static const char* AllocationIndexToString(int index) {
187
+ ASSERT(index >= 0 && index < kNumAllocatableRegisters);
188
+ const char* const names[] = {
189
+ "f2",
190
+ "f4",
191
+ "f6",
192
+ "f8",
193
+ "f10",
194
+ "f12",
195
+ "f14",
196
+ "f16",
197
+ "f18",
198
+ "f20",
199
+ "f22",
200
+ "f24",
201
+ "f26",
202
+ "f28",
203
+ "f30"
204
+ };
205
+ return names[index];
206
+ }
207
+
208
+ static FPURegister from_code(int code) {
209
+ FPURegister r = { code };
210
+ return r;
211
+ }
212
+
213
+ bool is_valid() const { return 0 <= code_ && code_ < kNumFPURegisters ; }
214
+ bool is(FPURegister creg) const { return code_ == creg.code_; }
215
+ int code() const {
216
+ ASSERT(is_valid());
217
+ return code_;
218
+ }
219
+ int bit() const {
220
+ ASSERT(is_valid());
221
+ return 1 << code_;
222
+ }
223
+ void setcode(int f) {
224
+ code_ = f;
225
+ ASSERT(is_valid());
226
+ }
227
+ // Unfortunately we can't make this private in a struct.
228
+ int code_;
229
+ };
230
+
231
+ typedef FPURegister DoubleRegister;
232
+
233
+ const FPURegister no_creg = { -1 };
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+
235
+ const FPURegister f0 = { 0 }; // Return value in hard float mode.
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+ const FPURegister f1 = { 1 };
237
+ const FPURegister f2 = { 2 };
238
+ const FPURegister f3 = { 3 };
239
+ const FPURegister f4 = { 4 };
240
+ const FPURegister f5 = { 5 };
241
+ const FPURegister f6 = { 6 };
242
+ const FPURegister f7 = { 7 };
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+ const FPURegister f8 = { 8 };
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+ const FPURegister f9 = { 9 };
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+ const FPURegister f10 = { 10 };
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+ const FPURegister f11 = { 11 };
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+ const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
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+ const FPURegister f13 = { 13 };
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+ const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
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+ const FPURegister f15 = { 15 };
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+ const FPURegister f16 = { 16 };
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+ const FPURegister f17 = { 17 };
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+ const FPURegister f18 = { 18 };
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+ const FPURegister f19 = { 19 };
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+ const FPURegister f20 = { 20 };
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+ const FPURegister f21 = { 21 };
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+ const FPURegister f22 = { 22 };
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+ const FPURegister f23 = { 23 };
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+ const FPURegister f24 = { 24 };
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+ const FPURegister f25 = { 25 };
261
+ const FPURegister f26 = { 26 };
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+ const FPURegister f27 = { 27 };
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+ const FPURegister f28 = { 28 };
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+ const FPURegister f29 = { 29 };
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+ const FPURegister f30 = { 30 };
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+ const FPURegister f31 = { 31 };
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+
268
+ // FPU (coprocessor 1) control registers.
269
+ // Currently only FCSR (#31) is implemented.
270
+ struct FPUControlRegister {
271
+ bool is_valid() const { return code_ == kFCSRRegister; }
272
+ bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
273
+ int code() const {
274
+ ASSERT(is_valid());
275
+ return code_;
276
+ }
277
+ int bit() const {
278
+ ASSERT(is_valid());
279
+ return 1 << code_;
280
+ }
281
+ void setcode(int f) {
282
+ code_ = f;
283
+ ASSERT(is_valid());
284
+ }
285
+ // Unfortunately we can't make this private in a struct.
286
+ int code_;
287
+ };
288
+
289
+ const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
290
+ const FPUControlRegister FCSR = { kFCSRRegister };
291
+
292
+
293
+ // -----------------------------------------------------------------------------
294
+ // Machine instruction Operands.
295
+
296
+ // Class Operand represents a shifter operand in data processing instructions.
297
+ class Operand BASE_EMBEDDED {
298
+ public:
299
+ // Immediate.
300
+ INLINE(explicit Operand(int32_t immediate,
301
+ RelocInfo::Mode rmode = RelocInfo::NONE));
302
+ INLINE(explicit Operand(const ExternalReference& f));
303
+ INLINE(explicit Operand(const char* s));
304
+ INLINE(explicit Operand(Object** opp));
305
+ INLINE(explicit Operand(Context** cpp));
306
+ explicit Operand(Handle<Object> handle);
307
+ INLINE(explicit Operand(Smi* value));
308
+
309
+ // Register.
310
+ INLINE(explicit Operand(Register rm));
311
+
312
+ // Return true if this is a register operand.
313
+ INLINE(bool is_reg() const);
314
+
315
+ Register rm() const { return rm_; }
316
+
317
+ private:
318
+ Register rm_;
319
+ int32_t imm32_; // Valid if rm_ == no_reg.
320
+ RelocInfo::Mode rmode_;
321
+
322
+ friend class Assembler;
323
+ friend class MacroAssembler;
324
+ };
325
+
326
+
327
+ // On MIPS we have only one adressing mode with base_reg + offset.
328
+ // Class MemOperand represents a memory operand in load and store instructions.
329
+ class MemOperand : public Operand {
330
+ public:
331
+
332
+ explicit MemOperand(Register rn, int32_t offset = 0);
333
+
334
+ private:
335
+ int32_t offset_;
336
+
337
+ friend class Assembler;
338
+ };
339
+
340
+
341
+ // CpuFeatures keeps track of which features are supported by the target CPU.
342
+ // Supported features must be enabled by a Scope before use.
343
+ class CpuFeatures : public AllStatic {
344
+ public:
345
+ // Detect features of the target CPU. Set safe defaults if the serializer
346
+ // is enabled (snapshots must be portable).
347
+ static void Probe();
348
+
349
+ // Check whether a feature is supported by the target CPU.
350
+ static bool IsSupported(CpuFeature f) {
351
+ ASSERT(initialized_);
352
+ if (f == FPU && !FLAG_enable_fpu) return false;
353
+ return (supported_ & (1u << f)) != 0;
354
+ }
355
+
356
+
357
+ #ifdef DEBUG
358
+ // Check whether a feature is currently enabled.
359
+ static bool IsEnabled(CpuFeature f) {
360
+ ASSERT(initialized_);
361
+ Isolate* isolate = Isolate::UncheckedCurrent();
362
+ if (isolate == NULL) {
363
+ // When no isolate is available, work as if we're running in
364
+ // release mode.
365
+ return IsSupported(f);
366
+ }
367
+ unsigned enabled = static_cast<unsigned>(isolate->enabled_cpu_features());
368
+ return (enabled & (1u << f)) != 0;
369
+ }
370
+ #endif
371
+
372
+ // Enable a specified feature within a scope.
373
+ class Scope BASE_EMBEDDED {
374
+ #ifdef DEBUG
375
+ public:
376
+ explicit Scope(CpuFeature f) {
377
+ unsigned mask = 1u << f;
378
+ ASSERT(CpuFeatures::IsSupported(f));
379
+ ASSERT(!Serializer::enabled() ||
380
+ (CpuFeatures::found_by_runtime_probing_ & mask) == 0);
381
+ isolate_ = Isolate::UncheckedCurrent();
382
+ old_enabled_ = 0;
383
+ if (isolate_ != NULL) {
384
+ old_enabled_ = static_cast<unsigned>(isolate_->enabled_cpu_features());
385
+ isolate_->set_enabled_cpu_features(old_enabled_ | mask);
386
+ }
387
+ }
388
+ ~Scope() {
389
+ ASSERT_EQ(Isolate::UncheckedCurrent(), isolate_);
390
+ if (isolate_ != NULL) {
391
+ isolate_->set_enabled_cpu_features(old_enabled_);
392
+ }
393
+ }
394
+ private:
395
+ Isolate* isolate_;
396
+ unsigned old_enabled_;
397
+ #else
398
+ public:
399
+ explicit Scope(CpuFeature f) {}
400
+ #endif
401
+ };
402
+
403
+ class TryForceFeatureScope BASE_EMBEDDED {
404
+ public:
405
+ explicit TryForceFeatureScope(CpuFeature f)
406
+ : old_supported_(CpuFeatures::supported_) {
407
+ if (CanForce()) {
408
+ CpuFeatures::supported_ |= (1u << f);
409
+ }
410
+ }
411
+
412
+ ~TryForceFeatureScope() {
413
+ if (CanForce()) {
414
+ CpuFeatures::supported_ = old_supported_;
415
+ }
416
+ }
417
+
418
+ private:
419
+ static bool CanForce() {
420
+ // It's only safe to temporarily force support of CPU features
421
+ // when there's only a single isolate, which is guaranteed when
422
+ // the serializer is enabled.
423
+ return Serializer::enabled();
424
+ }
425
+
426
+ const unsigned old_supported_;
427
+ };
428
+
429
+ private:
430
+ #ifdef DEBUG
431
+ static bool initialized_;
432
+ #endif
433
+ static unsigned supported_;
434
+ static unsigned found_by_runtime_probing_;
435
+
436
+ DISALLOW_COPY_AND_ASSIGN(CpuFeatures);
437
+ };
438
+
439
+
440
+ class Assembler : public AssemblerBase {
441
+ public:
442
+ // Create an assembler. Instructions and relocation information are emitted
443
+ // into a buffer, with the instructions starting from the beginning and the
444
+ // relocation information starting from the end of the buffer. See CodeDesc
445
+ // for a detailed comment on the layout (globals.h).
446
+ //
447
+ // If the provided buffer is NULL, the assembler allocates and grows its own
448
+ // buffer, and buffer_size determines the initial buffer size. The buffer is
449
+ // owned by the assembler and deallocated upon destruction of the assembler.
450
+ //
451
+ // If the provided buffer is not NULL, the assembler uses the provided buffer
452
+ // for code generation and assumes its size to be buffer_size. If the buffer
453
+ // is too small, a fatal error occurs. No deallocation of the buffer is done
454
+ // upon destruction of the assembler.
455
+ Assembler(Isolate* isolate, void* buffer, int buffer_size);
456
+ ~Assembler();
457
+
458
+ // Overrides the default provided by FLAG_debug_code.
459
+ void set_emit_debug_code(bool value) { emit_debug_code_ = value; }
460
+
461
+ // GetCode emits any pending (non-emitted) code and fills the descriptor
462
+ // desc. GetCode() is idempotent; it returns the same result if no other
463
+ // Assembler functions are invoked in between GetCode() calls.
464
+ void GetCode(CodeDesc* desc);
465
+
466
+ // Label operations & relative jumps (PPUM Appendix D).
467
+ //
468
+ // Takes a branch opcode (cc) and a label (L) and generates
469
+ // either a backward branch or a forward branch and links it
470
+ // to the label fixup chain. Usage:
471
+ //
472
+ // Label L; // unbound label
473
+ // j(cc, &L); // forward branch to unbound label
474
+ // bind(&L); // bind label to the current pc
475
+ // j(cc, &L); // backward branch to bound label
476
+ // bind(&L); // illegal: a label may be bound only once
477
+ //
478
+ // Note: The same Label can be used for forward and backward branches
479
+ // but it may be bound only once.
480
+ void bind(Label* L); // Binds an unbound label L to current code position.
481
+
482
+ // Returns the branch offset to the given label from the current code
483
+ // position. Links the label to the current position if it is still unbound.
484
+ // Manages the jump elimination optimization if the second parameter is true.
485
+ int32_t branch_offset(Label* L, bool jump_elimination_allowed);
486
+ int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
487
+ int32_t o = branch_offset(L, jump_elimination_allowed);
488
+ ASSERT((o & 3) == 0); // Assert the offset is aligned.
489
+ return o >> 2;
490
+ }
491
+
492
+ // Puts a labels target address at the given position.
493
+ // The high 8 bits are set to zero.
494
+ void label_at_put(Label* L, int at_offset);
495
+
496
+ // Read/Modify the code target address in the branch/call instruction at pc.
497
+ static Address target_address_at(Address pc);
498
+ static void set_target_address_at(Address pc, Address target);
499
+
500
+ // This sets the branch destination (which gets loaded at the call address).
501
+ // This is for calls and branches within generated code.
502
+ inline static void set_target_at(Address instruction_payload,
503
+ Address target) {
504
+ set_target_address_at(instruction_payload, target);
505
+ }
506
+
507
+ // This sets the branch destination.
508
+ // This is for calls and branches to runtime code.
509
+ inline static void set_external_target_at(Address instruction_payload,
510
+ Address target) {
511
+ set_target_address_at(instruction_payload, target);
512
+ }
513
+
514
+ // Size of an instruction.
515
+ static const int kInstrSize = sizeof(Instr);
516
+
517
+ // Difference between address of current opcode and target address offset.
518
+ static const int kBranchPCOffset = 4;
519
+
520
+ // Here we are patching the address in the LUI/ORI instruction pair.
521
+ // These values are used in the serialization process and must be zero for
522
+ // MIPS platform, as Code, Embedded Object or External-reference pointers
523
+ // are split across two consecutive instructions and don't exist separately
524
+ // in the code, so the serializer should not step forwards in memory after
525
+ // a target is resolved and written.
526
+ static const int kCallTargetSize = 0 * kInstrSize;
527
+ static const int kExternalTargetSize = 0 * kInstrSize;
528
+
529
+ // Number of consecutive instructions used to store 32bit constant.
530
+ // Used in RelocInfo::target_address_address() function to tell serializer
531
+ // address of the instruction that follows LUI/ORI instruction pair.
532
+ static const int kInstructionsFor32BitConstant = 2;
533
+
534
+ // Distance between the instruction referring to the address of the call
535
+ // target and the return address.
536
+ static const int kCallTargetAddressOffset = 4 * kInstrSize;
537
+
538
+ // Distance between start of patched return sequence and the emitted address
539
+ // to jump to.
540
+ static const int kPatchReturnSequenceAddressOffset = 0;
541
+
542
+ // Distance between start of patched debug break slot and the emitted address
543
+ // to jump to.
544
+ static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
545
+
546
+ // Difference between address of current opcode and value read from pc
547
+ // register.
548
+ static const int kPcLoadDelta = 4;
549
+
550
+ // Number of instructions used for the JS return sequence. The constant is
551
+ // used by the debugger to patch the JS return sequence.
552
+ static const int kJSReturnSequenceInstructions = 7;
553
+ static const int kDebugBreakSlotInstructions = 4;
554
+ static const int kDebugBreakSlotLength =
555
+ kDebugBreakSlotInstructions * kInstrSize;
556
+
557
+
558
+ // ---------------------------------------------------------------------------
559
+ // Code generation.
560
+
561
+ // Insert the smallest number of nop instructions
562
+ // possible to align the pc offset to a multiple
563
+ // of m. m must be a power of 2 (>= 4).
564
+ void Align(int m);
565
+ // Aligns code to something that's optimal for a jump target for the platform.
566
+ void CodeTargetAlign();
567
+
568
+ // Different nop operations are used by the code generator to detect certain
569
+ // states of the generated code.
570
+ enum NopMarkerTypes {
571
+ NON_MARKING_NOP = 0,
572
+ DEBUG_BREAK_NOP,
573
+ // IC markers.
574
+ PROPERTY_ACCESS_INLINED,
575
+ PROPERTY_ACCESS_INLINED_CONTEXT,
576
+ PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
577
+ // Helper values.
578
+ LAST_CODE_MARKER,
579
+ FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED
580
+ };
581
+
582
+ // Type == 0 is the default non-marking type.
583
+ void nop(unsigned int type = 0) {
584
+ ASSERT(type < 32);
585
+ sll(zero_reg, zero_reg, type, true);
586
+ }
587
+
588
+
589
+ // --------Branch-and-jump-instructions----------
590
+ // We don't use likely variant of instructions.
591
+ void b(int16_t offset);
592
+ void b(Label* L) { b(branch_offset(L, false)>>2); }
593
+ void bal(int16_t offset);
594
+ void bal(Label* L) { bal(branch_offset(L, false)>>2); }
595
+
596
+ void beq(Register rs, Register rt, int16_t offset);
597
+ void beq(Register rs, Register rt, Label* L) {
598
+ beq(rs, rt, branch_offset(L, false) >> 2);
599
+ }
600
+ void bgez(Register rs, int16_t offset);
601
+ void bgezal(Register rs, int16_t offset);
602
+ void bgtz(Register rs, int16_t offset);
603
+ void blez(Register rs, int16_t offset);
604
+ void bltz(Register rs, int16_t offset);
605
+ void bltzal(Register rs, int16_t offset);
606
+ void bne(Register rs, Register rt, int16_t offset);
607
+ void bne(Register rs, Register rt, Label* L) {
608
+ bne(rs, rt, branch_offset(L, false)>>2);
609
+ }
610
+
611
+ // Never use the int16_t b(l)cond version with a branch offset
612
+ // instead of using the Label* version.
613
+
614
+ // Jump targets must be in the current 256 MB-aligned region. ie 28 bits.
615
+ void j(int32_t target);
616
+ void jal(int32_t target);
617
+ void jalr(Register rs, Register rd = ra);
618
+ void jr(Register target);
619
+
620
+
621
+ //-------Data-processing-instructions---------
622
+
623
+ // Arithmetic.
624
+ void addu(Register rd, Register rs, Register rt);
625
+ void subu(Register rd, Register rs, Register rt);
626
+ void mult(Register rs, Register rt);
627
+ void multu(Register rs, Register rt);
628
+ void div(Register rs, Register rt);
629
+ void divu(Register rs, Register rt);
630
+ void mul(Register rd, Register rs, Register rt);
631
+
632
+ void addiu(Register rd, Register rs, int32_t j);
633
+
634
+ // Logical.
635
+ void and_(Register rd, Register rs, Register rt);
636
+ void or_(Register rd, Register rs, Register rt);
637
+ void xor_(Register rd, Register rs, Register rt);
638
+ void nor(Register rd, Register rs, Register rt);
639
+
640
+ void andi(Register rd, Register rs, int32_t j);
641
+ void ori(Register rd, Register rs, int32_t j);
642
+ void xori(Register rd, Register rs, int32_t j);
643
+ void lui(Register rd, int32_t j);
644
+
645
+ // Shifts.
646
+ // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
647
+ // and may cause problems in normal code. coming_from_nop makes sure this
648
+ // doesn't happen.
649
+ void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
650
+ void sllv(Register rd, Register rt, Register rs);
651
+ void srl(Register rd, Register rt, uint16_t sa);
652
+ void srlv(Register rd, Register rt, Register rs);
653
+ void sra(Register rt, Register rd, uint16_t sa);
654
+ void srav(Register rt, Register rd, Register rs);
655
+ void rotr(Register rd, Register rt, uint16_t sa);
656
+ void rotrv(Register rd, Register rt, Register rs);
657
+
658
+
659
+ //------------Memory-instructions-------------
660
+
661
+ void lb(Register rd, const MemOperand& rs);
662
+ void lbu(Register rd, const MemOperand& rs);
663
+ void lh(Register rd, const MemOperand& rs);
664
+ void lhu(Register rd, const MemOperand& rs);
665
+ void lw(Register rd, const MemOperand& rs);
666
+ void lwl(Register rd, const MemOperand& rs);
667
+ void lwr(Register rd, const MemOperand& rs);
668
+ void sb(Register rd, const MemOperand& rs);
669
+ void sh(Register rd, const MemOperand& rs);
670
+ void sw(Register rd, const MemOperand& rs);
671
+ void swl(Register rd, const MemOperand& rs);
672
+ void swr(Register rd, const MemOperand& rs);
673
+
674
+
675
+ //-------------Misc-instructions--------------
676
+
677
+ // Break / Trap instructions.
678
+ void break_(uint32_t code);
679
+ void tge(Register rs, Register rt, uint16_t code);
680
+ void tgeu(Register rs, Register rt, uint16_t code);
681
+ void tlt(Register rs, Register rt, uint16_t code);
682
+ void tltu(Register rs, Register rt, uint16_t code);
683
+ void teq(Register rs, Register rt, uint16_t code);
684
+ void tne(Register rs, Register rt, uint16_t code);
685
+
686
+ // Move from HI/LO register.
687
+ void mfhi(Register rd);
688
+ void mflo(Register rd);
689
+
690
+ // Set on less than.
691
+ void slt(Register rd, Register rs, Register rt);
692
+ void sltu(Register rd, Register rs, Register rt);
693
+ void slti(Register rd, Register rs, int32_t j);
694
+ void sltiu(Register rd, Register rs, int32_t j);
695
+
696
+ // Conditional move.
697
+ void movz(Register rd, Register rs, Register rt);
698
+ void movn(Register rd, Register rs, Register rt);
699
+ void movt(Register rd, Register rs, uint16_t cc = 0);
700
+ void movf(Register rd, Register rs, uint16_t cc = 0);
701
+
702
+ // Bit twiddling.
703
+ void clz(Register rd, Register rs);
704
+ void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
705
+ void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
706
+
707
+ //--------Coprocessor-instructions----------------
708
+
709
+ // Load, store, and move.
710
+ void lwc1(FPURegister fd, const MemOperand& src);
711
+ void ldc1(FPURegister fd, const MemOperand& src);
712
+
713
+ void swc1(FPURegister fs, const MemOperand& dst);
714
+ void sdc1(FPURegister fs, const MemOperand& dst);
715
+
716
+ void mtc1(Register rt, FPURegister fs);
717
+ void mfc1(Register rt, FPURegister fs);
718
+
719
+ void ctc1(Register rt, FPUControlRegister fs);
720
+ void cfc1(Register rt, FPUControlRegister fs);
721
+
722
+ // Arithmetic.
723
+ void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
724
+ void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
725
+ void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
726
+ void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
727
+ void abs_d(FPURegister fd, FPURegister fs);
728
+ void mov_d(FPURegister fd, FPURegister fs);
729
+ void neg_d(FPURegister fd, FPURegister fs);
730
+ void sqrt_d(FPURegister fd, FPURegister fs);
731
+
732
+ // Conversion.
733
+ void cvt_w_s(FPURegister fd, FPURegister fs);
734
+ void cvt_w_d(FPURegister fd, FPURegister fs);
735
+ void trunc_w_s(FPURegister fd, FPURegister fs);
736
+ void trunc_w_d(FPURegister fd, FPURegister fs);
737
+ void round_w_s(FPURegister fd, FPURegister fs);
738
+ void round_w_d(FPURegister fd, FPURegister fs);
739
+ void floor_w_s(FPURegister fd, FPURegister fs);
740
+ void floor_w_d(FPURegister fd, FPURegister fs);
741
+ void ceil_w_s(FPURegister fd, FPURegister fs);
742
+ void ceil_w_d(FPURegister fd, FPURegister fs);
743
+
744
+ void cvt_l_s(FPURegister fd, FPURegister fs);
745
+ void cvt_l_d(FPURegister fd, FPURegister fs);
746
+ void trunc_l_s(FPURegister fd, FPURegister fs);
747
+ void trunc_l_d(FPURegister fd, FPURegister fs);
748
+ void round_l_s(FPURegister fd, FPURegister fs);
749
+ void round_l_d(FPURegister fd, FPURegister fs);
750
+ void floor_l_s(FPURegister fd, FPURegister fs);
751
+ void floor_l_d(FPURegister fd, FPURegister fs);
752
+ void ceil_l_s(FPURegister fd, FPURegister fs);
753
+ void ceil_l_d(FPURegister fd, FPURegister fs);
754
+
755
+ void cvt_s_w(FPURegister fd, FPURegister fs);
756
+ void cvt_s_l(FPURegister fd, FPURegister fs);
757
+ void cvt_s_d(FPURegister fd, FPURegister fs);
758
+
759
+ void cvt_d_w(FPURegister fd, FPURegister fs);
760
+ void cvt_d_l(FPURegister fd, FPURegister fs);
761
+ void cvt_d_s(FPURegister fd, FPURegister fs);
762
+
763
+ // Conditions and branches.
764
+ void c(FPUCondition cond, SecondaryField fmt,
765
+ FPURegister ft, FPURegister fs, uint16_t cc = 0);
766
+
767
+ void bc1f(int16_t offset, uint16_t cc = 0);
768
+ void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
769
+ void bc1t(int16_t offset, uint16_t cc = 0);
770
+ void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
771
+ void fcmp(FPURegister src1, const double src2, FPUCondition cond);
772
+
773
+ // Check the code size generated from label to here.
774
+ int InstructionsGeneratedSince(Label* l) {
775
+ return (pc_offset() - l->pos()) / kInstrSize;
776
+ }
777
+
778
+ // Class for scoping postponing the trampoline pool generation.
779
+ class BlockTrampolinePoolScope {
780
+ public:
781
+ explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
782
+ assem_->StartBlockTrampolinePool();
783
+ }
784
+ ~BlockTrampolinePoolScope() {
785
+ assem_->EndBlockTrampolinePool();
786
+ }
787
+
788
+ private:
789
+ Assembler* assem_;
790
+
791
+ DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
792
+ };
793
+
794
+ // Debugging.
795
+
796
+ // Mark address of the ExitJSFrame code.
797
+ void RecordJSReturn();
798
+
799
+ // Mark address of a debug break slot.
800
+ void RecordDebugBreakSlot();
801
+
802
+ // Record the AST id of the CallIC being compiled, so that it can be placed
803
+ // in the relocation information.
804
+ void RecordAstId(unsigned ast_id) { ast_id_for_reloc_info_ = ast_id; }
805
+
806
+ // Record a comment relocation entry that can be used by a disassembler.
807
+ // Use --code-comments to enable.
808
+ void RecordComment(const char* msg);
809
+
810
+ // Writes a single byte or word of data in the code stream. Used for
811
+ // inline tables, e.g., jump-tables.
812
+ void db(uint8_t data);
813
+ void dd(uint32_t data);
814
+
815
+ int32_t pc_offset() const { return pc_ - buffer_; }
816
+
817
+ PositionsRecorder* positions_recorder() { return &positions_recorder_; }
818
+
819
+ // Postpone the generation of the trampoline pool for the specified number of
820
+ // instructions.
821
+ void BlockTrampolinePoolFor(int instructions);
822
+
823
+ // Check if there is less than kGap bytes available in the buffer.
824
+ // If this is the case, we need to grow the buffer before emitting
825
+ // an instruction or relocation information.
826
+ inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
827
+
828
+ // Get the number of bytes available in the buffer.
829
+ inline int available_space() const { return reloc_info_writer.pos() - pc_; }
830
+
831
+ // Read/patch instructions.
832
+ static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
833
+ static void instr_at_put(byte* pc, Instr instr) {
834
+ *reinterpret_cast<Instr*>(pc) = instr;
835
+ }
836
+ Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
837
+ void instr_at_put(int pos, Instr instr) {
838
+ *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
839
+ }
840
+
841
+ // Check if an instruction is a branch of some kind.
842
+ static bool IsBranch(Instr instr);
843
+ static bool IsBeq(Instr instr);
844
+ static bool IsBne(Instr instr);
845
+
846
+ static bool IsNop(Instr instr, unsigned int type);
847
+ static bool IsPop(Instr instr);
848
+ static bool IsPush(Instr instr);
849
+ static bool IsLwRegFpOffset(Instr instr);
850
+ static bool IsSwRegFpOffset(Instr instr);
851
+ static bool IsLwRegFpNegOffset(Instr instr);
852
+ static bool IsSwRegFpNegOffset(Instr instr);
853
+
854
+ static Register GetRtReg(Instr instr);
855
+ static Register GetRsReg(Instr instr);
856
+ static Register GetRdReg(Instr instr);
857
+
858
+ static uint32_t GetRt(Instr instr);
859
+ static uint32_t GetRtField(Instr instr);
860
+ static uint32_t GetRs(Instr instr);
861
+ static uint32_t GetRsField(Instr instr);
862
+ static uint32_t GetRd(Instr instr);
863
+ static uint32_t GetRdField(Instr instr);
864
+ static uint32_t GetSa(Instr instr);
865
+ static uint32_t GetSaField(Instr instr);
866
+ static uint32_t GetOpcodeField(Instr instr);
867
+ static uint32_t GetImmediate16(Instr instr);
868
+ static uint32_t GetLabelConst(Instr instr);
869
+
870
+ static int32_t GetBranchOffset(Instr instr);
871
+ static bool IsLw(Instr instr);
872
+ static int16_t GetLwOffset(Instr instr);
873
+ static Instr SetLwOffset(Instr instr, int16_t offset);
874
+
875
+ static bool IsSw(Instr instr);
876
+ static Instr SetSwOffset(Instr instr, int16_t offset);
877
+ static bool IsAddImmediate(Instr instr);
878
+ static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
879
+
880
+ static bool IsAndImmediate(Instr instr);
881
+
882
+ void CheckTrampolinePool(bool force_emit = false);
883
+
884
+ protected:
885
+ // Relocation for a type-recording IC has the AST id added to it. This
886
+ // member variable is a way to pass the information from the call site to
887
+ // the relocation info.
888
+ unsigned ast_id_for_reloc_info_;
889
+
890
+ bool emit_debug_code() const { return emit_debug_code_; }
891
+
892
+ int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
893
+
894
+ // Decode branch instruction at pos and return branch target pos.
895
+ int target_at(int32_t pos);
896
+
897
+ // Patch branch instruction at pos to branch to given branch target pos.
898
+ void target_at_put(int32_t pos, int32_t target_pos);
899
+
900
+ // Say if we need to relocate with this mode.
901
+ bool MustUseReg(RelocInfo::Mode rmode);
902
+
903
+ // Record reloc info for current pc_.
904
+ void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
905
+
906
+ // Block the emission of the trampoline pool before pc_offset.
907
+ void BlockTrampolinePoolBefore(int pc_offset) {
908
+ if (no_trampoline_pool_before_ < pc_offset)
909
+ no_trampoline_pool_before_ = pc_offset;
910
+ }
911
+
912
+ void StartBlockTrampolinePool() {
913
+ trampoline_pool_blocked_nesting_++;
914
+ }
915
+ void EndBlockTrampolinePool() {
916
+ trampoline_pool_blocked_nesting_--;
917
+ }
918
+
919
+ bool is_trampoline_pool_blocked() const {
920
+ return trampoline_pool_blocked_nesting_ > 0;
921
+ }
922
+
923
+ bool has_exception() const {
924
+ return internal_trampoline_exception_;
925
+ }
926
+
927
+ private:
928
+ // Code buffer:
929
+ // The buffer into which code and relocation info are generated.
930
+ byte* buffer_;
931
+ int buffer_size_;
932
+ // True if the assembler owns the buffer, false if buffer is external.
933
+ bool own_buffer_;
934
+
935
+ // Buffer size and constant pool distance are checked together at regular
936
+ // intervals of kBufferCheckInterval emitted bytes.
937
+ static const int kBufferCheckInterval = 1*KB/2;
938
+
939
+ // Code generation.
940
+ // The relocation writer's position is at least kGap bytes below the end of
941
+ // the generated instructions. This is so that multi-instruction sequences do
942
+ // not have to check for overflow. The same is true for writes of large
943
+ // relocation info entries.
944
+ static const int kGap = 32;
945
+ byte* pc_; // The program counter - moves forward.
946
+
947
+
948
+ // Repeated checking whether the trampoline pool should be emitted is rather
949
+ // expensive. By default we only check again once a number of instructions
950
+ // has been generated.
951
+ static const int kCheckConstIntervalInst = 32;
952
+ static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
953
+
954
+ int next_buffer_check_; // pc offset of next buffer check.
955
+
956
+ // Emission of the trampoline pool may be blocked in some code sequences.
957
+ int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
958
+ int no_trampoline_pool_before_; // Block emission before this pc offset.
959
+
960
+ // Keep track of the last emitted pool to guarantee a maximal distance.
961
+ int last_trampoline_pool_end_; // pc offset of the end of the last pool.
962
+
963
+ // Relocation information generation.
964
+ // Each relocation is encoded as a variable size value.
965
+ static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
966
+ RelocInfoWriter reloc_info_writer;
967
+
968
+ // The bound position, before this we cannot do instruction elimination.
969
+ int last_bound_pos_;
970
+
971
+ // Code emission.
972
+ inline void CheckBuffer();
973
+ void GrowBuffer();
974
+ inline void emit(Instr x);
975
+ inline void CheckTrampolinePoolQuick();
976
+
977
+ // Instruction generation.
978
+ // We have 3 different kind of encoding layout on MIPS.
979
+ // However due to many different types of objects encoded in the same fields
980
+ // we have quite a few aliases for each mode.
981
+ // Using the same structure to refer to Register and FPURegister would spare a
982
+ // few aliases, but mixing both does not look clean to me.
983
+ // Anyway we could surely implement this differently.
984
+
985
+ void GenInstrRegister(Opcode opcode,
986
+ Register rs,
987
+ Register rt,
988
+ Register rd,
989
+ uint16_t sa = 0,
990
+ SecondaryField func = NULLSF);
991
+
992
+ void GenInstrRegister(Opcode opcode,
993
+ Register rs,
994
+ Register rt,
995
+ uint16_t msb,
996
+ uint16_t lsb,
997
+ SecondaryField func);
998
+
999
+ void GenInstrRegister(Opcode opcode,
1000
+ SecondaryField fmt,
1001
+ FPURegister ft,
1002
+ FPURegister fs,
1003
+ FPURegister fd,
1004
+ SecondaryField func = NULLSF);
1005
+
1006
+ void GenInstrRegister(Opcode opcode,
1007
+ SecondaryField fmt,
1008
+ Register rt,
1009
+ FPURegister fs,
1010
+ FPURegister fd,
1011
+ SecondaryField func = NULLSF);
1012
+
1013
+ void GenInstrRegister(Opcode opcode,
1014
+ SecondaryField fmt,
1015
+ Register rt,
1016
+ FPUControlRegister fs,
1017
+ SecondaryField func = NULLSF);
1018
+
1019
+
1020
+ void GenInstrImmediate(Opcode opcode,
1021
+ Register rs,
1022
+ Register rt,
1023
+ int32_t j);
1024
+ void GenInstrImmediate(Opcode opcode,
1025
+ Register rs,
1026
+ SecondaryField SF,
1027
+ int32_t j);
1028
+ void GenInstrImmediate(Opcode opcode,
1029
+ Register r1,
1030
+ FPURegister r2,
1031
+ int32_t j);
1032
+
1033
+
1034
+ void GenInstrJump(Opcode opcode,
1035
+ uint32_t address);
1036
+
1037
+ // Helpers.
1038
+ void LoadRegPlusOffsetToAt(const MemOperand& src);
1039
+
1040
+ // Labels.
1041
+ void print(Label* L);
1042
+ void bind_to(Label* L, int pos);
1043
+ void link_to(Label* L, Label* appendix);
1044
+ void next(Label* L);
1045
+
1046
+ // One trampoline consists of:
1047
+ // - space for trampoline slots,
1048
+ // - space for labels.
1049
+ //
1050
+ // Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
1051
+ // Space for trampoline slots preceeds space for labels. Each label is of one
1052
+ // instruction size, so total amount for labels is equal to
1053
+ // label_count * kInstrSize.
1054
+ class Trampoline {
1055
+ public:
1056
+ Trampoline(int start, int slot_count, int label_count) {
1057
+ start_ = start;
1058
+ next_slot_ = start;
1059
+ free_slot_count_ = slot_count;
1060
+ next_label_ = start + slot_count * 2 * kInstrSize;
1061
+ free_label_count_ = label_count;
1062
+ end_ = next_label_ + (label_count - 1) * kInstrSize;
1063
+ }
1064
+ int start() {
1065
+ return start_;
1066
+ }
1067
+ int end() {
1068
+ return end_;
1069
+ }
1070
+ int take_slot() {
1071
+ int trampoline_slot = kInvalidSlotPos;
1072
+ if (free_slot_count_ <= 0) {
1073
+ // We have run out of space on trampolines.
1074
+ // Make sure we fail in debug mode, so we become aware of each case
1075
+ // when this happens.
1076
+ ASSERT(0);
1077
+ // Internal exception will be caught.
1078
+ } else {
1079
+ trampoline_slot = next_slot_;
1080
+ free_slot_count_--;
1081
+ next_slot_ += 2*kInstrSize;
1082
+ }
1083
+ return trampoline_slot;
1084
+ }
1085
+ int take_label() {
1086
+ int label_pos = next_label_;
1087
+ ASSERT(free_label_count_ > 0);
1088
+ free_label_count_--;
1089
+ next_label_ += kInstrSize;
1090
+ return label_pos;
1091
+ }
1092
+ private:
1093
+ int start_;
1094
+ int end_;
1095
+ int next_slot_;
1096
+ int free_slot_count_;
1097
+ int next_label_;
1098
+ int free_label_count_;
1099
+ };
1100
+
1101
+ int32_t get_label_entry(int32_t pos, bool next_pool = true);
1102
+ int32_t get_trampoline_entry(int32_t pos, bool next_pool = true);
1103
+
1104
+ static const int kSlotsPerTrampoline = 2304;
1105
+ static const int kLabelsPerTrampoline = 8;
1106
+ static const int kTrampolineInst =
1107
+ 2 * kSlotsPerTrampoline + kLabelsPerTrampoline;
1108
+ static const int kTrampolineSize = kTrampolineInst * kInstrSize;
1109
+ static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
1110
+ static const int kMaxDistBetweenPools =
1111
+ kMaxBranchOffset - 2 * kTrampolineSize;
1112
+ static const int kInvalidSlotPos = -1;
1113
+
1114
+ List<Trampoline> trampolines_;
1115
+ bool internal_trampoline_exception_;
1116
+
1117
+ friend class RegExpMacroAssemblerMIPS;
1118
+ friend class RelocInfo;
1119
+ friend class CodePatcher;
1120
+ friend class BlockTrampolinePoolScope;
1121
+
1122
+ PositionsRecorder positions_recorder_;
1123
+ bool emit_debug_code_;
1124
+ friend class PositionsRecorder;
1125
+ friend class EnsureSpace;
1126
+ };
1127
+
1128
+
1129
+ class EnsureSpace BASE_EMBEDDED {
1130
+ public:
1131
+ explicit EnsureSpace(Assembler* assembler) {
1132
+ assembler->CheckBuffer();
1133
+ }
1134
+ };
1135
+
1136
+ } } // namespace v8::internal
1137
+
1138
+ #endif // V8_ARM_ASSEMBLER_MIPS_H_