html-to-markdown 2.28.0 → 2.28.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/Gemfile.lock +6 -6
- data/README.md +5 -1
- data/ext/html-to-markdown-rb/native/Cargo.lock +1694 -0
- data/ext/html-to-markdown-rb/native/Cargo.toml +1 -1
- data/lib/html_to_markdown/version.rb +1 -1
- data/rust-vendor/html-to-markdown-rs/Cargo.toml +1 -1
- data/rust-vendor/html-to-markdown-rs/src/converter/text_node.rs +1 -0
- data/rust-vendor/html-to-markdown-rs/src/converter/utility/content.rs +17 -0
- data/rust-vendor/html-to-markdown-rs/src/converter/visitor_hooks.rs +8 -5
- data/rust-vendor/html-to-markdown-rs/tests/test_issue_218.rs +56 -0
- data/rust-vendor/libc/.cargo-checksum.json +1 -1
- data/rust-vendor/libc/.cargo_vcs_info.json +1 -1
- data/rust-vendor/libc/CHANGELOG.md +19 -0
- data/rust-vendor/libc/Cargo.lock +1 -1
- data/rust-vendor/libc/Cargo.toml +1 -1
- data/rust-vendor/libc/Cargo.toml.orig +1 -1
- data/rust-vendor/libc/build.rs +3 -3
- data/rust-vendor/libc/src/fuchsia/mod.rs +2 -0
- data/rust-vendor/libc/src/hermit.rs +1 -0
- data/rust-vendor/libc/src/lib.rs +1 -0
- data/rust-vendor/libc/src/new/linux_uapi/linux/mod.rs +1 -0
- data/rust-vendor/libc/src/new/linux_uapi/linux/pidfd.rs +59 -0
- data/rust-vendor/libc/src/new/mod.rs +3 -0
- data/rust-vendor/libc/src/new/netbsd/sys/file.rs +16 -0
- data/rust-vendor/libc/src/new/netbsd/sys/mod.rs +2 -0
- data/rust-vendor/libc/src/new/netbsd/sys/socket.rs +44 -0
- data/rust-vendor/libc/src/new/qurt/mod.rs +2 -0
- data/rust-vendor/libc/src/solid/mod.rs +1 -0
- data/rust-vendor/libc/src/switch.rs +1 -0
- data/rust-vendor/libc/src/teeos/mod.rs +2 -0
- data/rust-vendor/libc/src/trusty.rs +1 -0
- data/rust-vendor/libc/src/unix/bsd/apple/b64/mod.rs +1 -0
- data/rust-vendor/libc/src/unix/bsd/netbsdlike/netbsd/mod.rs +31 -0
- data/rust-vendor/libc/src/unix/bsd/netbsdlike/openbsd/mod.rs +92 -0
- data/rust-vendor/libc/src/unix/hurd/mod.rs +1 -0
- data/rust-vendor/libc/src/unix/linux_like/linux/gnu/mod.rs +1 -0
- data/rust-vendor/libc/src/unix/linux_like/linux/mod.rs +22 -46
- data/rust-vendor/libc/src/unix/mod.rs +2 -0
- data/rust-vendor/libc/src/unix/newlib/espidf/mod.rs +2 -0
- data/rust-vendor/libc/src/unix/redox/mod.rs +2 -2
- data/rust-vendor/libc/src/vxworks/mod.rs +46 -0
- data/rust-vendor/libc/src/wasi/mod.rs +2 -0
- data/rust-vendor/libc/src/windows/mod.rs +2 -0
- data/rust-vendor/uuid/.cargo-checksum.json +1 -1
- data/rust-vendor/uuid/.cargo_vcs_info.json +1 -1
- data/rust-vendor/uuid/Cargo.lock +71 -137
- data/rust-vendor/uuid/Cargo.toml +4 -4
- data/rust-vendor/uuid/Cargo.toml.orig +4 -4
- data/rust-vendor/uuid/README.md +3 -3
- data/rust-vendor/uuid/src/lib.rs +4 -4
- data/rust-vendor/zerocopy/.cargo-checksum.json +1 -1
- data/rust-vendor/zerocopy/.cargo_vcs_info.json +1 -1
- data/rust-vendor/zerocopy/Cargo.lock +3 -3
- data/rust-vendor/zerocopy/Cargo.toml +178 -4
- data/rust-vendor/zerocopy/Cargo.toml.orig +5 -5
- data/rust-vendor/zerocopy/benches/formats/coco_dynamic_padding.rs +24 -0
- data/rust-vendor/zerocopy/benches/formats/coco_dynamic_size.rs +23 -0
- data/rust-vendor/zerocopy/benches/formats/coco_static_size.rs +23 -0
- data/rust-vendor/zerocopy/benches/read_from_bytes.rs +7 -0
- data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64 +15 -0
- data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64.mca +65 -0
- data/rust-vendor/zerocopy/benches/read_from_prefix.rs +10 -0
- data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64 +14 -0
- data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64.mca +63 -0
- data/rust-vendor/zerocopy/benches/read_from_suffix.rs +10 -0
- data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64 +15 -0
- data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64.mca +65 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.rs +7 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64 +20 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64.mca +75 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64 +8 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64.mca +53 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64 +30 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +95 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64 +16 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64.mca +65 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64 +17 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64.mca +67 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64 +8 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64.mca +53 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64 +23 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64.mca +79 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64 +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64.mca +63 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64 +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64.mca +61 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64 +34 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +99 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64 +23 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/transmute.rs +16 -0
- data/rust-vendor/zerocopy/benches/transmute.x86-64 +3 -0
- data/rust-vendor/zerocopy/benches/transmute.x86-64.mca +43 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.rs +16 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64 +4 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64.mca +45 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_static_size.rs +15 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64 +3 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64.mca +43 -0
- data/rust-vendor/zerocopy/benches/try_read_from_bytes.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64 +23 -0
- data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64.mca +79 -0
- data/rust-vendor/zerocopy/benches/try_read_from_prefix.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64 +16 -0
- data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64.mca +67 -0
- data/rust-vendor/zerocopy/benches/try_read_from_suffix.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64 +18 -0
- data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64.mca +71 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64 +24 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64.mca +81 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64.mca +79 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64 +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64.mca +59 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64 +36 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +105 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64 +18 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64.mca +69 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64 +29 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64.mca +91 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64 +15 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64.mca +63 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64 +26 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64.mca +83 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64 +26 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64.mca +85 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64 +18 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64.mca +71 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64 +16 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64.mca +67 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64 +39 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +109 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64 +28 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64.mca +87 -0
- data/rust-vendor/zerocopy/benches/try_transmute.rs +16 -0
- data/rust-vendor/zerocopy/benches/try_transmute.x86-64 +9 -0
- data/rust-vendor/zerocopy/benches/try_transmute.x86-64.mca +55 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.rs +18 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64 +6 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64.mca +49 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.rs +17 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64 +5 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64.mca +47 -0
- data/rust-vendor/zerocopy/rustdoc/style.css +55 -0
- data/rust-vendor/zerocopy/src/lib.rs +331 -0
- data/rust-vendor/zerocopy/src/macros.rs +48 -1
- data/rust-vendor/zerocopy/src/util/macros.rs +199 -0
- data/rust-vendor/zerocopy/tests/codegen.rs +111 -0
- data/rust-vendor/zerocopy-derive/.cargo-checksum.json +1 -1
- data/rust-vendor/zerocopy-derive/.cargo_vcs_info.json +1 -1
- data/rust-vendor/zerocopy-derive/Cargo.lock +1 -1
- data/rust-vendor/zerocopy-derive/Cargo.toml +1 -1
- data/rust-vendor/zerocopy-derive/Cargo.toml.orig +1 -1
- metadata +138 -2
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Iterations: 100
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Instructions: 1300
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Total Cycles: 377
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Total uOps: 1400
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6
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Dispatch Width: 4
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uOps Per Cycle: 3.71
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IPC: 3.45
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9
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Block RThroughput: 3.5
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Instruction Info:
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[1]: #uOps
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[2]: Latency
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[3]: RThroughput
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[4]: MayLoad
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[5]: MayStore
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[6]: HasSideEffects (U)
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[1] [2] [3] [4] [5] [6] Instructions:
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1 1 0.33 mov rcx, rsi
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1 1 0.33 cmp rsi, 6
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1 1 1.00 jb .LBB5_2
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1 5 0.50 * mov eax, dword ptr [rdi + rsi - 6]
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1 5 0.50 * movzx ecx, word ptr [rdi + rsi - 2]
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1 1 0.50 shl rcx, 32
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1 1 0.33 or rcx, rax
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1 1 0.50 shl rcx, 16
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1 1 0.33 inc rcx
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1 0 0.25 xor eax, eax
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1 1 0.33 cmp rsi, 6
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32
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2 2 0.67 cmovae rax, rcx
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1 1 1.00 U ret
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Resources:
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[0] - SBDivider
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[1] - SBFPDivider
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[2] - SBPort0
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[3] - SBPort1
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[4] - SBPort4
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[5] - SBPort5
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[6.0] - SBPort23
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[6.1] - SBPort23
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45
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46
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47
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Resource pressure per iteration:
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48
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[0] [1] [2] [3] [4] [5] [6.0] [6.1]
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- - 3.66 3.67 - 3.67 1.00 1.00
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Resource pressure by instruction:
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[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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- - 0.63 0.36 - 0.01 - - mov rcx, rsi
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- - 0.05 0.05 - 0.90 - - cmp rsi, 6
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- - - - - 1.00 - - jb .LBB5_2
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- - - - - - - 1.00 mov eax, dword ptr [rdi + rsi - 6]
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- - - - - - 1.00 - movzx ecx, word ptr [rdi + rsi - 2]
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58
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- - 0.97 - - 0.03 - - shl rcx, 32
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59
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- - 0.02 0.35 - 0.63 - - or rcx, rax
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60
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- - 0.98 - - 0.02 - - shl rcx, 16
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61
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- - - 0.98 - 0.02 - - inc rcx
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62
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- - - - - - - - xor eax, eax
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63
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- - 0.03 0.93 - 0.04 - - cmp rsi, 6
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64
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- - 0.98 1.00 - 0.02 - - cmovae rax, rcx
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65
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- - - - - 1.00 - - ret
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bench_ref_from_bytes_dynamic_padding:
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test dil, 3
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3
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jne .LBB5_3
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4
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movabs rax, 9223372036854775804
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5
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and rax, rsi
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6
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cmp rax, 9
|
|
7
|
+
jb .LBB5_3
|
|
8
|
+
add rax, -9
|
|
9
|
+
movabs rcx, -6148914691236517205
|
|
10
|
+
mul rcx
|
|
11
|
+
shr rdx
|
|
12
|
+
lea rax, [rdx + 2*rdx]
|
|
13
|
+
or rax, 3
|
|
14
|
+
add rax, 9
|
|
15
|
+
cmp rsi, rax
|
|
16
|
+
je .LBB5_4
|
|
17
|
+
.LBB5_3:
|
|
18
|
+
xor edi, edi
|
|
19
|
+
mov rdx, rsi
|
|
20
|
+
.LBB5_4:
|
|
21
|
+
mov rax, rdi
|
|
22
|
+
ret
|
|
@@ -0,0 +1,77 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 1900
|
|
3
|
+
Total Cycles: 645
|
|
4
|
+
Total uOps: 2000
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.10
|
|
8
|
+
IPC: 2.95
|
|
9
|
+
Block RThroughput: 5.0
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 test dil, 3
|
|
22
|
+
1 1 1.00 jne .LBB5_3
|
|
23
|
+
1 1 0.33 movabs rax, 9223372036854775804
|
|
24
|
+
1 1 0.33 and rax, rsi
|
|
25
|
+
1 1 0.33 cmp rax, 9
|
|
26
|
+
1 1 1.00 jb .LBB5_3
|
|
27
|
+
1 1 0.33 add rax, -9
|
|
28
|
+
1 1 0.33 movabs rcx, -6148914691236517205
|
|
29
|
+
2 4 1.00 mul rcx
|
|
30
|
+
1 1 0.50 shr rdx
|
|
31
|
+
1 1 0.50 lea rax, [rdx + 2*rdx]
|
|
32
|
+
1 1 0.33 or rax, 3
|
|
33
|
+
1 1 0.33 add rax, 9
|
|
34
|
+
1 1 0.33 cmp rsi, rax
|
|
35
|
+
1 1 1.00 je .LBB5_4
|
|
36
|
+
1 0 0.25 xor edi, edi
|
|
37
|
+
1 1 0.33 mov rdx, rsi
|
|
38
|
+
1 1 0.33 mov rax, rdi
|
|
39
|
+
1 1 1.00 U ret
|
|
40
|
+
|
|
41
|
+
|
|
42
|
+
Resources:
|
|
43
|
+
[0] - SBDivider
|
|
44
|
+
[1] - SBFPDivider
|
|
45
|
+
[2] - SBPort0
|
|
46
|
+
[3] - SBPort1
|
|
47
|
+
[4] - SBPort4
|
|
48
|
+
[5] - SBPort5
|
|
49
|
+
[6.0] - SBPort23
|
|
50
|
+
[6.1] - SBPort23
|
|
51
|
+
|
|
52
|
+
|
|
53
|
+
Resource pressure per iteration:
|
|
54
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
55
|
+
- - 6.32 6.33 - 6.35 - -
|
|
56
|
+
|
|
57
|
+
Resource pressure by instruction:
|
|
58
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
59
|
+
- - 0.64 0.35 - 0.01 - - test dil, 3
|
|
60
|
+
- - - - - 1.00 - - jne .LBB5_3
|
|
61
|
+
- - 0.34 0.65 - 0.01 - - movabs rax, 9223372036854775804
|
|
62
|
+
- - 0.35 0.65 - - - - and rax, rsi
|
|
63
|
+
- - 0.33 0.34 - 0.33 - - cmp rax, 9
|
|
64
|
+
- - - - - 1.00 - - jb .LBB5_3
|
|
65
|
+
- - 0.35 - - 0.65 - - add rax, -9
|
|
66
|
+
- - 0.97 0.01 - 0.02 - - movabs rcx, -6148914691236517205
|
|
67
|
+
- - 1.00 1.00 - - - - mul rcx
|
|
68
|
+
- - 0.99 - - 0.01 - - shr rdx
|
|
69
|
+
- - 0.33 0.67 - - - - lea rax, [rdx + 2*rdx]
|
|
70
|
+
- - 0.34 0.66 - - - - or rax, 3
|
|
71
|
+
- - 0.33 0.66 - 0.01 - - add rax, 9
|
|
72
|
+
- - 0.01 0.99 - - - - cmp rsi, rax
|
|
73
|
+
- - - - - 1.00 - - je .LBB5_4
|
|
74
|
+
- - - - - - - - xor edi, edi
|
|
75
|
+
- - 0.32 0.01 - 0.67 - - mov rdx, rsi
|
|
76
|
+
- - 0.02 0.34 - 0.64 - - mov rax, rdi
|
|
77
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,20 @@
|
|
|
1
|
+
bench_ref_from_bytes_dynamic_size:
|
|
2
|
+
mov rdx, rsi
|
|
3
|
+
cmp rsi, 4
|
|
4
|
+
setb al
|
|
5
|
+
or al, dil
|
|
6
|
+
test al, 1
|
|
7
|
+
je .LBB5_2
|
|
8
|
+
xor eax, eax
|
|
9
|
+
ret
|
|
10
|
+
.LBB5_2:
|
|
11
|
+
lea rcx, [rdx - 4]
|
|
12
|
+
mov rsi, rcx
|
|
13
|
+
and rsi, -2
|
|
14
|
+
add rsi, 4
|
|
15
|
+
shr rcx
|
|
16
|
+
xor eax, eax
|
|
17
|
+
cmp rdx, rsi
|
|
18
|
+
cmove rdx, rcx
|
|
19
|
+
cmove rax, rdi
|
|
20
|
+
ret
|
|
@@ -0,0 +1,75 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 1800
|
|
3
|
+
Total Cycles: 704
|
|
4
|
+
Total uOps: 2000
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 2.84
|
|
8
|
+
IPC: 2.56
|
|
9
|
+
Block RThroughput: 5.0
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 mov rdx, rsi
|
|
22
|
+
1 1 0.33 cmp rsi, 4
|
|
23
|
+
1 1 0.50 setb al
|
|
24
|
+
1 1 0.33 or al, dil
|
|
25
|
+
1 1 0.33 test al, 1
|
|
26
|
+
1 1 1.00 je .LBB5_2
|
|
27
|
+
1 0 0.25 xor eax, eax
|
|
28
|
+
1 1 1.00 U ret
|
|
29
|
+
1 1 0.50 lea rcx, [rdx - 4]
|
|
30
|
+
1 1 0.33 mov rsi, rcx
|
|
31
|
+
1 1 0.33 and rsi, -2
|
|
32
|
+
1 1 0.33 add rsi, 4
|
|
33
|
+
1 1 0.50 shr rcx
|
|
34
|
+
1 0 0.25 xor eax, eax
|
|
35
|
+
1 1 0.33 cmp rdx, rsi
|
|
36
|
+
2 2 0.67 cmove rdx, rcx
|
|
37
|
+
2 2 0.67 cmove rax, rdi
|
|
38
|
+
1 1 1.00 U ret
|
|
39
|
+
|
|
40
|
+
|
|
41
|
+
Resources:
|
|
42
|
+
[0] - SBDivider
|
|
43
|
+
[1] - SBFPDivider
|
|
44
|
+
[2] - SBPort0
|
|
45
|
+
[3] - SBPort1
|
|
46
|
+
[4] - SBPort4
|
|
47
|
+
[5] - SBPort5
|
|
48
|
+
[6.0] - SBPort23
|
|
49
|
+
[6.1] - SBPort23
|
|
50
|
+
|
|
51
|
+
|
|
52
|
+
Resource pressure per iteration:
|
|
53
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
54
|
+
- - 5.97 5.98 - 6.05 - -
|
|
55
|
+
|
|
56
|
+
Resource pressure by instruction:
|
|
57
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
58
|
+
- - 0.97 0.01 - 0.02 - - mov rdx, rsi
|
|
59
|
+
- - 0.01 0.02 - 0.97 - - cmp rsi, 4
|
|
60
|
+
- - 0.03 - - 0.97 - - setb al
|
|
61
|
+
- - 0.01 0.02 - 0.97 - - or al, dil
|
|
62
|
+
- - - 0.98 - 0.02 - - test al, 1
|
|
63
|
+
- - - - - 1.00 - - je .LBB5_2
|
|
64
|
+
- - - - - - - - xor eax, eax
|
|
65
|
+
- - - - - 1.00 - - ret
|
|
66
|
+
- - 0.98 0.02 - - - - lea rcx, [rdx - 4]
|
|
67
|
+
- - 0.01 0.99 - - - - mov rsi, rcx
|
|
68
|
+
- - - 0.98 - 0.02 - - and rsi, -2
|
|
69
|
+
- - 0.98 0.01 - 0.01 - - add rsi, 4
|
|
70
|
+
- - 0.99 - - 0.01 - - shr rcx
|
|
71
|
+
- - - - - - - - xor eax, eax
|
|
72
|
+
- - 0.02 0.97 - 0.01 - - cmp rdx, rsi
|
|
73
|
+
- - 0.99 0.99 - 0.02 - - cmove rdx, rcx
|
|
74
|
+
- - 0.98 0.99 - 0.03 - - cmove rax, rdi
|
|
75
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,53 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 700
|
|
3
|
+
Total Cycles: 240
|
|
4
|
+
Total uOps: 800
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.33
|
|
8
|
+
IPC: 2.92
|
|
9
|
+
Block RThroughput: 2.0
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 mov ecx, edi
|
|
22
|
+
1 1 0.33 and ecx, 1
|
|
23
|
+
1 1 0.33 xor rsi, 6
|
|
24
|
+
1 0 0.25 xor eax, eax
|
|
25
|
+
1 1 0.33 or rsi, rcx
|
|
26
|
+
2 2 0.67 cmove rax, rdi
|
|
27
|
+
1 1 1.00 U ret
|
|
28
|
+
|
|
29
|
+
|
|
30
|
+
Resources:
|
|
31
|
+
[0] - SBDivider
|
|
32
|
+
[1] - SBFPDivider
|
|
33
|
+
[2] - SBPort0
|
|
34
|
+
[3] - SBPort1
|
|
35
|
+
[4] - SBPort4
|
|
36
|
+
[5] - SBPort5
|
|
37
|
+
[6.0] - SBPort23
|
|
38
|
+
[6.1] - SBPort23
|
|
39
|
+
|
|
40
|
+
|
|
41
|
+
Resource pressure per iteration:
|
|
42
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
43
|
+
- - 2.33 2.33 - 2.34 - -
|
|
44
|
+
|
|
45
|
+
Resource pressure by instruction:
|
|
46
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
47
|
+
- - 0.01 0.98 - 0.01 - - mov ecx, edi
|
|
48
|
+
- - 0.02 0.66 - 0.32 - - and ecx, 1
|
|
49
|
+
- - 0.33 0.66 - 0.01 - - xor rsi, 6
|
|
50
|
+
- - - - - - - - xor eax, eax
|
|
51
|
+
- - 0.98 0.02 - - - - or rsi, rcx
|
|
52
|
+
- - 0.99 0.01 - 1.00 - - cmove rax, rdi
|
|
53
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,10 @@
|
|
|
1
|
+
#[path = "formats/coco_dynamic_padding.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_ref_from_bytes_with_elems_dynamic_padding(
|
|
6
|
+
source: &[u8],
|
|
7
|
+
count: usize,
|
|
8
|
+
) -> Option<&format::LocoPacket> {
|
|
9
|
+
zerocopy::FromBytes::ref_from_bytes_with_elems(source, count).ok()
|
|
10
|
+
}
|
|
@@ -0,0 +1,30 @@
|
|
|
1
|
+
bench_ref_from_bytes_with_elems_dynamic_padding:
|
|
2
|
+
mov rcx, rdx
|
|
3
|
+
mov edx, 3
|
|
4
|
+
mov rax, rcx
|
|
5
|
+
mul rdx
|
|
6
|
+
jo .LBB5_5
|
|
7
|
+
cmp rax, -10
|
|
8
|
+
ja .LBB5_5
|
|
9
|
+
mov edx, eax
|
|
10
|
+
not edx
|
|
11
|
+
and edx, 3
|
|
12
|
+
add rdx, rax
|
|
13
|
+
add rdx, 9
|
|
14
|
+
cmp rsi, rdx
|
|
15
|
+
jne .LBB5_5
|
|
16
|
+
mov r8d, edi
|
|
17
|
+
and r8d, 3
|
|
18
|
+
jne .LBB5_5
|
|
19
|
+
add rax, 9
|
|
20
|
+
cmp rdx, rax
|
|
21
|
+
jb .LBB5_5
|
|
22
|
+
mov rax, rdi
|
|
23
|
+
mov rdx, rcx
|
|
24
|
+
ret
|
|
25
|
+
.LBB5_5:
|
|
26
|
+
xor edi, edi
|
|
27
|
+
mov rcx, rsi
|
|
28
|
+
mov rax, rdi
|
|
29
|
+
mov rdx, rcx
|
|
30
|
+
ret
|
|
@@ -0,0 +1,95 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 2800
|
|
3
|
+
Total Cycles: 944
|
|
4
|
+
Total uOps: 2900
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.07
|
|
8
|
+
IPC: 2.97
|
|
9
|
+
Block RThroughput: 7.3
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 mov rcx, rdx
|
|
22
|
+
1 1 0.33 mov edx, 3
|
|
23
|
+
1 1 0.33 mov rax, rcx
|
|
24
|
+
2 4 1.00 mul rdx
|
|
25
|
+
1 1 1.00 jo .LBB5_5
|
|
26
|
+
1 1 0.33 cmp rax, -10
|
|
27
|
+
1 1 1.00 ja .LBB5_5
|
|
28
|
+
1 1 0.33 mov edx, eax
|
|
29
|
+
1 1 0.33 not edx
|
|
30
|
+
1 1 0.33 and edx, 3
|
|
31
|
+
1 1 0.33 add rdx, rax
|
|
32
|
+
1 1 0.33 add rdx, 9
|
|
33
|
+
1 1 0.33 cmp rsi, rdx
|
|
34
|
+
1 1 1.00 jne .LBB5_5
|
|
35
|
+
1 1 0.33 mov r8d, edi
|
|
36
|
+
1 1 0.33 and r8d, 3
|
|
37
|
+
1 1 1.00 jne .LBB5_5
|
|
38
|
+
1 1 0.33 add rax, 9
|
|
39
|
+
1 1 0.33 cmp rdx, rax
|
|
40
|
+
1 1 1.00 jb .LBB5_5
|
|
41
|
+
1 1 0.33 mov rax, rdi
|
|
42
|
+
1 1 0.33 mov rdx, rcx
|
|
43
|
+
1 1 1.00 U ret
|
|
44
|
+
1 0 0.25 xor edi, edi
|
|
45
|
+
1 1 0.33 mov rcx, rsi
|
|
46
|
+
1 1 0.33 mov rax, rdi
|
|
47
|
+
1 1 0.33 mov rdx, rcx
|
|
48
|
+
1 1 1.00 U ret
|
|
49
|
+
|
|
50
|
+
|
|
51
|
+
Resources:
|
|
52
|
+
[0] - SBDivider
|
|
53
|
+
[1] - SBFPDivider
|
|
54
|
+
[2] - SBPort0
|
|
55
|
+
[3] - SBPort1
|
|
56
|
+
[4] - SBPort4
|
|
57
|
+
[5] - SBPort5
|
|
58
|
+
[6.0] - SBPort23
|
|
59
|
+
[6.1] - SBPort23
|
|
60
|
+
|
|
61
|
+
|
|
62
|
+
Resource pressure per iteration:
|
|
63
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
64
|
+
- - 9.32 9.32 - 9.36 - -
|
|
65
|
+
|
|
66
|
+
Resource pressure by instruction:
|
|
67
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
68
|
+
- - 0.64 0.18 - 0.18 - - mov rcx, rdx
|
|
69
|
+
- - 0.17 0.83 - - - - mov edx, 3
|
|
70
|
+
- - 0.50 0.49 - 0.01 - - mov rax, rcx
|
|
71
|
+
- - 1.00 1.00 - - - - mul rdx
|
|
72
|
+
- - - - - 1.00 - - jo .LBB5_5
|
|
73
|
+
- - 0.82 0.18 - - - - cmp rax, -10
|
|
74
|
+
- - - - - 1.00 - - ja .LBB5_5
|
|
75
|
+
- - 0.02 0.98 - - - - mov edx, eax
|
|
76
|
+
- - 0.82 0.02 - 0.16 - - not edx
|
|
77
|
+
- - 0.82 0.17 - 0.01 - - and edx, 3
|
|
78
|
+
- - 0.99 - - 0.01 - - add rdx, rax
|
|
79
|
+
- - 0.98 0.01 - 0.01 - - add rdx, 9
|
|
80
|
+
- - 1.00 - - - - - cmp rsi, rdx
|
|
81
|
+
- - - - - 1.00 - - jne .LBB5_5
|
|
82
|
+
- - 0.16 0.83 - 0.01 - - mov r8d, edi
|
|
83
|
+
- - 0.17 0.17 - 0.66 - - and r8d, 3
|
|
84
|
+
- - - - - 1.00 - - jne .LBB5_5
|
|
85
|
+
- - 0.02 0.98 - - - - add rax, 9
|
|
86
|
+
- - - 0.17 - 0.83 - - cmp rdx, rax
|
|
87
|
+
- - - - - 1.00 - - jb .LBB5_5
|
|
88
|
+
- - 0.01 0.67 - 0.32 - - mov rax, rdi
|
|
89
|
+
- - 0.02 0.98 - - - - mov rdx, rcx
|
|
90
|
+
- - - - - 1.00 - - ret
|
|
91
|
+
- - - - - - - - xor edi, edi
|
|
92
|
+
- - 0.34 0.66 - - - - mov rcx, rsi
|
|
93
|
+
- - 0.34 0.50 - 0.16 - - mov rax, rdi
|
|
94
|
+
- - 0.50 0.50 - - - - mov rdx, rcx
|
|
95
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,10 @@
|
|
|
1
|
+
#[path = "formats/coco_dynamic_size.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_ref_from_bytes_with_elems_dynamic_size(
|
|
6
|
+
source: &[u8],
|
|
7
|
+
count: usize,
|
|
8
|
+
) -> Option<&format::LocoPacket> {
|
|
9
|
+
zerocopy::FromBytes::ref_from_bytes_with_elems(source, count).ok()
|
|
10
|
+
}
|
|
@@ -0,0 +1,16 @@
|
|
|
1
|
+
bench_ref_from_bytes_with_elems_dynamic_size:
|
|
2
|
+
movabs rax, 9223372036854775805
|
|
3
|
+
cmp rdx, rax
|
|
4
|
+
seta cl
|
|
5
|
+
mov rax, rdi
|
|
6
|
+
or dil, cl
|
|
7
|
+
test dil, 1
|
|
8
|
+
jne .LBB5_2
|
|
9
|
+
lea rcx, [2*rdx + 4]
|
|
10
|
+
cmp rsi, rcx
|
|
11
|
+
je .LBB5_3
|
|
12
|
+
.LBB5_2:
|
|
13
|
+
xor eax, eax
|
|
14
|
+
mov rdx, rsi
|
|
15
|
+
.LBB5_3:
|
|
16
|
+
ret
|
|
@@ -0,0 +1,65 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 1300
|
|
3
|
+
Total Cycles: 439
|
|
4
|
+
Total uOps: 1400
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.19
|
|
8
|
+
IPC: 2.96
|
|
9
|
+
Block RThroughput: 3.5
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 movabs rax, 9223372036854775805
|
|
22
|
+
1 1 0.33 cmp rdx, rax
|
|
23
|
+
2 2 1.00 seta cl
|
|
24
|
+
1 1 0.33 mov rax, rdi
|
|
25
|
+
1 1 0.33 or dil, cl
|
|
26
|
+
1 1 0.33 test dil, 1
|
|
27
|
+
1 1 1.00 jne .LBB5_2
|
|
28
|
+
1 1 0.50 lea rcx, [2*rdx + 4]
|
|
29
|
+
1 1 0.33 cmp rsi, rcx
|
|
30
|
+
1 1 1.00 je .LBB5_3
|
|
31
|
+
1 0 0.25 xor eax, eax
|
|
32
|
+
1 1 0.33 mov rdx, rsi
|
|
33
|
+
1 1 1.00 U ret
|
|
34
|
+
|
|
35
|
+
|
|
36
|
+
Resources:
|
|
37
|
+
[0] - SBDivider
|
|
38
|
+
[1] - SBFPDivider
|
|
39
|
+
[2] - SBPort0
|
|
40
|
+
[3] - SBPort1
|
|
41
|
+
[4] - SBPort4
|
|
42
|
+
[5] - SBPort5
|
|
43
|
+
[6.0] - SBPort23
|
|
44
|
+
[6.1] - SBPort23
|
|
45
|
+
|
|
46
|
+
|
|
47
|
+
Resource pressure per iteration:
|
|
48
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
49
|
+
- - 4.32 4.33 - 4.35 - -
|
|
50
|
+
|
|
51
|
+
Resource pressure by instruction:
|
|
52
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
53
|
+
- - - 0.99 - 0.01 - - movabs rax, 9223372036854775805
|
|
54
|
+
- - 0.33 0.67 - - - - cmp rdx, rax
|
|
55
|
+
- - 1.98 - - 0.02 - - seta cl
|
|
56
|
+
- - 0.01 0.99 - - - - mov rax, rdi
|
|
57
|
+
- - 1.00 - - - - - or dil, cl
|
|
58
|
+
- - 0.99 0.01 - - - - test dil, 1
|
|
59
|
+
- - - - - 1.00 - - jne .LBB5_2
|
|
60
|
+
- - - 1.00 - - - - lea rcx, [2*rdx + 4]
|
|
61
|
+
- - 0.01 - - 0.99 - - cmp rsi, rcx
|
|
62
|
+
- - - - - 1.00 - - je .LBB5_3
|
|
63
|
+
- - - - - - - - xor eax, eax
|
|
64
|
+
- - - 0.67 - 0.33 - - mov rdx, rsi
|
|
65
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,10 @@
|
|
|
1
|
+
#[path = "formats/coco_dynamic_padding.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_ref_from_prefix_dynamic_padding(source: &[u8]) -> Option<&format::LocoPacket> {
|
|
6
|
+
match zerocopy::FromBytes::ref_from_prefix(source) {
|
|
7
|
+
Ok((packet, _rest)) => Some(packet),
|
|
8
|
+
_ => None,
|
|
9
|
+
}
|
|
10
|
+
}
|
|
@@ -0,0 +1,22 @@
|
|
|
1
|
+
bench_ref_from_prefix_dynamic_padding:
|
|
2
|
+
xor edx, edx
|
|
3
|
+
mov eax, 0
|
|
4
|
+
test dil, 3
|
|
5
|
+
je .LBB5_1
|
|
6
|
+
ret
|
|
7
|
+
.LBB5_1:
|
|
8
|
+
movabs rax, 9223372036854775804
|
|
9
|
+
and rsi, rax
|
|
10
|
+
cmp rsi, 9
|
|
11
|
+
jae .LBB5_3
|
|
12
|
+
mov edx, 1
|
|
13
|
+
xor eax, eax
|
|
14
|
+
ret
|
|
15
|
+
.LBB5_3:
|
|
16
|
+
add rsi, -9
|
|
17
|
+
movabs rcx, -6148914691236517205
|
|
18
|
+
mov rax, rsi
|
|
19
|
+
mul rcx
|
|
20
|
+
shr rdx
|
|
21
|
+
mov rax, rdi
|
|
22
|
+
ret
|