html-to-markdown 2.28.0 → 2.28.2

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (196) hide show
  1. checksums.yaml +4 -4
  2. data/Gemfile.lock +6 -6
  3. data/README.md +5 -1
  4. data/ext/html-to-markdown-rb/native/Cargo.lock +1694 -0
  5. data/ext/html-to-markdown-rb/native/Cargo.toml +1 -1
  6. data/lib/html_to_markdown/version.rb +1 -1
  7. data/rust-vendor/html-to-markdown-rs/Cargo.toml +1 -1
  8. data/rust-vendor/html-to-markdown-rs/src/converter/text_node.rs +1 -0
  9. data/rust-vendor/html-to-markdown-rs/src/converter/utility/content.rs +17 -0
  10. data/rust-vendor/html-to-markdown-rs/src/converter/visitor_hooks.rs +8 -5
  11. data/rust-vendor/html-to-markdown-rs/tests/test_issue_218.rs +56 -0
  12. data/rust-vendor/libc/.cargo-checksum.json +1 -1
  13. data/rust-vendor/libc/.cargo_vcs_info.json +1 -1
  14. data/rust-vendor/libc/CHANGELOG.md +19 -0
  15. data/rust-vendor/libc/Cargo.lock +1 -1
  16. data/rust-vendor/libc/Cargo.toml +1 -1
  17. data/rust-vendor/libc/Cargo.toml.orig +1 -1
  18. data/rust-vendor/libc/build.rs +3 -3
  19. data/rust-vendor/libc/src/fuchsia/mod.rs +2 -0
  20. data/rust-vendor/libc/src/hermit.rs +1 -0
  21. data/rust-vendor/libc/src/lib.rs +1 -0
  22. data/rust-vendor/libc/src/new/linux_uapi/linux/mod.rs +1 -0
  23. data/rust-vendor/libc/src/new/linux_uapi/linux/pidfd.rs +59 -0
  24. data/rust-vendor/libc/src/new/mod.rs +3 -0
  25. data/rust-vendor/libc/src/new/netbsd/sys/file.rs +16 -0
  26. data/rust-vendor/libc/src/new/netbsd/sys/mod.rs +2 -0
  27. data/rust-vendor/libc/src/new/netbsd/sys/socket.rs +44 -0
  28. data/rust-vendor/libc/src/new/qurt/mod.rs +2 -0
  29. data/rust-vendor/libc/src/solid/mod.rs +1 -0
  30. data/rust-vendor/libc/src/switch.rs +1 -0
  31. data/rust-vendor/libc/src/teeos/mod.rs +2 -0
  32. data/rust-vendor/libc/src/trusty.rs +1 -0
  33. data/rust-vendor/libc/src/unix/bsd/apple/b64/mod.rs +1 -0
  34. data/rust-vendor/libc/src/unix/bsd/netbsdlike/netbsd/mod.rs +31 -0
  35. data/rust-vendor/libc/src/unix/bsd/netbsdlike/openbsd/mod.rs +92 -0
  36. data/rust-vendor/libc/src/unix/hurd/mod.rs +1 -0
  37. data/rust-vendor/libc/src/unix/linux_like/linux/gnu/mod.rs +1 -0
  38. data/rust-vendor/libc/src/unix/linux_like/linux/mod.rs +22 -46
  39. data/rust-vendor/libc/src/unix/mod.rs +2 -0
  40. data/rust-vendor/libc/src/unix/newlib/espidf/mod.rs +2 -0
  41. data/rust-vendor/libc/src/unix/redox/mod.rs +2 -2
  42. data/rust-vendor/libc/src/vxworks/mod.rs +46 -0
  43. data/rust-vendor/libc/src/wasi/mod.rs +2 -0
  44. data/rust-vendor/libc/src/windows/mod.rs +2 -0
  45. data/rust-vendor/uuid/.cargo-checksum.json +1 -1
  46. data/rust-vendor/uuid/.cargo_vcs_info.json +1 -1
  47. data/rust-vendor/uuid/Cargo.lock +71 -137
  48. data/rust-vendor/uuid/Cargo.toml +4 -4
  49. data/rust-vendor/uuid/Cargo.toml.orig +4 -4
  50. data/rust-vendor/uuid/README.md +3 -3
  51. data/rust-vendor/uuid/src/lib.rs +4 -4
  52. data/rust-vendor/zerocopy/.cargo-checksum.json +1 -1
  53. data/rust-vendor/zerocopy/.cargo_vcs_info.json +1 -1
  54. data/rust-vendor/zerocopy/Cargo.lock +3 -3
  55. data/rust-vendor/zerocopy/Cargo.toml +178 -4
  56. data/rust-vendor/zerocopy/Cargo.toml.orig +5 -5
  57. data/rust-vendor/zerocopy/benches/formats/coco_dynamic_padding.rs +24 -0
  58. data/rust-vendor/zerocopy/benches/formats/coco_dynamic_size.rs +23 -0
  59. data/rust-vendor/zerocopy/benches/formats/coco_static_size.rs +23 -0
  60. data/rust-vendor/zerocopy/benches/read_from_bytes.rs +7 -0
  61. data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64 +15 -0
  62. data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64.mca +65 -0
  63. data/rust-vendor/zerocopy/benches/read_from_prefix.rs +10 -0
  64. data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64 +14 -0
  65. data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64.mca +63 -0
  66. data/rust-vendor/zerocopy/benches/read_from_suffix.rs +10 -0
  67. data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64 +15 -0
  68. data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64.mca +65 -0
  69. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.rs +7 -0
  70. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64 +22 -0
  71. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64.mca +77 -0
  72. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.rs +7 -0
  73. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64 +20 -0
  74. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64.mca +75 -0
  75. data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.rs +7 -0
  76. data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64 +8 -0
  77. data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64.mca +53 -0
  78. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
  79. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64 +30 -0
  80. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +95 -0
  81. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.rs +10 -0
  82. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64 +16 -0
  83. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64.mca +65 -0
  84. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.rs +10 -0
  85. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64 +22 -0
  86. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64.mca +77 -0
  87. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.rs +10 -0
  88. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64 +17 -0
  89. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64.mca +67 -0
  90. data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.rs +10 -0
  91. data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64 +8 -0
  92. data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64.mca +53 -0
  93. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
  94. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
  95. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
  96. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.rs +13 -0
  97. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64 +22 -0
  98. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64.mca +77 -0
  99. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.rs +10 -0
  100. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64 +23 -0
  101. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64.mca +79 -0
  102. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.rs +10 -0
  103. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64 +13 -0
  104. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64.mca +63 -0
  105. data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.rs +10 -0
  106. data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64 +13 -0
  107. data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64.mca +61 -0
  108. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
  109. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64 +34 -0
  110. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +99 -0
  111. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.rs +13 -0
  112. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64 +23 -0
  113. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64.mca +77 -0
  114. data/rust-vendor/zerocopy/benches/transmute.rs +16 -0
  115. data/rust-vendor/zerocopy/benches/transmute.x86-64 +3 -0
  116. data/rust-vendor/zerocopy/benches/transmute.x86-64.mca +43 -0
  117. data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.rs +16 -0
  118. data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64 +4 -0
  119. data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64.mca +45 -0
  120. data/rust-vendor/zerocopy/benches/transmute_ref_static_size.rs +15 -0
  121. data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64 +3 -0
  122. data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64.mca +43 -0
  123. data/rust-vendor/zerocopy/benches/try_read_from_bytes.rs +7 -0
  124. data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64 +23 -0
  125. data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64.mca +79 -0
  126. data/rust-vendor/zerocopy/benches/try_read_from_prefix.rs +10 -0
  127. data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64 +16 -0
  128. data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64.mca +67 -0
  129. data/rust-vendor/zerocopy/benches/try_read_from_suffix.rs +10 -0
  130. data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64 +18 -0
  131. data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64.mca +71 -0
  132. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.rs +7 -0
  133. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64 +24 -0
  134. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64.mca +81 -0
  135. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.rs +7 -0
  136. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64 +22 -0
  137. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64.mca +79 -0
  138. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.rs +7 -0
  139. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64 +13 -0
  140. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64.mca +59 -0
  141. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
  142. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64 +36 -0
  143. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +105 -0
  144. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.rs +10 -0
  145. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64 +18 -0
  146. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64.mca +69 -0
  147. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.rs +10 -0
  148. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64 +29 -0
  149. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64.mca +91 -0
  150. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.rs +10 -0
  151. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64 +22 -0
  152. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64.mca +77 -0
  153. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.rs +10 -0
  154. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64 +15 -0
  155. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64.mca +63 -0
  156. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
  157. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
  158. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
  159. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.rs +13 -0
  160. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64 +26 -0
  161. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64.mca +83 -0
  162. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.rs +10 -0
  163. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64 +26 -0
  164. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64.mca +85 -0
  165. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.rs +10 -0
  166. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64 +18 -0
  167. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64.mca +71 -0
  168. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.rs +10 -0
  169. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64 +16 -0
  170. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64.mca +67 -0
  171. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
  172. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64 +39 -0
  173. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +109 -0
  174. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.rs +13 -0
  175. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64 +28 -0
  176. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64.mca +87 -0
  177. data/rust-vendor/zerocopy/benches/try_transmute.rs +16 -0
  178. data/rust-vendor/zerocopy/benches/try_transmute.x86-64 +9 -0
  179. data/rust-vendor/zerocopy/benches/try_transmute.x86-64.mca +55 -0
  180. data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.rs +18 -0
  181. data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64 +6 -0
  182. data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64.mca +49 -0
  183. data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.rs +17 -0
  184. data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64 +5 -0
  185. data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64.mca +47 -0
  186. data/rust-vendor/zerocopy/rustdoc/style.css +55 -0
  187. data/rust-vendor/zerocopy/src/lib.rs +331 -0
  188. data/rust-vendor/zerocopy/src/macros.rs +48 -1
  189. data/rust-vendor/zerocopy/src/util/macros.rs +199 -0
  190. data/rust-vendor/zerocopy/tests/codegen.rs +111 -0
  191. data/rust-vendor/zerocopy-derive/.cargo-checksum.json +1 -1
  192. data/rust-vendor/zerocopy-derive/.cargo_vcs_info.json +1 -1
  193. data/rust-vendor/zerocopy-derive/Cargo.lock +1 -1
  194. data/rust-vendor/zerocopy-derive/Cargo.toml +1 -1
  195. data/rust-vendor/zerocopy-derive/Cargo.toml.orig +1 -1
  196. metadata +138 -2
@@ -0,0 +1,101 @@
1
+ Iterations: 100
2
+ Instructions: 3100
3
+ Total Cycles: 1008
4
+ Total uOps: 3400
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.37
8
+ IPC: 3.08
9
+ Block RThroughput: 8.5
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.33 mov rcx, rdx
22
+ 1 1 0.33 mov edx, 3
23
+ 1 1 0.33 mov rax, rcx
24
+ 2 4 1.00 mul rdx
25
+ 1 1 1.00 jo .LBB5_1
26
+ 1 1 0.33 cmp rax, -10
27
+ 1 1 1.00 ja .LBB5_1
28
+ 1 1 0.50 lea rdx, [rax + 9]
29
+ 1 1 0.33 not eax
30
+ 1 1 0.33 and eax, 3
31
+ 1 1 0.33 add rax, rdx
32
+ 1 1 1.00 jae .LBB5_4
33
+ 1 0 0.25 xor eax, eax
34
+ 1 1 0.33 mov edx, 1
35
+ 1 1 1.00 U ret
36
+ 1 1 0.33 mov r8, rax
37
+ 1 0 0.25 xor edx, edx
38
+ 1 1 0.33 mov eax, 0
39
+ 1 1 0.33 test dil, 3
40
+ 1 1 1.00 je .LBB5_5
41
+ 1 1 1.00 U ret
42
+ 1 1 0.33 cmp r8, rsi
43
+ 1 1 1.00 ja .LBB5_1
44
+ 1 5 0.50 * movzx esi, word ptr [rdi]
45
+ 1 1 0.33 cmp si, -16192
46
+ 1 1 0.33 mov edx, 2
47
+ 2 2 0.67 cmove rdx, rcx
48
+ 1 0 0.25 xor eax, eax
49
+ 1 1 0.33 cmp esi, 49344
50
+ 2 2 0.67 cmove rax, rdi
51
+ 1 1 1.00 U ret
52
+
53
+
54
+ Resources:
55
+ [0] - SBDivider
56
+ [1] - SBFPDivider
57
+ [2] - SBPort0
58
+ [3] - SBPort1
59
+ [4] - SBPort4
60
+ [5] - SBPort5
61
+ [6.0] - SBPort23
62
+ [6.1] - SBPort23
63
+
64
+
65
+ Resource pressure per iteration:
66
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
67
+ - - 9.98 9.99 - 10.03 0.50 0.50
68
+
69
+ Resource pressure by instruction:
70
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
71
+ - - 0.49 0.50 - 0.01 - - mov rcx, rdx
72
+ - - 0.01 0.99 - - - - mov edx, 3
73
+ - - 0.99 0.01 - - - - mov rax, rcx
74
+ - - 1.00 1.00 - - - - mul rdx
75
+ - - - - - 1.00 - - jo .LBB5_1
76
+ - - 1.00 - - - - - cmp rax, -10
77
+ - - - - - 1.00 - - ja .LBB5_1
78
+ - - - 1.00 - - - - lea rdx, [rax + 9]
79
+ - - 1.00 - - - - - not eax
80
+ - - 0.99 0.01 - - - - and eax, 3
81
+ - - 0.99 0.01 - - - - add rax, rdx
82
+ - - - - - 1.00 - - jae .LBB5_4
83
+ - - - - - - - - xor eax, eax
84
+ - - - 0.98 - 0.02 - - mov edx, 1
85
+ - - - - - 1.00 - - ret
86
+ - - 0.50 0.50 - - - - mov r8, rax
87
+ - - - - - - - - xor edx, edx
88
+ - - 0.02 0.49 - 0.49 - - mov eax, 0
89
+ - - - 0.49 - 0.51 - - test dil, 3
90
+ - - - - - 1.00 - - je .LBB5_5
91
+ - - - - - 1.00 - - ret
92
+ - - 0.98 0.02 - - - - cmp r8, rsi
93
+ - - - - - 1.00 - - ja .LBB5_1
94
+ - - - - - - 0.50 0.50 movzx esi, word ptr [rdi]
95
+ - - 0.02 0.98 - - - - cmp si, -16192
96
+ - - 0.98 0.02 - - - - mov edx, 2
97
+ - - 0.50 1.00 - 0.50 - - cmove rdx, rcx
98
+ - - - - - - - - xor eax, eax
99
+ - - 0.01 0.99 - - - - cmp esi, 49344
100
+ - - 0.50 1.00 - 0.50 - - cmove rax, rdi
101
+ - - - - - 1.00 - - ret
@@ -0,0 +1,13 @@
1
+ #[path = "formats/coco_dynamic_size.rs"]
2
+ mod format;
3
+
4
+ #[unsafe(no_mangle)]
5
+ fn bench_try_ref_from_prefix_with_elems_dynamic_size(
6
+ source: &[u8],
7
+ count: usize,
8
+ ) -> Option<&format::CocoPacket> {
9
+ match zerocopy::TryFromBytes::try_ref_from_prefix_with_elems(source, count) {
10
+ Ok((packet, _rest)) => Some(packet),
11
+ _ => None,
12
+ }
13
+ }
@@ -0,0 +1,26 @@
1
+ bench_try_ref_from_prefix_with_elems_dynamic_size:
2
+ movabs rax, 9223372036854775805
3
+ cmp rdx, rax
4
+ ja .LBB5_1
5
+ mov rcx, rdx
6
+ xor edx, edx
7
+ mov eax, 0
8
+ test dil, 1
9
+ jne .LBB5_5
10
+ lea rax, [2*rcx + 4]
11
+ cmp rax, rsi
12
+ jbe .LBB5_4
13
+ .LBB5_1:
14
+ xor eax, eax
15
+ mov edx, 1
16
+ ret
17
+ .LBB5_4:
18
+ movzx esi, word ptr [rdi]
19
+ cmp si, -16192
20
+ mov edx, 2
21
+ cmove rdx, rcx
22
+ xor eax, eax
23
+ cmp esi, 49344
24
+ cmove rax, rdi
25
+ .LBB5_5:
26
+ ret
@@ -0,0 +1,83 @@
1
+ Iterations: 100
2
+ Instructions: 2200
3
+ Total Cycles: 674
4
+ Total uOps: 2400
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.56
8
+ IPC: 3.26
9
+ Block RThroughput: 6.0
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.33 movabs rax, 9223372036854775805
22
+ 1 1 0.33 cmp rdx, rax
23
+ 1 1 1.00 ja .LBB5_1
24
+ 1 1 0.33 mov rcx, rdx
25
+ 1 0 0.25 xor edx, edx
26
+ 1 1 0.33 mov eax, 0
27
+ 1 1 0.33 test dil, 1
28
+ 1 1 1.00 jne .LBB5_5
29
+ 1 1 0.50 lea rax, [2*rcx + 4]
30
+ 1 1 0.33 cmp rax, rsi
31
+ 1 1 1.00 jbe .LBB5_4
32
+ 1 0 0.25 xor eax, eax
33
+ 1 1 0.33 mov edx, 1
34
+ 1 1 1.00 U ret
35
+ 1 5 0.50 * movzx esi, word ptr [rdi]
36
+ 1 1 0.33 cmp si, -16192
37
+ 1 1 0.33 mov edx, 2
38
+ 2 2 0.67 cmove rdx, rcx
39
+ 1 0 0.25 xor eax, eax
40
+ 1 1 0.33 cmp esi, 49344
41
+ 2 2 0.67 cmove rax, rdi
42
+ 1 1 1.00 U ret
43
+
44
+
45
+ Resources:
46
+ [0] - SBDivider
47
+ [1] - SBFPDivider
48
+ [2] - SBPort0
49
+ [3] - SBPort1
50
+ [4] - SBPort4
51
+ [5] - SBPort5
52
+ [6.0] - SBPort23
53
+ [6.1] - SBPort23
54
+
55
+
56
+ Resource pressure per iteration:
57
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
58
+ - - 6.65 6.66 - 6.69 0.50 0.50
59
+
60
+ Resource pressure by instruction:
61
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
62
+ - - 0.66 0.33 - 0.01 - - movabs rax, 9223372036854775805
63
+ - - 0.02 0.66 - 0.32 - - cmp rdx, rax
64
+ - - - - - 1.00 - - ja .LBB5_1
65
+ - - 0.66 0.33 - 0.01 - - mov rcx, rdx
66
+ - - - - - - - - xor edx, edx
67
+ - - 0.33 0.01 - 0.66 - - mov eax, 0
68
+ - - 0.34 0.65 - 0.01 - - test dil, 1
69
+ - - - - - 1.00 - - jne .LBB5_5
70
+ - - 0.65 0.35 - - - - lea rax, [2*rcx + 4]
71
+ - - - 1.00 - - - - cmp rax, rsi
72
+ - - - - - 1.00 - - jbe .LBB5_4
73
+ - - - - - - - - xor eax, eax
74
+ - - 0.34 0.01 - 0.65 - - mov edx, 1
75
+ - - - - - 1.00 - - ret
76
+ - - - - - - 0.50 0.50 movzx esi, word ptr [rdi]
77
+ - - 0.65 0.34 - 0.01 - - cmp si, -16192
78
+ - - 0.66 0.34 - - - - mov edx, 2
79
+ - - 1.00 0.99 - 0.01 - - cmove rdx, rcx
80
+ - - - - - - - - xor eax, eax
81
+ - - 0.34 0.66 - - - - cmp esi, 49344
82
+ - - 1.00 0.99 - 0.01 - - cmove rax, rdi
83
+ - - - - - 1.00 - - ret
@@ -0,0 +1,10 @@
1
+ #[path = "formats/coco_dynamic_padding.rs"]
2
+ mod format;
3
+
4
+ #[unsafe(no_mangle)]
5
+ fn bench_try_ref_from_suffix_dynamic_padding(source: &[u8]) -> Option<&format::CocoPacket> {
6
+ match zerocopy::TryFromBytes::try_ref_from_suffix(source) {
7
+ Ok((_rest, packet)) => Some(packet),
8
+ _ => None,
9
+ }
10
+ }
@@ -0,0 +1,26 @@
1
+ bench_try_ref_from_suffix_dynamic_padding:
2
+ lea eax, [rsi + rdi]
3
+ test al, 3
4
+ jne .LBB5_1
5
+ movabs rax, 9223372036854775804
6
+ and rax, rsi
7
+ cmp rax, 9
8
+ jae .LBB5_3
9
+ .LBB5_1:
10
+ xor eax, eax
11
+ ret
12
+ .LBB5_3:
13
+ add rax, -9
14
+ movabs rcx, -6148914691236517205
15
+ mul rcx
16
+ shr rdx
17
+ lea rcx, [rdx + 2*rdx]
18
+ sub rsi, rcx
19
+ or rcx, -4
20
+ add rsi, rdi
21
+ lea rdi, [rcx + rsi]
22
+ add rdi, -8
23
+ xor eax, eax
24
+ cmp word ptr [rcx + rsi - 8], -16192
25
+ cmove rax, rdi
26
+ ret
@@ -0,0 +1,85 @@
1
+ Iterations: 100
2
+ Instructions: 2300
3
+ Total Cycles: 791
4
+ Total uOps: 2600
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.29
8
+ IPC: 2.91
9
+ Block RThroughput: 6.5
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.50 lea eax, [rsi + rdi]
22
+ 1 1 0.33 test al, 3
23
+ 1 1 1.00 jne .LBB5_1
24
+ 1 1 0.33 movabs rax, 9223372036854775804
25
+ 1 1 0.33 and rax, rsi
26
+ 1 1 0.33 cmp rax, 9
27
+ 1 1 1.00 jae .LBB5_3
28
+ 1 0 0.25 xor eax, eax
29
+ 1 1 1.00 U ret
30
+ 1 1 0.33 add rax, -9
31
+ 1 1 0.33 movabs rcx, -6148914691236517205
32
+ 2 4 1.00 mul rcx
33
+ 1 1 0.50 shr rdx
34
+ 1 1 0.50 lea rcx, [rdx + 2*rdx]
35
+ 1 1 0.33 sub rsi, rcx
36
+ 1 1 0.33 or rcx, -4
37
+ 1 1 0.33 add rsi, rdi
38
+ 1 1 0.50 lea rdi, [rcx + rsi]
39
+ 1 1 0.33 add rdi, -8
40
+ 1 0 0.25 xor eax, eax
41
+ 2 6 0.50 * cmp word ptr [rcx + rsi - 8], -16192
42
+ 2 2 0.67 cmove rax, rdi
43
+ 1 1 1.00 U ret
44
+
45
+
46
+ Resources:
47
+ [0] - SBDivider
48
+ [1] - SBFPDivider
49
+ [2] - SBPort0
50
+ [3] - SBPort1
51
+ [4] - SBPort4
52
+ [5] - SBPort5
53
+ [6.0] - SBPort23
54
+ [6.1] - SBPort23
55
+
56
+
57
+ Resource pressure per iteration:
58
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
59
+ - - 7.70 7.58 - 7.72 0.50 0.50
60
+
61
+ Resource pressure by instruction:
62
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
63
+ - - 0.26 0.74 - - - - lea eax, [rsi + rdi]
64
+ - - 0.19 0.28 - 0.53 - - test al, 3
65
+ - - - - - 1.00 - - jne .LBB5_1
66
+ - - 0.93 0.06 - 0.01 - - movabs rax, 9223372036854775804
67
+ - - 0.81 0.14 - 0.05 - - and rax, rsi
68
+ - - 0.55 0.43 - 0.02 - - cmp rax, 9
69
+ - - - - - 1.00 - - jae .LBB5_3
70
+ - - - - - - - - xor eax, eax
71
+ - - - - - 1.00 - - ret
72
+ - - 0.42 0.56 - 0.02 - - add rax, -9
73
+ - - 0.67 0.30 - 0.03 - - movabs rcx, -6148914691236517205
74
+ - - 1.00 1.00 - - - - mul rcx
75
+ - - 0.71 - - 0.29 - - shr rdx
76
+ - - 0.32 0.68 - - - - lea rcx, [rdx + 2*rdx]
77
+ - - 0.57 0.04 - 0.39 - - sub rsi, rcx
78
+ - - 0.28 0.67 - 0.05 - - or rcx, -4
79
+ - - 0.29 0.29 - 0.42 - - add rsi, rdi
80
+ - - 0.02 0.98 - - - - lea rdi, [rcx + rsi]
81
+ - - 0.02 0.41 - 0.57 - - add rdi, -8
82
+ - - - - - - - - xor eax, eax
83
+ - - 0.57 0.01 - 0.42 0.50 0.50 cmp word ptr [rcx + rsi - 8], -16192
84
+ - - 0.09 0.99 - 0.92 - - cmove rax, rdi
85
+ - - - - - 1.00 - - ret
@@ -0,0 +1,10 @@
1
+ #[path = "formats/coco_dynamic_size.rs"]
2
+ mod format;
3
+
4
+ #[unsafe(no_mangle)]
5
+ fn bench_try_ref_from_suffix_dynamic_size(source: &[u8]) -> Option<&format::CocoPacket> {
6
+ match zerocopy::TryFromBytes::try_ref_from_suffix(source) {
7
+ Ok((_rest, packet)) => Some(packet),
8
+ _ => None,
9
+ }
10
+ }
@@ -0,0 +1,18 @@
1
+ bench_try_ref_from_suffix_dynamic_size:
2
+ lea eax, [rsi + rdi]
3
+ cmp rsi, 4
4
+ setb cl
5
+ or cl, al
6
+ test cl, 1
7
+ je .LBB5_2
8
+ xor eax, eax
9
+ ret
10
+ .LBB5_2:
11
+ lea rdx, [rsi - 4]
12
+ shr rdx
13
+ and esi, 1
14
+ lea rcx, [rdi + rsi]
15
+ xor eax, eax
16
+ cmp word ptr [rdi + rsi], -16192
17
+ cmove rax, rcx
18
+ ret
@@ -0,0 +1,71 @@
1
+ Iterations: 100
2
+ Instructions: 1600
3
+ Total Cycles: 510
4
+ Total uOps: 1800
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.53
8
+ IPC: 3.14
9
+ Block RThroughput: 4.5
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.50 lea eax, [rsi + rdi]
22
+ 1 1 0.33 cmp rsi, 4
23
+ 1 1 0.50 setb cl
24
+ 1 1 0.33 or cl, al
25
+ 1 1 0.33 test cl, 1
26
+ 1 1 1.00 je .LBB5_2
27
+ 1 0 0.25 xor eax, eax
28
+ 1 1 1.00 U ret
29
+ 1 1 0.50 lea rdx, [rsi - 4]
30
+ 1 1 0.50 shr rdx
31
+ 1 1 0.33 and esi, 1
32
+ 1 1 0.50 lea rcx, [rdi + rsi]
33
+ 1 0 0.25 xor eax, eax
34
+ 2 6 0.50 * cmp word ptr [rdi + rsi], -16192
35
+ 2 2 0.67 cmove rax, rcx
36
+ 1 1 1.00 U ret
37
+
38
+
39
+ Resources:
40
+ [0] - SBDivider
41
+ [1] - SBFPDivider
42
+ [2] - SBPort0
43
+ [3] - SBPort1
44
+ [4] - SBPort4
45
+ [5] - SBPort5
46
+ [6.0] - SBPort23
47
+ [6.1] - SBPort23
48
+
49
+
50
+ Resource pressure per iteration:
51
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
52
+ - - 4.99 5.00 - 5.01 0.50 0.50
53
+
54
+ Resource pressure by instruction:
55
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
56
+ - - 0.98 0.02 - - - - lea eax, [rsi + rdi]
57
+ - - - 0.98 - 0.02 - - cmp rsi, 4
58
+ - - 1.00 - - - - - setb cl
59
+ - - 0.01 0.99 - - - - or cl, al
60
+ - - 0.01 0.07 - 0.92 - - test cl, 1
61
+ - - - - - 1.00 - - je .LBB5_2
62
+ - - - - - - - - xor eax, eax
63
+ - - - - - 1.00 - - ret
64
+ - - 0.93 0.07 - - - - lea rdx, [rsi - 4]
65
+ - - 0.93 - - 0.07 - - shr rdx
66
+ - - 0.06 0.93 - 0.01 - - and esi, 1
67
+ - - 0.07 0.93 - - - - lea rcx, [rdi + rsi]
68
+ - - - - - - - - xor eax, eax
69
+ - - - 0.01 - 0.99 0.50 0.50 cmp word ptr [rdi + rsi], -16192
70
+ - - 1.00 1.00 - - - - cmove rax, rcx
71
+ - - - - - 1.00 - - ret
@@ -0,0 +1,10 @@
1
+ #[path = "formats/coco_static_size.rs"]
2
+ mod format;
3
+
4
+ #[unsafe(no_mangle)]
5
+ fn bench_try_ref_from_suffix_static_size(source: &[u8]) -> Option<&format::CocoPacket> {
6
+ match zerocopy::TryFromBytes::try_ref_from_suffix(source) {
7
+ Ok((_rest, packet)) => Some(packet),
8
+ _ => None,
9
+ }
10
+ }
@@ -0,0 +1,16 @@
1
+ bench_try_ref_from_suffix_static_size:
2
+ lea eax, [rsi + rdi]
3
+ cmp rsi, 6
4
+ setb cl
5
+ or cl, al
6
+ test cl, 1
7
+ je .LBB5_2
8
+ xor eax, eax
9
+ ret
10
+ .LBB5_2:
11
+ lea rcx, [rdi + rsi]
12
+ add rcx, -6
13
+ xor eax, eax
14
+ cmp word ptr [rdi + rsi - 6], -16192
15
+ cmove rax, rcx
16
+ ret
@@ -0,0 +1,67 @@
1
+ Iterations: 100
2
+ Instructions: 1400
3
+ Total Cycles: 443
4
+ Total uOps: 1600
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.61
8
+ IPC: 3.16
9
+ Block RThroughput: 4.0
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.50 lea eax, [rsi + rdi]
22
+ 1 1 0.33 cmp rsi, 6
23
+ 1 1 0.50 setb cl
24
+ 1 1 0.33 or cl, al
25
+ 1 1 0.33 test cl, 1
26
+ 1 1 1.00 je .LBB5_2
27
+ 1 0 0.25 xor eax, eax
28
+ 1 1 1.00 U ret
29
+ 1 1 0.50 lea rcx, [rdi + rsi]
30
+ 1 1 0.33 add rcx, -6
31
+ 1 0 0.25 xor eax, eax
32
+ 2 6 0.50 * cmp word ptr [rdi + rsi - 6], -16192
33
+ 2 2 0.67 cmove rax, rcx
34
+ 1 1 1.00 U ret
35
+
36
+
37
+ Resources:
38
+ [0] - SBDivider
39
+ [1] - SBFPDivider
40
+ [2] - SBPort0
41
+ [3] - SBPort1
42
+ [4] - SBPort4
43
+ [5] - SBPort5
44
+ [6.0] - SBPort23
45
+ [6.1] - SBPort23
46
+
47
+
48
+ Resource pressure per iteration:
49
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
50
+ - - 4.33 4.33 - 4.34 0.50 0.50
51
+
52
+ Resource pressure by instruction:
53
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
54
+ - - 0.32 0.68 - - - - lea eax, [rsi + rdi]
55
+ - - 0.05 0.94 - 0.01 - - cmp rsi, 6
56
+ - - 1.00 - - - - - setb cl
57
+ - - 0.95 0.05 - - - - or cl, al
58
+ - - 0.95 0.02 - 0.03 - - test cl, 1
59
+ - - - - - 1.00 - - je .LBB5_2
60
+ - - - - - - - - xor eax, eax
61
+ - - - - - 1.00 - - ret
62
+ - - 0.04 0.96 - - - - lea rcx, [rdi + rsi]
63
+ - - 0.02 0.97 - 0.01 - - add rcx, -6
64
+ - - - - - - - - xor eax, eax
65
+ - - 0.03 0.66 - 0.31 0.50 0.50 cmp word ptr [rdi + rsi - 6], -16192
66
+ - - 0.97 0.05 - 0.98 - - cmove rax, rcx
67
+ - - - - - 1.00 - - ret
@@ -0,0 +1,13 @@
1
+ #[path = "formats/coco_dynamic_padding.rs"]
2
+ mod format;
3
+
4
+ #[unsafe(no_mangle)]
5
+ fn bench_try_ref_from_suffix_with_elems_dynamic_padding(
6
+ source: &[u8],
7
+ count: usize,
8
+ ) -> Option<&format::CocoPacket> {
9
+ match zerocopy::TryFromBytes::try_ref_from_suffix_with_elems(source, count) {
10
+ Ok((_rest, packet)) => Some(packet),
11
+ _ => None,
12
+ }
13
+ }
@@ -0,0 +1,39 @@
1
+ bench_try_ref_from_suffix_with_elems_dynamic_padding:
2
+ mov rcx, rdx
3
+ mov edx, 3
4
+ mov rax, rcx
5
+ mul rdx
6
+ jo .LBB5_1
7
+ cmp rax, -10
8
+ ja .LBB5_1
9
+ lea rdx, [rax + 9]
10
+ not eax
11
+ and eax, 3
12
+ add rax, rdx
13
+ jae .LBB5_4
14
+ .LBB5_1:
15
+ xor r8d, r8d
16
+ mov edx, 1
17
+ mov rax, r8
18
+ ret
19
+ .LBB5_4:
20
+ lea r9d, [rsi + rdi]
21
+ xor edx, edx
22
+ mov r8d, 0
23
+ test r9b, 3
24
+ je .LBB5_5
25
+ mov rax, r8
26
+ ret
27
+ .LBB5_5:
28
+ sub rsi, rax
29
+ jb .LBB5_1
30
+ lea rax, [rdi + rsi]
31
+ movzx esi, word ptr [rdi + rsi]
32
+ cmp si, -16192
33
+ mov edx, 2
34
+ cmove rdx, rcx
35
+ xor r8d, r8d
36
+ cmp esi, 49344
37
+ cmove r8, rax
38
+ mov rax, r8
39
+ ret