html-to-markdown 2.28.0 → 2.28.2

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (196) hide show
  1. checksums.yaml +4 -4
  2. data/Gemfile.lock +6 -6
  3. data/README.md +5 -1
  4. data/ext/html-to-markdown-rb/native/Cargo.lock +1694 -0
  5. data/ext/html-to-markdown-rb/native/Cargo.toml +1 -1
  6. data/lib/html_to_markdown/version.rb +1 -1
  7. data/rust-vendor/html-to-markdown-rs/Cargo.toml +1 -1
  8. data/rust-vendor/html-to-markdown-rs/src/converter/text_node.rs +1 -0
  9. data/rust-vendor/html-to-markdown-rs/src/converter/utility/content.rs +17 -0
  10. data/rust-vendor/html-to-markdown-rs/src/converter/visitor_hooks.rs +8 -5
  11. data/rust-vendor/html-to-markdown-rs/tests/test_issue_218.rs +56 -0
  12. data/rust-vendor/libc/.cargo-checksum.json +1 -1
  13. data/rust-vendor/libc/.cargo_vcs_info.json +1 -1
  14. data/rust-vendor/libc/CHANGELOG.md +19 -0
  15. data/rust-vendor/libc/Cargo.lock +1 -1
  16. data/rust-vendor/libc/Cargo.toml +1 -1
  17. data/rust-vendor/libc/Cargo.toml.orig +1 -1
  18. data/rust-vendor/libc/build.rs +3 -3
  19. data/rust-vendor/libc/src/fuchsia/mod.rs +2 -0
  20. data/rust-vendor/libc/src/hermit.rs +1 -0
  21. data/rust-vendor/libc/src/lib.rs +1 -0
  22. data/rust-vendor/libc/src/new/linux_uapi/linux/mod.rs +1 -0
  23. data/rust-vendor/libc/src/new/linux_uapi/linux/pidfd.rs +59 -0
  24. data/rust-vendor/libc/src/new/mod.rs +3 -0
  25. data/rust-vendor/libc/src/new/netbsd/sys/file.rs +16 -0
  26. data/rust-vendor/libc/src/new/netbsd/sys/mod.rs +2 -0
  27. data/rust-vendor/libc/src/new/netbsd/sys/socket.rs +44 -0
  28. data/rust-vendor/libc/src/new/qurt/mod.rs +2 -0
  29. data/rust-vendor/libc/src/solid/mod.rs +1 -0
  30. data/rust-vendor/libc/src/switch.rs +1 -0
  31. data/rust-vendor/libc/src/teeos/mod.rs +2 -0
  32. data/rust-vendor/libc/src/trusty.rs +1 -0
  33. data/rust-vendor/libc/src/unix/bsd/apple/b64/mod.rs +1 -0
  34. data/rust-vendor/libc/src/unix/bsd/netbsdlike/netbsd/mod.rs +31 -0
  35. data/rust-vendor/libc/src/unix/bsd/netbsdlike/openbsd/mod.rs +92 -0
  36. data/rust-vendor/libc/src/unix/hurd/mod.rs +1 -0
  37. data/rust-vendor/libc/src/unix/linux_like/linux/gnu/mod.rs +1 -0
  38. data/rust-vendor/libc/src/unix/linux_like/linux/mod.rs +22 -46
  39. data/rust-vendor/libc/src/unix/mod.rs +2 -0
  40. data/rust-vendor/libc/src/unix/newlib/espidf/mod.rs +2 -0
  41. data/rust-vendor/libc/src/unix/redox/mod.rs +2 -2
  42. data/rust-vendor/libc/src/vxworks/mod.rs +46 -0
  43. data/rust-vendor/libc/src/wasi/mod.rs +2 -0
  44. data/rust-vendor/libc/src/windows/mod.rs +2 -0
  45. data/rust-vendor/uuid/.cargo-checksum.json +1 -1
  46. data/rust-vendor/uuid/.cargo_vcs_info.json +1 -1
  47. data/rust-vendor/uuid/Cargo.lock +71 -137
  48. data/rust-vendor/uuid/Cargo.toml +4 -4
  49. data/rust-vendor/uuid/Cargo.toml.orig +4 -4
  50. data/rust-vendor/uuid/README.md +3 -3
  51. data/rust-vendor/uuid/src/lib.rs +4 -4
  52. data/rust-vendor/zerocopy/.cargo-checksum.json +1 -1
  53. data/rust-vendor/zerocopy/.cargo_vcs_info.json +1 -1
  54. data/rust-vendor/zerocopy/Cargo.lock +3 -3
  55. data/rust-vendor/zerocopy/Cargo.toml +178 -4
  56. data/rust-vendor/zerocopy/Cargo.toml.orig +5 -5
  57. data/rust-vendor/zerocopy/benches/formats/coco_dynamic_padding.rs +24 -0
  58. data/rust-vendor/zerocopy/benches/formats/coco_dynamic_size.rs +23 -0
  59. data/rust-vendor/zerocopy/benches/formats/coco_static_size.rs +23 -0
  60. data/rust-vendor/zerocopy/benches/read_from_bytes.rs +7 -0
  61. data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64 +15 -0
  62. data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64.mca +65 -0
  63. data/rust-vendor/zerocopy/benches/read_from_prefix.rs +10 -0
  64. data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64 +14 -0
  65. data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64.mca +63 -0
  66. data/rust-vendor/zerocopy/benches/read_from_suffix.rs +10 -0
  67. data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64 +15 -0
  68. data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64.mca +65 -0
  69. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.rs +7 -0
  70. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64 +22 -0
  71. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64.mca +77 -0
  72. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.rs +7 -0
  73. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64 +20 -0
  74. data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64.mca +75 -0
  75. data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.rs +7 -0
  76. data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64 +8 -0
  77. data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64.mca +53 -0
  78. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
  79. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64 +30 -0
  80. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +95 -0
  81. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.rs +10 -0
  82. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64 +16 -0
  83. data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64.mca +65 -0
  84. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.rs +10 -0
  85. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64 +22 -0
  86. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64.mca +77 -0
  87. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.rs +10 -0
  88. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64 +17 -0
  89. data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64.mca +67 -0
  90. data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.rs +10 -0
  91. data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64 +8 -0
  92. data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64.mca +53 -0
  93. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
  94. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
  95. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
  96. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.rs +13 -0
  97. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64 +22 -0
  98. data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64.mca +77 -0
  99. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.rs +10 -0
  100. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64 +23 -0
  101. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64.mca +79 -0
  102. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.rs +10 -0
  103. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64 +13 -0
  104. data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64.mca +63 -0
  105. data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.rs +10 -0
  106. data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64 +13 -0
  107. data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64.mca +61 -0
  108. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
  109. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64 +34 -0
  110. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +99 -0
  111. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.rs +13 -0
  112. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64 +23 -0
  113. data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64.mca +77 -0
  114. data/rust-vendor/zerocopy/benches/transmute.rs +16 -0
  115. data/rust-vendor/zerocopy/benches/transmute.x86-64 +3 -0
  116. data/rust-vendor/zerocopy/benches/transmute.x86-64.mca +43 -0
  117. data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.rs +16 -0
  118. data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64 +4 -0
  119. data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64.mca +45 -0
  120. data/rust-vendor/zerocopy/benches/transmute_ref_static_size.rs +15 -0
  121. data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64 +3 -0
  122. data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64.mca +43 -0
  123. data/rust-vendor/zerocopy/benches/try_read_from_bytes.rs +7 -0
  124. data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64 +23 -0
  125. data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64.mca +79 -0
  126. data/rust-vendor/zerocopy/benches/try_read_from_prefix.rs +10 -0
  127. data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64 +16 -0
  128. data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64.mca +67 -0
  129. data/rust-vendor/zerocopy/benches/try_read_from_suffix.rs +10 -0
  130. data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64 +18 -0
  131. data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64.mca +71 -0
  132. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.rs +7 -0
  133. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64 +24 -0
  134. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64.mca +81 -0
  135. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.rs +7 -0
  136. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64 +22 -0
  137. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64.mca +79 -0
  138. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.rs +7 -0
  139. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64 +13 -0
  140. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64.mca +59 -0
  141. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
  142. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64 +36 -0
  143. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +105 -0
  144. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.rs +10 -0
  145. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64 +18 -0
  146. data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64.mca +69 -0
  147. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.rs +10 -0
  148. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64 +29 -0
  149. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64.mca +91 -0
  150. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.rs +10 -0
  151. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64 +22 -0
  152. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64.mca +77 -0
  153. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.rs +10 -0
  154. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64 +15 -0
  155. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64.mca +63 -0
  156. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
  157. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
  158. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
  159. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.rs +13 -0
  160. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64 +26 -0
  161. data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64.mca +83 -0
  162. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.rs +10 -0
  163. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64 +26 -0
  164. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64.mca +85 -0
  165. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.rs +10 -0
  166. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64 +18 -0
  167. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64.mca +71 -0
  168. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.rs +10 -0
  169. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64 +16 -0
  170. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64.mca +67 -0
  171. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
  172. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64 +39 -0
  173. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +109 -0
  174. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.rs +13 -0
  175. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64 +28 -0
  176. data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64.mca +87 -0
  177. data/rust-vendor/zerocopy/benches/try_transmute.rs +16 -0
  178. data/rust-vendor/zerocopy/benches/try_transmute.x86-64 +9 -0
  179. data/rust-vendor/zerocopy/benches/try_transmute.x86-64.mca +55 -0
  180. data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.rs +18 -0
  181. data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64 +6 -0
  182. data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64.mca +49 -0
  183. data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.rs +17 -0
  184. data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64 +5 -0
  185. data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64.mca +47 -0
  186. data/rust-vendor/zerocopy/rustdoc/style.css +55 -0
  187. data/rust-vendor/zerocopy/src/lib.rs +331 -0
  188. data/rust-vendor/zerocopy/src/macros.rs +48 -1
  189. data/rust-vendor/zerocopy/src/util/macros.rs +199 -0
  190. data/rust-vendor/zerocopy/tests/codegen.rs +111 -0
  191. data/rust-vendor/zerocopy-derive/.cargo-checksum.json +1 -1
  192. data/rust-vendor/zerocopy-derive/.cargo_vcs_info.json +1 -1
  193. data/rust-vendor/zerocopy-derive/Cargo.lock +1 -1
  194. data/rust-vendor/zerocopy-derive/Cargo.toml +1 -1
  195. data/rust-vendor/zerocopy-derive/Cargo.toml.orig +1 -1
  196. metadata +138 -2
@@ -0,0 +1,109 @@
1
+ Iterations: 100
2
+ Instructions: 3500
3
+ Total Cycles: 1144
4
+ Total uOps: 3800
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.32
8
+ IPC: 3.06
9
+ Block RThroughput: 9.5
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.33 mov rcx, rdx
22
+ 1 1 0.33 mov edx, 3
23
+ 1 1 0.33 mov rax, rcx
24
+ 2 4 1.00 mul rdx
25
+ 1 1 1.00 jo .LBB5_1
26
+ 1 1 0.33 cmp rax, -10
27
+ 1 1 1.00 ja .LBB5_1
28
+ 1 1 0.50 lea rdx, [rax + 9]
29
+ 1 1 0.33 not eax
30
+ 1 1 0.33 and eax, 3
31
+ 1 1 0.33 add rax, rdx
32
+ 1 1 1.00 jae .LBB5_4
33
+ 1 0 0.25 xor r8d, r8d
34
+ 1 1 0.33 mov edx, 1
35
+ 1 1 0.33 mov rax, r8
36
+ 1 1 1.00 U ret
37
+ 1 1 0.50 lea r9d, [rsi + rdi]
38
+ 1 0 0.25 xor edx, edx
39
+ 1 1 0.33 mov r8d, 0
40
+ 1 1 0.33 test r9b, 3
41
+ 1 1 1.00 je .LBB5_5
42
+ 1 1 0.33 mov rax, r8
43
+ 1 1 1.00 U ret
44
+ 1 1 0.33 sub rsi, rax
45
+ 1 1 1.00 jb .LBB5_1
46
+ 1 1 0.50 lea rax, [rdi + rsi]
47
+ 1 5 0.50 * movzx esi, word ptr [rdi + rsi]
48
+ 1 1 0.33 cmp si, -16192
49
+ 1 1 0.33 mov edx, 2
50
+ 2 2 0.67 cmove rdx, rcx
51
+ 1 0 0.25 xor r8d, r8d
52
+ 1 1 0.33 cmp esi, 49344
53
+ 2 2 0.67 cmove r8, rax
54
+ 1 1 0.33 mov rax, r8
55
+ 1 1 1.00 U ret
56
+
57
+
58
+ Resources:
59
+ [0] - SBDivider
60
+ [1] - SBFPDivider
61
+ [2] - SBPort0
62
+ [3] - SBPort1
63
+ [4] - SBPort4
64
+ [5] - SBPort5
65
+ [6.0] - SBPort23
66
+ [6.1] - SBPort23
67
+
68
+
69
+ Resource pressure per iteration:
70
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
71
+ - - 11.32 11.32 - 11.36 0.50 0.50
72
+
73
+ Resource pressure by instruction:
74
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
75
+ - - 0.32 0.67 - 0.01 - - mov rcx, rdx
76
+ - - 0.66 0.18 - 0.16 - - mov edx, 3
77
+ - - 1.00 - - - - - mov rax, rcx
78
+ - - 1.00 1.00 - - - - mul rdx
79
+ - - - - - 1.00 - - jo .LBB5_1
80
+ - - 0.01 0.99 - - - - cmp rax, -10
81
+ - - - - - 1.00 - - ja .LBB5_1
82
+ - - 0.99 0.01 - - - - lea rdx, [rax + 9]
83
+ - - 0.01 0.99 - - - - not eax
84
+ - - 0.02 0.98 - - - - and eax, 3
85
+ - - 0.02 0.98 - - - - add rax, rdx
86
+ - - - - - 1.00 - - jae .LBB5_4
87
+ - - - - - - - - xor r8d, r8d
88
+ - - 0.66 0.01 - 0.33 - - mov edx, 1
89
+ - - 0.50 - - 0.50 - - mov rax, r8
90
+ - - - - - 1.00 - - ret
91
+ - - 0.99 0.01 - - - - lea r9d, [rsi + rdi]
92
+ - - - - - - - - xor edx, edx
93
+ - - 0.50 0.32 - 0.18 - - mov r8d, 0
94
+ - - 0.16 0.17 - 0.67 - - test r9b, 3
95
+ - - - - - 1.00 - - je .LBB5_5
96
+ - - 0.33 0.33 - 0.34 - - mov rax, r8
97
+ - - - - - 1.00 - - ret
98
+ - - - 0.51 - 0.49 - - sub rsi, rax
99
+ - - - - - 1.00 - - jb .LBB5_1
100
+ - - 0.16 0.84 - - - - lea rax, [rdi + rsi]
101
+ - - - - - - 0.50 0.50 movzx esi, word ptr [rdi + rsi]
102
+ - - 0.02 0.98 - - - - cmp si, -16192
103
+ - - 1.00 - - - - - mov edx, 2
104
+ - - 0.99 0.84 - 0.17 - - cmove rdx, rcx
105
+ - - - - - - - - xor r8d, r8d
106
+ - - 0.98 - - 0.02 - - cmp esi, 49344
107
+ - - 0.99 0.52 - 0.49 - - cmove r8, rax
108
+ - - 0.01 0.99 - - - - mov rax, r8
109
+ - - - - - 1.00 - - ret
@@ -0,0 +1,13 @@
1
+ #[path = "formats/coco_dynamic_size.rs"]
2
+ mod format;
3
+
4
+ #[unsafe(no_mangle)]
5
+ fn bench_try_ref_from_suffix_with_elems_dynamic_size(
6
+ source: &[u8],
7
+ count: usize,
8
+ ) -> Option<&format::CocoPacket> {
9
+ match zerocopy::TryFromBytes::try_ref_from_suffix_with_elems(source, count) {
10
+ Ok((_rest, packet)) => Some(packet),
11
+ _ => None,
12
+ }
13
+ }
@@ -0,0 +1,28 @@
1
+ bench_try_ref_from_suffix_with_elems_dynamic_size:
2
+ movabs rax, 9223372036854775805
3
+ cmp rdx, rax
4
+ ja .LBB5_1
5
+ lea r8d, [rsi + rdi]
6
+ xor ecx, ecx
7
+ mov eax, 0
8
+ test r8b, 1
9
+ jne .LBB5_5
10
+ lea rax, [2*rdx + 4]
11
+ sub rsi, rax
12
+ jae .LBB5_4
13
+ .LBB5_1:
14
+ xor eax, eax
15
+ mov edx, 1
16
+ ret
17
+ .LBB5_4:
18
+ lea r8, [rdi + rsi]
19
+ movzx esi, word ptr [rdi + rsi]
20
+ cmp si, -16192
21
+ mov ecx, 2
22
+ cmove rcx, rdx
23
+ xor eax, eax
24
+ cmp esi, 49344
25
+ cmove rax, r8
26
+ .LBB5_5:
27
+ mov rdx, rcx
28
+ ret
@@ -0,0 +1,87 @@
1
+ Iterations: 100
2
+ Instructions: 2400
3
+ Total Cycles: 1107
4
+ Total uOps: 2600
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 2.35
8
+ IPC: 2.17
9
+ Block RThroughput: 6.5
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.33 movabs rax, 9223372036854775805
22
+ 1 1 0.33 cmp rdx, rax
23
+ 1 1 1.00 ja .LBB5_1
24
+ 1 1 0.50 lea r8d, [rsi + rdi]
25
+ 1 0 0.25 xor ecx, ecx
26
+ 1 1 0.33 mov eax, 0
27
+ 1 1 0.33 test r8b, 1
28
+ 1 1 1.00 jne .LBB5_5
29
+ 1 1 0.50 lea rax, [2*rdx + 4]
30
+ 1 1 0.33 sub rsi, rax
31
+ 1 1 1.00 jae .LBB5_4
32
+ 1 0 0.25 xor eax, eax
33
+ 1 1 0.33 mov edx, 1
34
+ 1 1 1.00 U ret
35
+ 1 1 0.50 lea r8, [rdi + rsi]
36
+ 1 5 0.50 * movzx esi, word ptr [rdi + rsi]
37
+ 1 1 0.33 cmp si, -16192
38
+ 1 1 0.33 mov ecx, 2
39
+ 2 2 0.67 cmove rcx, rdx
40
+ 1 0 0.25 xor eax, eax
41
+ 1 1 0.33 cmp esi, 49344
42
+ 2 2 0.67 cmove rax, r8
43
+ 1 1 0.33 mov rdx, rcx
44
+ 1 1 1.00 U ret
45
+
46
+
47
+ Resources:
48
+ [0] - SBDivider
49
+ [1] - SBFPDivider
50
+ [2] - SBPort0
51
+ [3] - SBPort1
52
+ [4] - SBPort4
53
+ [5] - SBPort5
54
+ [6.0] - SBPort23
55
+ [6.1] - SBPort23
56
+
57
+
58
+ Resource pressure per iteration:
59
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
60
+ - - 6.99 7.00 - 8.01 0.50 0.50
61
+
62
+ Resource pressure by instruction:
63
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
64
+ - - 0.02 0.95 - 0.03 - - movabs rax, 9223372036854775805
65
+ - - 0.93 0.04 - 0.03 - - cmp rdx, rax
66
+ - - - - - 1.00 - - ja .LBB5_1
67
+ - - 0.96 0.04 - - - - lea r8d, [rsi + rdi]
68
+ - - - - - - - - xor ecx, ecx
69
+ - - 0.95 0.02 - 0.03 - - mov eax, 0
70
+ - - 0.95 0.05 - - - - test r8b, 1
71
+ - - - - - 1.00 - - jne .LBB5_5
72
+ - - 0.06 0.94 - - - - lea rax, [2*rdx + 4]
73
+ - - 0.93 0.07 - - - - sub rsi, rax
74
+ - - - - - 1.00 - - jae .LBB5_4
75
+ - - - - - - - - xor eax, eax
76
+ - - 0.03 0.95 - 0.02 - - mov edx, 1
77
+ - - - - - 1.00 - - ret
78
+ - - 0.97 0.03 - - - - lea r8, [rdi + rsi]
79
+ - - - - - - 0.50 0.50 movzx esi, word ptr [rdi + rsi]
80
+ - - 0.03 0.97 - - - - cmp si, -16192
81
+ - - 0.05 0.94 - 0.01 - - mov ecx, 2
82
+ - - 0.06 0.98 - 0.96 - - cmove rcx, rdx
83
+ - - - - - - - - xor eax, eax
84
+ - - 0.97 0.03 - - - - cmp esi, 49344
85
+ - - 0.06 0.96 - 0.98 - - cmove rax, r8
86
+ - - 0.02 0.03 - 0.95 - - mov rdx, rcx
87
+ - - - - - 1.00 - - ret
@@ -0,0 +1,16 @@
1
+ use zerocopy::Unalign;
2
+ use zerocopy_derive::*;
3
+
4
+ #[path = "formats/coco_static_size.rs"]
5
+ mod format;
6
+
7
+ #[derive(IntoBytes, KnownLayout, Immutable)]
8
+ #[repr(C)]
9
+ struct MinimalViableSource {
10
+ bytes: [u8; 6],
11
+ }
12
+
13
+ #[unsafe(no_mangle)]
14
+ fn bench_try_transmute(source: MinimalViableSource) -> Option<Unalign<format::CocoPacket>> {
15
+ zerocopy::try_transmute!(source).ok()
16
+ }
@@ -0,0 +1,9 @@
1
+ bench_try_transmute:
2
+ movzx ecx, di
3
+ xor eax, eax
4
+ cmp ecx, 49344
5
+ sete al
6
+ and rdi, -65536
7
+ xor rax, 49345
8
+ or rax, rdi
9
+ ret
@@ -0,0 +1,55 @@
1
+ Iterations: 100
2
+ Instructions: 800
3
+ Total Cycles: 238
4
+ Total uOps: 800
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.36
8
+ IPC: 3.36
9
+ Block RThroughput: 2.0
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.33 movzx ecx, di
22
+ 1 0 0.25 xor eax, eax
23
+ 1 1 0.33 cmp ecx, 49344
24
+ 1 1 0.50 sete al
25
+ 1 1 0.33 and rdi, -65536
26
+ 1 1 0.33 xor rax, 49345
27
+ 1 1 0.33 or rax, rdi
28
+ 1 1 1.00 U ret
29
+
30
+
31
+ Resources:
32
+ [0] - SBDivider
33
+ [1] - SBFPDivider
34
+ [2] - SBPort0
35
+ [3] - SBPort1
36
+ [4] - SBPort4
37
+ [5] - SBPort5
38
+ [6.0] - SBPort23
39
+ [6.1] - SBPort23
40
+
41
+
42
+ Resource pressure per iteration:
43
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
44
+ - - 2.33 2.33 - 2.34 - -
45
+
46
+ Resource pressure by instruction:
47
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
48
+ - - 0.32 0.67 - 0.01 - - movzx ecx, di
49
+ - - - - - - - - xor eax, eax
50
+ - - 0.33 0.67 - - - - cmp ecx, 49344
51
+ - - 1.00 - - - - - sete al
52
+ - - 0.67 0.33 - - - - and rdi, -65536
53
+ - - - 0.66 - 0.34 - - xor rax, 49345
54
+ - - 0.01 - - 0.99 - - or rax, rdi
55
+ - - - - - 1.00 - - ret
@@ -0,0 +1,18 @@
1
+ use zerocopy_derive::*;
2
+
3
+ #[path = "formats/coco_dynamic_size.rs"]
4
+ mod format;
5
+
6
+ #[derive(IntoBytes, KnownLayout, Immutable)]
7
+ #[repr(C, align(2))]
8
+ struct MinimalViableSource {
9
+ header: [u8; 6],
10
+ trailer: [[u8; 2]],
11
+ }
12
+
13
+ #[unsafe(no_mangle)]
14
+ fn bench_try_transmute_ref_dynamic_size(
15
+ source: &MinimalViableSource,
16
+ ) -> Option<&format::CocoPacket> {
17
+ zerocopy::try_transmute_ref!(source).ok()
18
+ }
@@ -0,0 +1,6 @@
1
+ bench_try_transmute_ref_dynamic_size:
2
+ lea rdx, [rsi + 1]
3
+ xor eax, eax
4
+ cmp word ptr [rdi], -16192
5
+ cmove rax, rdi
6
+ ret
@@ -0,0 +1,49 @@
1
+ Iterations: 100
2
+ Instructions: 500
3
+ Total Cycles: 209
4
+ Total uOps: 700
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.35
8
+ IPC: 2.39
9
+ Block RThroughput: 1.8
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 1 0.50 lea rdx, [rsi + 1]
22
+ 1 0 0.25 xor eax, eax
23
+ 2 6 0.50 * cmp word ptr [rdi], -16192
24
+ 2 2 0.67 cmove rax, rdi
25
+ 1 1 1.00 U ret
26
+
27
+
28
+ Resources:
29
+ [0] - SBDivider
30
+ [1] - SBFPDivider
31
+ [2] - SBPort0
32
+ [3] - SBPort1
33
+ [4] - SBPort4
34
+ [5] - SBPort5
35
+ [6.0] - SBPort23
36
+ [6.1] - SBPort23
37
+
38
+
39
+ Resource pressure per iteration:
40
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
41
+ - - 1.50 1.51 - 1.99 0.50 0.50
42
+
43
+ Resource pressure by instruction:
44
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
45
+ - - 0.51 0.49 - - - - lea rdx, [rsi + 1]
46
+ - - - - - - - - xor eax, eax
47
+ - - - 0.02 - 0.98 0.50 0.50 cmp word ptr [rdi], -16192
48
+ - - 0.99 1.00 - 0.01 - - cmove rax, rdi
49
+ - - - - - 1.00 - - ret
@@ -0,0 +1,17 @@
1
+ use zerocopy_derive::*;
2
+
3
+ #[path = "formats/coco_static_size.rs"]
4
+ mod format;
5
+
6
+ #[derive(IntoBytes, KnownLayout, Immutable)]
7
+ #[repr(C, align(2))]
8
+ struct MinimalViableSource {
9
+ bytes: [u8; 6],
10
+ }
11
+
12
+ #[unsafe(no_mangle)]
13
+ fn bench_try_transmute_ref_static_size(
14
+ source: &MinimalViableSource,
15
+ ) -> Option<&format::CocoPacket> {
16
+ zerocopy::try_transmute_ref!(source).ok()
17
+ }
@@ -0,0 +1,5 @@
1
+ bench_try_transmute_ref_static_size:
2
+ xor eax, eax
3
+ cmp word ptr [rdi], -16192
4
+ cmove rax, rdi
5
+ ret
@@ -0,0 +1,47 @@
1
+ Iterations: 100
2
+ Instructions: 400
3
+ Total Cycles: 160
4
+ Total uOps: 600
5
+
6
+ Dispatch Width: 4
7
+ uOps Per Cycle: 3.75
8
+ IPC: 2.50
9
+ Block RThroughput: 1.5
10
+
11
+
12
+ Instruction Info:
13
+ [1]: #uOps
14
+ [2]: Latency
15
+ [3]: RThroughput
16
+ [4]: MayLoad
17
+ [5]: MayStore
18
+ [6]: HasSideEffects (U)
19
+
20
+ [1] [2] [3] [4] [5] [6] Instructions:
21
+ 1 0 0.25 xor eax, eax
22
+ 2 6 0.50 * cmp word ptr [rdi], -16192
23
+ 2 2 0.67 cmove rax, rdi
24
+ 1 1 1.00 U ret
25
+
26
+
27
+ Resources:
28
+ [0] - SBDivider
29
+ [1] - SBFPDivider
30
+ [2] - SBPort0
31
+ [3] - SBPort1
32
+ [4] - SBPort4
33
+ [5] - SBPort5
34
+ [6.0] - SBPort23
35
+ [6.1] - SBPort23
36
+
37
+
38
+ Resource pressure per iteration:
39
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1]
40
+ - - 1.02 1.48 - 1.50 0.50 0.50
41
+
42
+ Resource pressure by instruction:
43
+ [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
44
+ - - - - - - - - xor eax, eax
45
+ - - 0.02 0.49 - 0.49 0.50 0.50 cmp word ptr [rdi], -16192
46
+ - - 1.00 0.99 - 0.01 - - cmove rax, rdi
47
+ - - - - - 1.00 - - ret
@@ -0,0 +1,55 @@
1
+ /*
2
+ Copyright 2026 The Fuchsia Authors
3
+
4
+ Licensed under a BSD-style license <LICENSE-BSD>, Apache License, Version 2.0
5
+ <LICENSE-APACHE or https://www.apache.org/licenses/LICENSE-2.0>, or the MIT
6
+ license <LICENSE-MIT or https://opensource.org/licenses/MIT>, at your option.
7
+ This file may not be copied, modified, or distributed except according to
8
+ those terms.
9
+ */
10
+
11
+ .codegen-tabs {
12
+ display: grid;
13
+ grid-template-columns: repeat(var(--arity), minmax(200px, 1fr));
14
+ grid-template-rows: auto 1fr;
15
+ column-gap: 1rem;
16
+ }
17
+
18
+ .codegen-tabs:not(:has(> details[open]))::after {
19
+ grid-column: 1/-1;
20
+ content: 'Click one of the above headers to expand its contents.';
21
+ font-style: italic;
22
+ font-size: small;
23
+ text-align: center;
24
+ }
25
+
26
+ .codegen-tabs details {
27
+ display: grid;
28
+ grid-column: 1 / -1;
29
+ grid-row: 1 / span 2;
30
+ grid-template-columns: subgrid;
31
+ grid-template-rows: subgrid;
32
+ }
33
+
34
+ .codegen-tabs summary {
35
+ display: grid;
36
+ grid-column: var(--n) / span 1;
37
+ grid-row: 1;
38
+ z-index: 1;
39
+ border-bottom: 2px solid var(--headings-border-bottom-color);
40
+ cursor: pointer;
41
+ }
42
+
43
+ .codegen-tabs details[open] > summary {
44
+ background-color: var(--code-block-background-color);
45
+ border-bottom-color: var(--target-border-color);
46
+ }
47
+
48
+ .codegen-tabs details::details-content {
49
+ grid-column: 1 / -1;
50
+ grid-row: 2;
51
+ }
52
+
53
+ .codegen-tabs details:not([open])::details-content {
54
+ display: none;
55
+ }