badline 0.16.1 → 0.17.0

data/lib/badline/drives/model8050/fdc_bus.rb

@@ -0,0 +1,102 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The floppy controller's bus (schematic 8050001, sheet 2), which
+      # decodes A0-A12 only, so it repeats every 8 KB. A 74LS42 on A10-A12
+      # picks a 1 KB block:
+      #
+      # $0000-$03FF - the 6530 and the VIA: with A7 set the 6530's
+      #               registers, else with A6 set the VIA's, else the
+      #               6530's 64 bytes of RAM, which the controller also
+      #               uses as its stack at $0100
+      # $0400-$13FF - the common RAM
+      # $1400-$1BFF - nothing: open bus
+      # $1C00-$1FFF - the 6530's ROM
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class FDCBus
+        include Addressable
+
+        attr_reader :common, :via, :rriot
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model8050::Idle).
+        attr_reader :common_changes
+
+        # Whether a counter or an interrupt flag has been read since it was
+        # last cleared (Model8050::Idle).
+        attr_accessor :volatile
+
+        def initialize(common:, via:, rriot:)
+          addressable_at(0, length: 2**16)
+          @common = common
+          @via = via
+          @rriot = rriot
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          addr &= 0x1fff
+          @data = if addr < 0x0400
+                    peek_chips(addr)
+                  elsif addr < 0x1400
+                    @common.peek(addr - 0x0400)
+                  elsif addr >= 0x1c00
+                    @rriot.read_rom(addr)
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          addr &= 0x1fff
+          if addr < 0x0400
+            poke_chips(addr, value)
+          elsif addr < 0x1400
+            poke_common(addr - 0x0400, value)
+          end
+        end
+
+        private
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+
+        def peek_chips(addr)
+          if addr.anybits?(0x80)
+            @volatile = true if addr.anybits?(0x04)
+            return @rriot.peek(addr & 0x0f)
+          end
+          return peek_via(addr & 0x0f) if addr.anybits?(0x40)
+
+          @rriot.read_ram(addr)
+        end
+
+        # The VIA's counters, shift register and flags move on their own.
+        def peek_via(register)
+          @volatile = true if register.between?(0x04, 0x0a) || register == 0x0d
+          @via.peek(0x40 | register)
+        end
+
+        def poke_chips(addr, value)
+          if addr.anybits?(0x80)
+            @rriot.poke(addr & 0x0f, value)
+          elsif addr.anybits?(0x40)
+            @via.poke(0x40 | (addr & 0x0f), value)
+          else
+            @rriot.write_ram(addr, value)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/idle.rb

@@ -0,0 +1,177 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # Sleeping through the two processors' idle loops, exactly.
+      #
+      # With nothing to do, the IP goes round DOS 2.7's idle loop from
+      # IP_LOOP, and the FDC round its job loop from FDC_LOOP, each pass
+      # finding the job queue empty, until ATN interrupts the IP or the
+      # 6530's timer the FDC, every 5 ms. A pass puts back what it found,
+      # so each processor comes back to its loop's start as it left it, and
+      # only the chips' counters and the cycle counts move.
+      #
+      # Each time a processor comes to its loop's start, the unit compares
+      # what that processor sees with what it saw last time round: the CPU
+      # (Engine::IdleCPU#idle_state), its chips but for their counters, its
+      # RAM and the common RAM, and on the FDC's side the drives. The same,
+      # with no read of a counter or an interrupt flag between (the buses'
+      # volatile), makes the pass repeatable. Once both processors have a
+      # repeatable pass, with the motors off, no head stepping, no disk
+      # going in or out and no interrupt pulled, the unit sleeps:
+      # host_cycle! only counts the cycles it owes, until one of the chips'
+      # counters is due to pull IRQ (quiet_cycles), the controller moves a
+      # line of the bus, or something outside reads or changes the unit
+      # (settle!).
+      #
+      # Waking runs the counters on in bulk, counts off each processor's
+      # whole passes, and runs the rest of a pass on that processor alone.
+      # Its passes touch nothing the other one or the counters move, so the
+      # order the two run in doesn't matter. Then the unit runs cycle by
+      # cycle again. Woken by a counter, it keeps the passes it found, and
+      # sleeps again as soon as both repeat: the IP's, which the timer's
+      # interrupt doesn't reach, at once, and the FDC's a pass after its
+      # interrupt. Woken from outside, it finds both afresh.
+      module Idle
+        IP_LOOP = 0xc5a1
+        FDC_LOOP = 0xfc17
+
+        # Whether the unit may sleep through its idle loops.
+        attr_reader :idle_skip
+
+        def idle_skip=(on)
+          settle!
+          @idle_skip = on
+        end
+
+        def asleep? = @asleep
+
+        # Brings the unit up to the present, cycle for cycle, and drops the
+        # passes it found, since whoever called may change it.
+        def settle!
+          wake! if @asleep
+          forget_passes
+        end
+
+        private
+
+        def init_idle
+          @idle_skip = true
+          @asleep = false
+          @owed = 0
+          @budget = 0
+          forget_passes
+        end
+
+        def forget_passes
+          @ip_mark = nil
+          @fdc_mark = nil
+          @ip_pass = nil
+          @fdc_pass = nil
+        end
+
+        # A cycle owed while asleep, which wakes the unit once the budget
+        # is spent.
+        def owe_cycle
+          @owed += 1
+          wake! if @owed >= @budget
+        end
+
+        # Looks for the loops' starts after a cycle run awake. An interrupt
+        # pulled breaks the processor's pass.
+        def watch_loops
+          ip = @ip_cpu
+          @ip_pass = nil if ip.irq
+          @fdc_pass = nil if @fdc_cpu.irq
+          ip_pass_found if ip.program_counter == IP_LOOP && ip.boundary?
+          fdc = @fdc_cpu
+          fdc_pass_found if fdc.program_counter == FDC_LOOP && fdc.boundary?
+        end
+
+        def ip_pass_found
+          state = ip_state
+          @ip_pass = repeated(@ip_mark, state, @ip_cpu, @ip_bus.volatile)
+          @ip_mark = [state, @ip_cpu.cycles, @ip_cpu.instructions]
+          @ip_bus.volatile = false
+          fall_asleep if @ip_pass && @fdc_pass
+        end
+
+        def fdc_pass_found
+          state = fdc_state
+          @fdc_pass = repeated(@fdc_mark, state, @fdc_cpu, @fdc_bus.volatile)
+          @fdc_mark = [state, @fdc_cpu.cycles, @fdc_cpu.instructions]
+          @fdc_bus.volatile = false
+          fall_asleep if @ip_pass && @fdc_pass
+        end
+
+        # The pass since +mark+ as [cycles, instructions] if it left the
+        # processor as it found it, or nil.
+        def repeated(mark, state, cpu, volatile)
+          return nil if mark.nil? || volatile || mark[0] != state
+
+          [cpu.cycles - mark[1], cpu.instructions - mark[2]]
+        end
+
+        def fall_asleep
+          return unless @mechanism.quiet? && !@ip_cpu.irq && !@fdc_cpu.irq
+
+          budget = quiet_cycles
+          return if budget < 2
+
+          @asleep = true
+          @owed = 0
+          @budget = budget
+        end
+
+        # How many cycles the chips can run with no counter pulling IRQ.
+        def quiet_cycles
+          [@data_riot.quiet_cycles, @control_riot.quiet_cycles, @rriot.quiet_cycles, @via.quiet_cycles].min
+        end
+
+        # Runs the cycles owed: the counters in bulk, then each processor's
+        # whole passes and the rest of a pass.
+        def wake!
+          owed = @owed
+          @asleep = false
+          @owed = 0
+          return if owed.zero?
+
+          @data_riot.fast_forward(owed)
+          @control_riot.fast_forward(owed)
+          @rriot.fast_forward(owed)
+          @via.fast_forward(owed)
+          skip(@ip_cpu, @ip_pass, @ip_mark, owed)
+          skip(@fdc_cpu, @fdc_pass, @fdc_mark, owed)
+          @cycles += owed
+        end
+
+        # Counts off the processor's whole passes, moving its mark on with
+        # them, and runs the rest on the processor alone.
+        def skip(cpu, pass, mark, owed)
+          passes = owed / pass[0]
+          cpu.fast_forward(passes * pass[0], passes * pass[1])
+          mark[1] += passes * pass[0]
+          mark[2] += passes * pass[1]
+          (owed - (passes * pass[0])).times { cpu.cycle! }
+        end
+
+        # What the IP sees: its CPU, its RIOTs but for their counters, its
+        # bus's last byte and the common RAM, as the count of the writes
+        # that changed it.
+        def ip_state
+          [*@ip_cpu.idle_state, *@data_riot.idle_state, *@control_riot.idle_state, @ip_bus.data, common_changes]
+        end
+
+        # What the FDC sees: its CPU, the VIA and the 6530 but for their
+        # counters, its bus's last byte, the drives and the common RAM.
+        def fdc_state
+          [*@fdc_cpu.idle_state, *@via.idle_state, *@rriot.idle_state, @fdc_bus.data, *@mechanism.idle_state,
+           common_changes]
+        end
+
+        def common_changes = @ip_bus.common_changes + @fdc_bus.common_changes
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/ieee_port.rb

@@ -0,0 +1,147 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The interface processor's two 6532s on the IEEE-488 bus
+      # (Drives::IEEEBus), through MC3446 transceivers (schematic 8050001,
+      # sheet 1). UC1 carries the data lines, its port A reading them and
+      # its port B driving them. UE1 carries the rest:
+      #
+      #   PA0  ATN acknowledge (ATNA)     PB0-2  the device number jumpers
+      #   PA1  NDAC out, low while set    PB3    drive 1's LED
+      #   PA2  NRFD out                   PB4    drive 0's LED
+      #   PA3  EOI out                    PB5    the error LED
+      #   PA4  DAV out                    PB6    NDAC in
+      #   PA5  EOI in                     PB7    NRFD in
+      #   PA6  DAV in
+      #   PA7  ATN in, high while ATN is low
+      #
+      # The ports read and drive the lines' levels, 0 for a low line, but
+      # for NDAC out, which pulls NDAC low while set. The DOS sets it as it
+      # waits for a byte and clears it once it has taken one ($C627-$C650).
+      # Every input reads the bus, the drive's own lines included.
+      #
+      # ATN in also reaches UE1's PA7 edge detector, which the DOS arms for
+      # the rising edge ($C58A), so ATN interrupts the interface processor.
+      # While ATN in and ATNA differ, the board pulls NRFD and NDAC low, so
+      # the drive answers ATN before the DOS gets to it, as the 2031 does.
+      #
+      # The device number jumpers ground PB0-2: cutting one adds its weight
+      # to 8.
+      #
+      # The drive takes the controller's lines a host cycle late, as the
+      # 2031 does: latch_host takes them at the end of each host cycle.
+      class IEEEPort
+        ATNA = 0x01
+        NDAC_OUT = 0x02
+        NRFD_OUT = 0x04
+        EOI_OUT = 0x08
+        DAV_OUT = 0x10
+        EOI_IN = 0x20
+        DAV_IN = 0x40
+        ATN_IN = 0x80
+        NDAC_IN = 0x40
+        NRFD_IN = 0x80
+
+        attr_reader :bus
+
+        # The lines the controller pulled, as latch_host took them.
+        attr_accessor :host
+
+        # The RIOTs on the data lines and on the control lines.
+        attr_accessor :data_riot, :control_riot
+
+        def initialize(device:, bus:)
+          raise ArgumentError, "an 8050 is device 8 to 15, not #{device}" unless device.between?(8, 15)
+
+          @jumpers = (device - 8) | 0xf8
+          @host = 0
+          @data_riot = nil
+          @control_riot = nil
+          self.bus = bus
+        end
+
+        def bus=(bus)
+          @bus = bus
+          latch_host
+        end
+
+        # Takes the controller's lines for the drive cycles of the next host
+        # cycle.
+        def latch_host
+          @host = @bus.host_lines
+        end
+
+        # Whether the controller has moved ATN since the last latch_host.
+        def atn_moved? = (@bus.host_lines ^ @host).anybits?(IEEEBus::ATN)
+
+        # Whether the controller has moved any line since the last
+        # latch_host.
+        def lines_moved? = @bus.host_lines != @host
+
+        def atn_low? = @host.anybits?(IEEEBus::ATN)
+
+        # UC1's port A: the data lines.
+        def data_lines = ~@bus.low_lines(@host) & 0xff
+
+        # UE1's port A inputs. ATN in comes through the edge detector's own
+        # pin (RIOT#pa7=), so bit 7 is left high here.
+        def control_a
+          low = @bus.low_lines(@host)
+          value = 0xff
+          value &= ~EOI_IN if low.anybits?(IEEEBus::EOI)
+          value &= ~DAV_IN if low.anybits?(IEEEBus::DAV)
+          value
+        end
+
+        # UE1's port B inputs: the jumpers, NDAC and NRFD.
+        def control_b
+          low = @bus.low_lines(@host)
+          value = @jumpers
+          value &= ~NDAC_IN if low.anybits?(IEEEBus::NDAC)
+          value &= ~NRFD_IN if low.anybits?(IEEEBus::NRFD)
+          value
+        end
+
+        # The lines the drive pulls low while ATN is low or not, as bus bits.
+        def ieee_low_lines(atn)
+          control = @control_riot.port_a_output
+          low = ~@data_riot.port_b_output & IEEEBus::DIO
+          low |= IEEEBus::EOI if control.nobits?(EOI_OUT)
+          low |= IEEEBus::DAV if control.nobits?(DAV_OUT)
+          low |= IEEEBus::NRFD if control.nobits?(NRFD_OUT)
+          low |= IEEEBus::NDAC if control.anybits?(NDAC_OUT)
+          low |= IEEEBus::NRFD | IEEEBus::NDAC if atn != control.anybits?(ATNA)
+          low
+        end
+
+        # Which LEDs UE1 lights: bit 0 drive 1's, bit 1 drive 0's, bit 2 the
+        # error LED.
+        def leds = (@control_riot.port_b_output >> 3) & 0x07
+      end
+
+      # UC1's peripheral: the data lines on port A, port B only driving.
+      class DataLines
+        def initialize(port)
+          @port = port
+        end
+
+        def read_a(_lines) = @port.data_lines
+
+        def read_b(_lines) = 0xff
+      end
+
+      # UE1's peripheral: the control lines and the jumpers.
+      class ControlLines
+        def initialize(port)
+          @port = port
+        end
+
+        def read_a(_lines) = @port.control_a
+
+        def read_b(_lines) = @port.control_b
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/ip_bus.rb

@@ -0,0 +1,93 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The interface processor's bus (schematic 8050001, sheet 1). A
+      # 74LS42 on A12-A15 picks a 4 KB block:
+      #
+      # $0000-$0FFF - the two 6532s. A9 is their RS pin and A7 picks one:
+      #               UC1's RAM at $00-$7F and UE1's at $80-$FF, mirrored at
+      #               $0100 for the stack since A8 isn't decoded, and their
+      #               registers at $0200 (UC1) and $0280 (UE1)
+      # $1000-$4FFF - the common RAM, 1 KB in each block, mirrored through it
+      # $5000-$BFFF - nothing: open bus
+      # $C000-$FFFF - DOS 2.7, 901887-01 and 901888-01
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class IPBus
+        include Addressable
+
+        attr_reader :common, :rom, :data_riot, :control_riot
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model8050::Idle).
+        attr_reader :common_changes
+
+        # Whether a timer or the interrupt flags have been read since it was
+        # last cleared (Model8050::Idle).
+        attr_accessor :volatile
+
+        def initialize(rom:, common:, data_riot:, control_riot:)
+          addressable_at(0, length: 2**16)
+          @rom = rom
+          @common = common
+          @data_riot = data_riot
+          @control_riot = control_riot
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          return @data = @rom.peek(addr) if addr >= 0xc000
+
+          @data = if addr < 0x1000
+                    peek_riots(addr)
+                  elsif addr < 0x5000
+                    @common.peek((((addr >> 12) - 1) << 10) | (addr & 0x03ff))
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          return if addr >= 0x5000
+
+          if addr < 0x1000
+            poke_riots(addr, value)
+          else
+            poke_common((((addr >> 12) - 1) << 10) | (addr & 0x03ff), value)
+          end
+        end
+
+        private
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+
+        def peek_riots(addr)
+          @volatile = true if addr & 0x204 == 0x204
+          if addr.anybits?(0x80)
+            addr.anybits?(0x200) ? @control_riot.peek(addr & 0x1f) : @control_riot.read_ram(addr)
+          else
+            addr.anybits?(0x200) ? @data_riot.peek(addr & 0x1f) : @data_riot.read_ram(addr)
+          end
+        end
+
+        def poke_riots(addr, value)
+          if addr.anybits?(0x80)
+            addr.anybits?(0x200) ? @control_riot.poke(addr & 0x1f, value) : @control_riot.write_ram(addr, value)
+          else
+            addr.anybits?(0x200) ? @data_riot.poke(addr & 0x1f, value) : @data_riot.write_ram(addr, value)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/keyed_state.rb

@@ -0,0 +1,160 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      class Disk
+        # A disk's fields in a keyed snapshot module (BL-D8-DISK, BL-D8-DISK1
+        # for drive 1): the image file's path and how it was opened, the
+        # image as last flushed, embedded under image and image.format, each
+        # track whose cells differ from what the image lays out, as
+        # track<N>, a cell per byte or 256 for a sync, and the tracks
+        # written since the last flush.
+        module KeyedState
+          IMAGE_FORMATS = %w[d80 d82].freeze
+
+          def save_fields(out)
+            image = @image
+            out.text("path", image.path.to_s).bool("read_only", image.read_only?)
+            out.text("image.format", image.is_a?(Storage::D82Image) ? "d82" : "d80")
+            out.bytes("image", image.contents)
+            @tracks.each do |number, cells|
+              out.ints("track#{number}", cells) unless cells == build(number)
+            end
+            out.ints("written", @written.keys)
+          end
+
+          # Puts back the tracks and the writes not yet flushed.
+          def load_track_fields(input)
+            (1..(side_tracks * sides)).each do |number|
+              cells = input.ints("track#{number}", [])
+              @tracks[number] = cells.dup unless cells.empty?
+            end
+            input.ints("written", []).each { |number| @written[number] = true }
+            self
+          end
+        end
+
+        include KeyedState
+
+        # The disk a BL-D8-DISK module holds. A detached reader gets the
+        # image write-protected, and it and a host file that is gone leave
+        # it no path to write back to.
+        def self.from_fields(input, detached: false)
+          path = input.text("path", "")
+          read_only = input.bool("read_only", false) || detached
+          kind = input.choice("image.format", KeyedState::IMAGE_FORMATS, "d80")
+          bytes = input.bytes("image", "".b).bytes
+          path = "" if detached || !File.file?(path)
+          image_class = kind == "d82" ? Storage::D82Image : Storage::D80Image
+          new(image_class.new(path, read_only:, bytes:)).load_track_fields(input)
+        end
+      end
+
+      class Mechanism
+        # The drives' fields in a keyed snapshot module (BL-D8-MECH), a value
+        # a drive in each list: the heads' cylinders, the stepper phases,
+        # each disk's place in its turn and its bit clock, the disk change
+        # under way and the motors, then the byte ready pulse, the byte on
+        # VIA port A and SYNC. The disks load from their own modules.
+        module KeyedState
+          def save_fields(out)
+            out.ints("cylinders", @cylinders).ints("phases", @phases).ints("positions", @positions)
+            out.ints("bit_clocks", @clocks).ints("changing", @changing)
+            out.ints("motors", @motors.map { |on| on ? 1 : 0 }).ints("syncs", @syncs.map { |low| low ? 1 : 0 })
+            out.bool("so_pending", @so_pending).bool("ca1_low", @ca1_low).int("data_in", @data_in)
+          end
+
+          def load_fields(input, disks)
+            @disks = disks
+            input.ints_into("cylinders", @cylinders)
+            input.ints_into("phases", @phases)
+            input.ints_into("positions", @positions)
+            input.ints_into("bit_clocks", @clocks)
+            input.ints_into("changing", @changing)
+            @motors = input.ints("motors", [0, 0]).map { |on| on == 1 }
+            @syncs = input.ints("syncs", [0, 0]).map { |low| low == 1 }
+            @so_pending = input.bool("so_pending", @so_pending)
+            @ca1_low = input.bool("ca1_low", @ca1_low)
+            @data_in = input.byte("data_in", @data_in)
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The unit's own fields in a keyed snapshot module (BL-D8): its model,
+      # its clock phase and cycle count, each bus's last byte, and the
+      # controller's lines as the port latched them, under ieee.*. A save
+      # settles the unit first, so it is awake; a load finds its passes
+      # afresh.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles)
+          out.int("ip_data", @ip_bus.data).int("fdc_data", @fdc_bus.data)
+          out.int("ieee.host", @ieee_port.host)
+          out
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @ip_bus.data = input.byte("ip_data", @ip_bus.data)
+          @fdc_bus.data = input.byte("fdc_data", @fdc_bus.data)
+          @ieee_port.host = input.int("ieee.host", @ieee_port.host)
+        end
+
+        # The unit as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, the common RAM, UC1 and UE1 with their
+        # RAM, each processor, the VIA, the 6530, the drives and each disk
+        # in, drive 1's as -DISK1.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-COMMON") { |out| @common.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-RIOT1") { |out| @data_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RIOT2") { |out| @control_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-IPCPU") { |out| @ip_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-FDCCPU") { |out| @fdc_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-VIA") { |out| @via.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RRIOT") { |out| @rriot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-MECH") { |out| @mechanism.save_fields(out) }
+          [0, 1].each do |drive|
+            disk = @mechanism.disk(drive)
+            sections << Snapshot::Keyed.section(disk_module(name, drive)) { |out| disk.save_fields(out) } if disk
+          end
+          sections
+        end
+
+        # The unit from its modules, `input` being its own. No disk module
+        # means no disk in that drive.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @common.load_fields(modules.required("#{name}-COMMON"), "ram")
+          @data_riot.load_fields(modules.required("#{name}-RIOT1"))
+          @control_riot.load_fields(modules.required("#{name}-RIOT2"))
+          @ip_cpu.load_fields(modules.required("#{name}-IPCPU"))
+          @fdc_cpu.load_fields(modules.required("#{name}-FDCCPU"))
+          @via.load_fields(modules.required("#{name}-VIA"))
+          @rriot.load_fields(modules.required("#{name}-RRIOT"))
+          disks = [0, 1].map do |drive|
+            disk = modules.optional(disk_module(name, drive))
+            disk.nil? ? nil : Disk.from_fields(disk, detached: modules.detached?)
+          end
+          @mechanism.load_fields(modules.required("#{name}-MECH"), disks)
+          @via.restored!
+          @ip_cpu.restored!
+          @fdc_cpu.restored!
+        end
+
+        private
+
+        def disk_module(name, drive) = drive.zero? ? "#{name}-DISK" : "#{name}-DISK1"
+      end
+
+      include KeyedState
+    end
+  end
+end