badline 0.16.1 → 0.17.0

data/lib/badline/snapshot/vice/p500_vicii.rb

@@ -0,0 +1,166 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module P500
+        # VIC-II 1.3 as xcbm5x0 writes it, which runs VICE's line-based
+        # VIC-II rather than x64sc's, so the module is laid out otherwise
+        # than x64sc's under the same name: whether bad lines may happen,
+        # whether this line is one, the vertical border, the colour
+        # buffer, colour RAM, whether the sequencer is idle, the light
+        # pen's trigger and position, the video matrix buffer, the sprites
+        # whose DMA starts next line, a word xcbm5x0 keeps at $00100000,
+        # the beam's cycle and line, the registers, the sprite collisions
+        # pending, the sprites' DMA, the VIC's bank, VC, the matrix's
+        # width, VCBASE, then sprite and drawing fields with the bank
+        # again, the line its picture draws next and its size, and the
+        # picture. xcbm5x0's cycle in the line is badline's column.
+        #
+        # Written: the registers, colour RAM, the buffers, the beam with
+        # its counters and the sprites' DMA as badline's VIC has them, the
+        # bank as TPI2's PC6 and PC7 pick it, and the rest as xcbm5x0
+        # leaves it. The picture is left blank, as xcbm5x0 paints it again.
+        #
+        # Read: the registers, colour RAM, the buffers, the beam with VC,
+        # VCBASE and whether the sequencer is idle, the light pen and the
+        # sprites' DMA, through the x64sc module's reader (VICII::Import).
+        # The row counter follows from the line and YSCROLL, and the
+        # sprites' counters and the borders' flip-flops start afresh.
+        # xcbm5x0's VIC isn't x64sc's, so a program badline runs on from its
+        # snapshot reads the raster a cycle or so off now and then.
+        module VICII
+          NAME = Vice::VICII::NAME
+          MAJOR = 1
+          MINOR = 3
+          ALLOW_BAD_LINES = 0x000
+          BAD_LINE = 0x001
+          BLANK = 0x002
+          COLOR_BUFFER = 0x003
+          COLOR_RAM = 0x02b
+          IDLE = 0x42b
+          LIGHT_PEN = 0x42c
+          MATRIX_BUFFER = 0x42f
+          RAM_BASE = 0x458
+          CYCLE = 0x45c
+          LINE = 0x45d
+          REGISTERS = 0x45f
+          SPRITE_DMA = 0x4a0
+          BANK = 0x4a2
+          VC = 0x4a4
+          VC_ADD = 0x4a6
+          VC_BASE = 0x4a7
+          VIDEO_INT = 0x4a9
+          DRAW_FLAGS = 0x4cd
+          FETCH_BANK = 0x4cf
+          DRAWN_LINE = 0x4d1
+          PICTURE = 0x4d5
+          HEADER = 0x4e1
+          # The picture's size: PAL's and NTSC's.
+          SIZES = { 312 => [504, 312], 263 => [520, 275] }.freeze
+
+          module_function
+
+          def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+          # The lines xcbm5x0's picture has, which name its region.
+          def picture_lines(section) = FieldReader.new(section).skip(PICTURE + 4).dword
+
+          def export(machine)
+            vic = machine.vic
+            width, height = SIZES.fetch(vic.region.lines_per_frame)
+            bytes = Array.new(HEADER + (width * (height + 4)), 0)
+            sequencer(vic, bytes)
+            bytes[COLOR_RAM, 0x400] = Array.new(0x400) { |offset| machine.color_ram.nibble(0xd400 + offset) }
+            beam(vic, bytes)
+            bank = ((machine.tpi2.port_c_output >> 6) & 0x03) << 14
+            [BANK, FETCH_BANK].each { |at| word(bytes, at, bank) }
+            [RAM_BASE + 2, DRAW_FLAGS].each { |at| bytes[at] = 0x10 }
+            bytes[VIDEO_INT] = 1
+            [vic.rasterline, width, height, width].each_with_index do |value, n|
+              dword(bytes, DRAWN_LINE + (4 * n), value)
+            end
+            FieldWriter.new.bytes(bytes).section(NAME, MAJOR, MINOR)
+          end
+
+          # The sequencer's state and the buffers it reads.
+          def sequencer(vic, bytes)
+            state = vic.display_state
+            bytes[ALLOW_BAD_LINES] = state.bad_lines_enabled ? 1 : 0
+            bytes[BAD_LINE] = state.bad_line_condition? ? 1 : 0
+            bytes[BLANK] = vic.sequencer.borders.first ? 1 : 0
+            bytes[COLOR_BUFFER, 40] = vic.color_buffer.map { |value| value || 0 }
+            bytes[IDLE] = state.display? ? 0 : 1
+            bytes[MATRIX_BUFFER, 40] = vic.character_buffer.map { |value| value || 0 }
+          end
+
+          # The beam, the registers and the counters.
+          def beam(vic, bytes)
+            state = vic.display_state
+            bytes[CYCLE] = vic.column
+            word(bytes, LINE, vic.rasterline)
+            bytes[REGISTERS, 0x40] = vic.register_file
+            bytes[SPRITE_DMA] = 8.times.sum { |n| vic.sprites[n].displaying? ? 1 << n : 0 }
+            word(bytes, VC, state.vc)
+            bytes[VC_ADD] = 40
+            word(bytes, VC_BASE, state.vc_base)
+          end
+
+          def word(bytes, at, value) = bytes[at, 2] = [value & 0xffff].pack("v").bytes
+
+          def dword(bytes, at, value) = bytes[at, 4] = [value].pack("V").bytes
+
+          def import(section, vic, color_ram)
+            Import.new(section, vic.region).apply_to(vic, color_ram, 0xd400)
+          end
+
+          # Reads xcbm5x0's module into the fields x64sc's reader puts into
+          # badline's VIC.
+          class Import < Vice::VICII::Import
+            # x64sc's cycle is badline's column plus one, its cycle 0 the
+            # last column of the line before (VICII.vice_cycle).
+            def initialize(section, region)
+              super(nil)
+              bytes = section.data.bytes
+              @registers = bytes[REGISTERS, 0x40]
+              line = bytes[LINE] | (bytes[LINE + 1] << 8)
+              @cycle = (bytes[CYCLE] + 1) % region.cycles_per_line
+              @line = @cycle.zero? ? (line + 1) % region.lines_per_frame : line
+              @frame_start = false
+              @irq_status = @registers[0x19]
+              @raster_match = false
+              @character_buffer = bytes[MATRIX_BUFFER, 40]
+              @color_buffer = bytes[COLOR_BUFFER, 40]
+              read_old_counters(bytes)
+              @color_ram = bytes[COLOR_RAM, 0x400]
+              @sprite_mc = Array.new(8, 0)
+              @sprite_mcbase = Array.new(8, 0)
+              @sprite_exp_ff = 0
+            end
+
+            private
+
+            def read_old_counters(bytes)
+              @bad_lines_enabled = !bytes[ALLOW_BAD_LINES].zero?
+              @collisions = [@registers[0x1e], @registers[0x1f]]
+              @display = bytes[IDLE].zero?
+              @vc_base = bytes[VC_BASE] | (bytes[VC_BASE + 1] << 8)
+              @vc = bytes[VC] | (bytes[VC + 1] << 8)
+              @rc = @display ? (@line - @registers[0x11]) & 0x07 : 7
+              @vmli = 0
+              @lp_low = false
+              @lp_triggered = !bytes[LIGHT_PEN].zero?
+              @fetch_d011 = @registers[0x11]
+              @dma_bits = bytes[SPRITE_DMA]
+              @display_bits = @dma_bits
+              blank = !bytes[BLANK].zero?
+              @vertical_border = blank
+              @vertical_armed = false
+              @main_border = blank
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/pet.rb

@@ -5,13 +5,16 @@ require "badline/snapshot/vice/pet_mem"
 require "badline/snapshot/vice/pet_pias"
 require "badline/snapshot/vice/pet_via"
 require "badline/snapshot/vice/pet_crtc"
+require "badline/snapshot/vice/pet_drive"
+require "badline/snapshot/vice/pet_drive8050"
 require "badline/snapshot/vice/pet_restore"
 
 module Badline
   module Snapshot
     module Vice
-      # xpet's modules for the PET: the CPU, the RAM, the CRTC, both PIAs
-      # and the VIA, written from badline's machine and read into it. Each
+      # xpet's modules for the PET: the CPU, the RAM, the CRTC, both PIAs,
+      # the VIA and a true 2031, written from badline's machine and read
+      # into it. Each
       # module's file says what maps and what is approximated. They go
       # through the PET's own keyed fields (Keyed), which a save writes and a
       # load reads, so they read no chip's insides.
@@ -45,7 +48,8 @@ module Badline
           [MainCPU.export(machine), CPU6809.export(machine), PETMem.export(machine),
            CRTC.export(machine, reader(readers, "BL-CRTC"), reader(readers, "BL-VIDEO")),
            PIAs.export("PIA1", machine.pia1, reader(readers, "BL-PIA1")),
-           PIAs.export("PIA2", machine.pia2, reader(readers, "BL-PIA2")), VIA.export(reader(readers, "BL-VIA"))] +
+           PIAs.export("PIA2", machine.pia2, reader(readers, "BL-PIA2")), VIA.export(reader(readers, "BL-VIA")),
+           *Drive2031.export(machine, readers), *Drive8050.export(machine, readers)] +
             PERIPHERALS.map { |name, major, minor, bytes| FieldWriter.new.bytes(bytes).section(name, major, minor) }
         end
 

data/lib/badline/snapshot/vice/pet_cpu.rb

@@ -25,14 +25,17 @@ module Badline
 
           def reads?(section) = section.major == MAJOR && section.minor == MINOR
 
-          def export(machine)
+          def export(machine) = write(machine, [machine.pia1.irq?, machine.pia2.irq?, machine.via.irq?].count(true))
+
+          # The module for `machine`, whose CPU's IRQ line `irqs` sources
+          # pull.
+          def write(machine, irqs)
             cpu = machine.cpu
             fields = FieldWriter.new.qword(machine.cycles)
             [cpu.a, cpu.x, cpu.y, cpu.stack_pointer].each { |register| fields.byte(register) }
             fields.word(cpu.program_counter).byte(cpu.p)
             fields.dword(0).dword(0).dword(0)
             5.times { fields.qword(0) }
-            irqs = [machine.pia1.irq?, machine.pia2.irq?, machine.via.irq?].count(true)
             fields.dword(irqs).dword(0).dword(irqs.positive? ? IK_IRQ : 0)
             fields.section(NAME, MAJOR, MINOR)
           end

data/lib/badline/snapshot/vice/pet_crtc.rb

@@ -82,7 +82,8 @@ module Badline
             beam = if discrete
                      discrete_beam(video_input)
                    else
-                     crtc_beam(run_on(machine, crtc_input, -CRTC_LEAD % frame_cycles(registers)), registers)
+                     crtc_beam(run_on(fresh_crtc(machine), crtc_input, -CRTC_LEAD % frame_cycles(registers)),
+                               registers)
                    end
             fields = FieldWriter.new.bytes(model.cbm8296? ? SETTINGS_8296 : SETTINGS).word(attributes(model))
             fields.byte(0).byte(columns(model))
@@ -119,10 +120,12 @@ module Badline
 
           def frame_cycles(registers) = (registers[0] + 1) * frame_lines(registers)
 
-          # The BL-CRTC fields of a CRTC loaded with those in `input` and run
-          # `cycles` cycles on its own, in a machine built as `machine` was.
-          def run_on(machine, input, cycles)
-            crtc = PETSetup.of(machine).build.crtc
+          # The CRTC of a machine built as `machine` was, at power-on.
+          def fresh_crtc(machine) = PETSetup.of(machine).build.crtc
+
+          # The BL-CRTC fields of `crtc`, a CRTC of its own, loaded with those
+          # in `input` and run `cycles` cycles.
+          def run_on(crtc, input, cycles)
             crtc.load_fields(input)
             cycles.times { crtc.cycle! }
             Keyed::Reader.parse(Keyed.section("BL-CRTC") { |out| crtc.save_fields(out) })
@@ -135,16 +138,13 @@ module Badline
             %w[adjusting row_display column_display].each { |key| out.bool(key, input.bool(key, false)) }
           end
 
-          # Both move a row's start on at R1 of its last line, and badline's
-          # moves it again where the vertical adjust runs past R9 lines,
-          # which xpet's doesn't.
+          # Both move a row's start on at R1 of its last line.
           def crtc_beam(input, registers)
             column = input.int("column", 0)
             row = input.int("row", 0)
             line = input.int("line", 0)
             adjusting = input.bool("adjusting", false)
             start = input.int("row_start", 0)
-            start = (start - registers[1]) & 0x3fff if adjusting && moved?(line, column, registers)
             rows = registers[4] + 1
             lines = registers[9] + 1
             Beam.new(column:, row: adjusting ? rows : row, raster: adjusting ? 0 : line,
@@ -212,12 +212,7 @@ module Badline
             adjusting = beam.row >= rows
             line = adjusting ? beam.frame_line - (rows * (registers[9] + 1)) : beam.raster
             start = start_address(beam.start, registers, columns, attributes)
-            if adjusting
-              start += registers[1] if line > registers[9]
-            elsif moved?(line, column_of(section), registers)
-              start -= registers[1]
-            end
-            start &= 0x3fff
+            start = (start - registers[1]) & 0x3fff if !adjusting && moved?(line, column_of(section), registers)
             out.bytes("registers", registers.first(Chips::CRTC::MASKS.length)).int("selected", selected(section) & 0x1f)
             out.int("column", 0).int("line", [line, 0].max).int("row", adjusting ? rows - 1 : beam.row)
             out.int("since_hsync", registers[0] + 1 - registers[2]).int("vsync_lines", beam.vsync)

data/lib/badline/snapshot/vice/pet_drive.rb

@@ -0,0 +1,180 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # A true 2031 on device 8, as xpet 3.10, xcbm2 and xcbm5x0 save it with true drive
+        # emulation: DRIVE8 to DRIVE11 2.0, one a unit, DRIVECPU0 1.3, the
+        # drive's 6502 and its RAM, and its VIAs as VIA 2.2 modules,
+        # 2031VIA1D0 at $1800 on the IEEE-488 bus and VIA2D0 at $1C00 on
+        # the mechanism.
+        #
+        # DRIVECPU0 holds the clock, the registers, the last opcode, the
+        # main CPU's clock, more clocks of the drive's interrupt bookkeeping,
+        # then the 2K of RAM from $5C and twelve bytes after it. DRIVE8
+        # holds the head's half track at $10, with track 18 at 36 as badline
+        # numbers them, the speed zone its VIA set at $24, $47 and $4B, the
+        # drive's type as a word at $28, and from $2C the disk's place in
+        # its turn and the clock it was last moved on at. The rest of it,
+        # the read electronics among it, badline doesn't read. xpet's head
+        # rests on a half track two phases on from where badline's stepper
+        # puts it (SLIP).
+        #
+        # Written: the registers and the RAM, the VIAs as the PET's VIA is
+        # written with the stepper's phase moved to xpet's, and DRIVE8 as
+        # xpet saves an idle 2031 but for the head's half track, the zone,
+        # and the disk at the start of its turn as of the snapshot's clock.
+        # The interrupt clocks are written as long past. The snapshot is
+        # settled with the drive's CPU between instructions too
+        # (PET#settle_for_vice!). One taken while the drive is mid-transfer
+        # on the bus may stall there in xpet, as xpet's own snapshots taken
+        # while it searches for a file do.
+        #
+        # Read: the registers, the RAM, the VIAs as the PET's VIA is read,
+        # and the head's half track, with the motor, the LED and the zone
+        # from VIA 2's port B and the stepper's phase as xpet's (SLIP). The
+        # disk turns on from where badline's left it, and the disk in the
+        # drive stays.
+        module Drive2031
+          UNITS = %w[DRIVE8 DRIVE9 DRIVE10 DRIVE11].freeze
+          DRIVE_MAJOR = 2
+          DRIVE_MINOR = 0
+          CPU = "DRIVECPU0"
+          CPU_MAJOR = 1
+          CPU_MINOR = 3
+          VIA1 = "2031VIA1D0"
+          VIA2 = "VIA2D0"
+          NAMES = [*UNITS, CPU, VIA1, VIA2].freeze
+          # Where DRIVECPU0's RAM starts, and its length.
+          RAM_AT = 0x5c
+          RAM_SIZE = 0x800
+          TAIL = 12
+          HALF_TRACK = 0x10
+          ZONES = [0x24, 0x47, 0x4b].freeze
+          SIZE = 145
+          # The disk's place in its turn, and the clock it was last moved on at.
+          TURN = 0x2c
+          # DRIVE8 as xpet saves an idle 2031, and a unit with no drive, by
+          # the bytes that aren't 0.
+          IDLE = { 0x00 => 0x01, 0x01 => 0x01, 0x02 => 0x01, 0x0f => 0x01, 0x10 => 0x25, 0x1a => 0x01, 0x1b => 0xdf,
+                   0x1f => 0x54, 0x20 => 0x55, 0x24 => 0x03, 0x28 => 0xef, 0x29 => 0x07, 0x2c => 0x60, 0x2d => 0x41,
+                   0x2e => 0x0f, 0x30 => 0x17, 0x31 => 0x51, 0x32 => 0x0f, 0x40 => 0x54, 0x41 => 0x01, 0x42 => 0x54,
+                   0x47 => 0x03, 0x4b => 0x03, 0x6f => 0xcd, 0x70 => 0xab, 0x71 => 0x34, 0x72 => 0x12 }.freeze
+          NONE = { 0x00 => 0x01, 0x01 => 0x01, 0x02 => 0x01, 0x0e => 0x01, 0x0f => 0x01, 0x10 => 0x24, 0x1a => 0x01,
+                   0x20 => 0x55, 0x6f => 0xcd, 0x70 => 0xab, 0x71 => 0x34, 0x72 => 0x12, 0x8f => 0x01 }.freeze
+          SLIP = 2
+          MOTOR = 0x04
+          LED = 0x08
+
+          module_function
+
+          # Whether the snapshot has a true 2031.
+          def present?(container) = !container[CPU].nil? && !container[VIA1].nil?
+
+          def reads?(section)
+            case section.name
+            when CPU then section.major == CPU_MAJOR && section.minor == CPU_MINOR
+            when VIA1, VIA2 then VIA.reads?(section)
+            else section.major == DRIVE_MAJOR && section.minor == DRIVE_MINOR
+            end
+          end
+
+          # xpet's modules for the 2031 whose BL-D8 modules `readers` holds,
+          # and none without one or for an 8050 or 8250, which they leave
+          # out.
+          def export(machine, readers)
+            drive = readers["BL-D8"]
+            return [] if drive.nil? || drive.text("model", "2031") != "2031"
+
+            via2 = readers.fetch("BL-D8-VIA2")
+            mechanism = readers.fetch("BL-D8-MECH")
+            zone = ((via2.int("orb", 0) | ~via2.int("ddrb", 0)) >> 5) & 0x03
+            idle = filled(IDLE)
+            idle[HALF_TRACK] = mechanism.int("half_track", 36)
+            ZONES.each { |offset| idle[offset] = zone }
+            idle[TURN, 8] = [0, machine.cycles & 0xffff_ffff].pack("VV").bytes
+            [FieldWriter.new.bytes(idle).section(UNITS.first, DRIVE_MAJOR, DRIVE_MINOR),
+             *UNITS.drop(1).map { |name| unit(NONE, name) },
+             cpu(machine, readers.fetch("BL-D8-CPU"), readers.fetch("BL-D8-RAM")),
+             stepper(VIA.export(via2, VIA2), mechanism.int("slip", 0)),
+             VIA.export(readers.fetch("BL-D8-VIA1"), VIA1)]
+          end
+
+          # VIA 2's port B with the stepper's phase as xpet's head takes it
+          # where badline's head is: SLIP on from badline's.
+          def stepper(section, slip)
+            bytes = section.data.bytes
+            bytes[2] = (bytes[2] & 0xfc) | ((bytes[2] - slip + SLIP) & 0x03)
+            section.with(data: bytes.pack("C*"))
+          end
+
+          def unit(bytes, name) = FieldWriter.new.bytes(filled(bytes)).section(name, DRIVE_MAJOR, DRIVE_MINOR)
+
+          def filled(bytes) = Array.new(SIZE) { |offset| bytes.fetch(offset, 0) }
+
+          def cpu(machine, input, ram)
+            bytes = ram.bytes("ram", "".b).bytes
+            cpu_section(machine, input, Array.new(RAM_SIZE) { |address| bytes[address] || 0 })
+          end
+
+          # The drive's clock, at its 1 MHz, for the machine's at its own.
+          def drive_clock(machine) = machine.cycles * Drives::Model2031::CLOCK_HZ / machine.timing.clock_hz
+
+          # DRIVECPU0 for a drive CPU whose BL- fields `input` holds, with
+          # `ram` the drive's RAM as xpet lays it out: the drive's clock,
+          # the registers, the machine's clock, the drive's clock again, and
+          # the RAM.
+          def cpu_section(machine, input, ram)
+            clock = drive_clock(machine)
+            fields = FieldWriter.new.qword(clock)
+            %w[a x y sp].each { |key| fields.byte(input.int(key, 0)) }
+            fields.word(input.int("pc", 0)).byte(input.int("p", 0x20)).dword(0)
+            fields.qword(machine.cycles).zeros(16).qword(clock).zeros(1).qword(0).zeros(8).qword(0)
+            fields.zeros(16).bytes(ram).zeros(TAIL)
+            fields.section(CPU, CPU_MAJOR, CPU_MINOR)
+          end
+
+          # The 2031's keyed modules, named for device 8, from the
+          # snapshot's, with `disk` the drive's disk module badline keeps,
+          # or nil.
+          def import(container, disk)
+            via2 = container[VIA2]
+            sections = [Keyed.section("BL-D8") { |out| drive(container, out) },
+                        Keyed.section("BL-D8-RAM") { |out| out.bytes("ram", ram(container[CPU])) },
+                        Keyed.section("BL-D8-VIA1") { |out| VIA.import(container[VIA1], out) },
+                        Keyed.section("BL-D8-VIA2") { |out| VIA.import(via2, out) },
+                        Keyed.section("BL-D8-CPU") { |out| registers(container[CPU], out) },
+                        Keyed.section("BL-D8-MECH") { |out| mechanism(container, via2, out) }]
+            disk ? sections + [disk] : sections
+          end
+
+          def drive(container, out)
+            out.text("model", "2031").int("phase", 0).int("cycles", FieldReader.new(container[CPU]).qword)
+            out.bool("so_pending", false)
+          end
+
+          def ram(section) = FieldReader.new(section).skip(RAM_AT).string(RAM_SIZE)
+
+          def registers(section, out)
+            fields = FieldReader.new(section)
+            clock = fields.qword
+            out.int("a", fields.byte).int("x", fields.byte).int("y", fields.byte).int("sp", fields.byte)
+            out.int("pc", fields.word).int("p", fields.byte).int("cycles", clock)
+          end
+
+          # The head where DRIVE8 has it, and the stepper's phase as VIA 2
+          # drives it, which the half track's low two bits stand for.
+          def mechanism(container, via2, out)
+            half_track = FieldReader.new(container[UNITS.first]).skip(HALF_TRACK).byte
+            bytes = FieldReader.new(via2).bytes(4)
+            port_b = bytes[2] | (~bytes[3] & 0xff)
+            out.int("half_track", half_track).int("slip", SLIP)
+            out.int("zone", (port_b >> 5) & 0x03)
+            out.bool("motor", port_b.anybits?(MOTOR)).bool("led", port_b.anybits?(LED))
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/pet_drive8050.rb

@@ -0,0 +1,216 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module PET
+        # A true 8050 or 8250 on device 8, as xpet 3.10, xcbm2 and xcbm5x0 save it with true
+        # drive emulation: DRIVE8 2.0 with both drives, DRIVE9 to DRIVE11
+        # with none, DRIVECPU0 1.3, the interface processor and its RAM,
+        # RIOT1D0 and RIOT2D0 0.0, its two 6532s, and FDC0 0.0. xpet runs
+        # the floppy controller at a high level, so its 6504, VIA and 6530
+        # aren't in the snapshot: FDC0 holds the controller's state, its
+        # last track in byte 6.
+        #
+        # DRIVE8 holds a block of 139 bytes for each drive, then 6 for the
+        # unit: each block has its head's half track, twice the track, at
+        # $10 and the drive's type as a word at $28 (8050 or 8250).
+        # DRIVECPU0 is laid out as the 2031's (Drive2031), its RAM the IP's
+        # page 0, the 6532s' 128 bytes each, then the 4K of common RAM.
+        # A RIOT module holds port A's output and direction registers, port
+        # B's, the edge control (bit 0 the PA7 interrupt, bit 1 a rising
+        # edge), the flags (bit 7 the timer's interrupt, which xpet raises
+        # IRQ for, bit 6 PA7's), the timer's
+        # counter, its divider as a word, two bytes xpet leaves 0, and
+        # whether the timer interrupts.
+        #
+        # Written, once the controller is in its idle loop between
+        # instructions (PET#settle_for_vice!): the IP's registers and RAM,
+        # the 6532s, the heads' tracks, and FDC0 as xpet leaves an idle
+        # controller with the track badline's controller last stepped to.
+        # A unit whose controller is still busy is left out of xpet's
+        # modules. Read: the IP's registers and RAM and the 6532s, with the
+        # controller as a unit switched on has it in its idle loop, its
+        # heads on track 1, from where its next job steps them. A job under
+        # way in xpet's controller starts again from there. The disks in
+        # the drives stay.
+        module Drive8050
+          UNIT = "DRIVE8"
+          CPU = Drive2031::CPU
+          RIOTS = %w[RIOT1D0 RIOT2D0].freeze
+          FDC = "FDC0"
+          NAMES = [UNIT, CPU, *RIOTS, FDC].freeze
+          TYPES = { 0x1f72 => "8050", 0x203a => "8250" }.freeze
+          # Where each drive's block starts in DRIVE8, and its fields.
+          DRIVES = [0x00, 0x8b].freeze
+          HALF_TRACK = 0x10
+          TYPE = 0x28
+          SIZE = 284
+          # DRIVE8 as xpet saves an idle 8050, by the bytes that aren't 0,
+          # but for the type.
+          IDLE = { 0x00 => 0x01, 0x01 => 0x02, 0x02 => 0x01, 0x0e => 0x01, 0x0f => 0x01, 0x10 => 0x4c, 0x1a => 0x01,
+                   0x20 => 0x55, 0x30 => 0x06, 0x6f => 0xcd, 0x70 => 0xab, 0x71 => 0x34, 0x72 => 0x12, 0x99 => 0x01,
+                   0x9a => 0x01, 0x9b => 0x24, 0xa5 => 0x01, 0xab => 0x55, 0x11a => 0x01 }.freeze
+          ZERO_PAGE = 0x80
+          COMMON = 0x1000
+          # FDC0 as xpet leaves an idle controller, and where the track goes.
+          FDC_IDLE = [0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00].freeze
+          FDC_TRACK = 6
+          # Where badline's controller keeps drive 0's track, in the 6530's
+          # RAM.
+          TRACK_AT = 0x21
+          DIVIDERS = [1, 8, 64, 1024].freeze
+          IRQ_EDGE = 0x01
+          RISING = 0x02
+          TIMER_FLAG = 0x80
+          PA7_FLAG = 0x40
+
+          module_function
+
+          # Whether the snapshot has a true 8050 or 8250.
+          def present?(container) = !container[FDC].nil? && !container[CPU].nil?
+
+          def reads?(section)
+            case section.name
+            when CPU then Drive2031.reads?(section)
+            when UNIT then section.major == Drive2031::DRIVE_MAJOR && section.minor == Drive2031::DRIVE_MINOR
+            else section.major.zero? && section.minor.zero?
+            end
+          end
+
+          # The model DRIVE8 names, or nil.
+          def model(container)
+            unit = container[UNIT]
+            return nil if unit.nil? || unit.data.bytesize < SIZE
+
+            TYPES[FieldReader.new(unit).skip(TYPE).word]
+          end
+
+          # xpet's modules for the 8050 or 8250 whose BL-D8 modules `readers`
+          # holds, and none without one, or with its controller away from
+          # its idle loop.
+          def export(machine, readers)
+            drive = readers["BL-D8"]
+            model = drive&.text("model", "")
+            return [] unless TYPES.value?(model) && idle?(readers)
+
+            [unit(model, readers.fetch("BL-D8-MECH")), *Drive2031::UNITS.drop(1).map { |name| none(name) },
+             Drive2031.cpu_section(machine, readers.fetch("BL-D8-IPCPU"), ram(readers)),
+             riot(RIOTS[0], readers.fetch("BL-D8-RIOT1")), riot(RIOTS[1], readers.fetch("BL-D8-RIOT2")),
+             fdc(readers.fetch("BL-D8-RRIOT"))]
+          end
+
+          # Whether both processors are between instructions, the
+          # controller at the start of its idle loop.
+          def idle?(readers)
+            fdc = readers.fetch("BL-D8-FDCCPU")
+            !position?(fdc) && !position?(readers.fetch("BL-D8-IPCPU")) &&
+              fdc.int("pc", 0) == Drives::Model8050::Idle::FDC_LOOP
+          end
+
+          def position?(cpu) = !cpu.text("pos.seq", "").empty?
+
+          def unit(model, mechanism)
+            bytes = Array.new(SIZE) { |offset| IDLE.fetch(offset, 0) }
+            cylinders = mechanism.ints("cylinders", [0, 0])
+            DRIVES.each_with_index do |at, drive|
+              bytes[at + HALF_TRACK] = ((cylinders[drive] || 0) + 1) * 2
+              bytes[at + TYPE, 2] = [TYPES.key(model)].pack("v").bytes
+            end
+            FieldWriter.new.bytes(bytes).section(UNIT, Drive2031::DRIVE_MAJOR, Drive2031::DRIVE_MINOR)
+          end
+
+          def none(name) = Drive2031.unit(Drive2031::NONE, name)
+
+          # The IP's RAM as xpet lays it out: page 0 from both 6532s, then
+          # the common RAM.
+          def ram(readers)
+            [readers.fetch("BL-D8-RIOT1"), readers.fetch("BL-D8-RIOT2")].flat_map do |riot|
+              filled(riot.bytes("ram", "".b).bytes, ZERO_PAGE)
+            end + filled(readers.fetch("BL-D8-COMMON").bytes("ram", "".b).bytes, COMMON)
+          end
+
+          def filled(bytes, length) = Array.new(length) { |index| bytes[index] || 0 }
+
+          def riot(name, input)
+            edge = input.bool("edge_irq_enabled", false) ? IRQ_EDGE : 0
+            edge |= RISING if input.bool("rising_edge", false)
+            timer = input.bool("timer.flag", false) && input.bool("timer.irq_enabled", false)
+            flags = (timer ? TIMER_FLAG : 0) | (input.bool("pa7_flag", false) ? PA7_FLAG : 0)
+            divider = DIVIDERS.fetch(input.int("timer.interval", 0) & 0x03)
+            fields = FieldWriter.new.byte(input.int("ora", 0)).byte(input.int("ddra", 0)).byte(input.int("orb", 0))
+            fields.byte(input.int("ddrb", 0)).byte(edge).byte(flags).byte(input.int("timer.counter", 0)).word(divider)
+            fields.zeros(2).flag(input.bool("timer.irq_enabled", false)).section(name, 0, 0)
+          end
+
+          def fdc(rriot)
+            bytes = FDC_IDLE.dup
+            bytes[FDC_TRACK] = rriot.bytes("ram", "".b).getbyte(TRACK_AT).to_i
+            FieldWriter.new.bytes(bytes).section(FDC, 0, 0)
+          end
+
+          # The unit's keyed modules, named for device 8, from the
+          # snapshot's: the IP's side from xpet's, the controller's side
+          # from `reference`, a unit's in its idle loop, and `disks`, the
+          # drives' disk modules badline keeps.
+          def import(container, reference, disks)
+            cpu = container[CPU]
+            page = FieldReader.new(cpu).skip(Drive2031::RAM_AT).string(ZERO_PAGE * 2)
+            common = FieldReader.new(cpu).skip(Drive2031::RAM_AT + (ZERO_PAGE * 2)).string(COMMON)
+            sections = [Keyed.section("BL-D8") { |out| unit_fields(container, reference, out) },
+                        Keyed.section("BL-D8-COMMON") { |out| out.bytes("ram", common) },
+                        riot_section("BL-D8-RIOT1", container[RIOTS[0]], page.byteslice(0, ZERO_PAGE)),
+                        riot_section("BL-D8-RIOT2", container[RIOTS[1]], page.byteslice(ZERO_PAGE, ZERO_PAGE)),
+                        Keyed.section("BL-D8-IPCPU") { |out| Drive2031.registers(cpu, out) }]
+            sections + reference.select { |section| CONTROLLER.include?(section.name) } + disks
+          end
+
+          # The controller's side, which comes from a unit in its idle loop.
+          CONTROLLER = %w[BL-D8-FDCCPU BL-D8-VIA BL-D8-RRIOT BL-D8-MECH].freeze
+
+          def unit_fields(container, reference, out)
+            own = Keyed::Reader.parse(reference.find { |section| section.name == "BL-D8" })
+            out.text("model", own.text("model", "8050")).int("phase", 0)
+            out.int("cycles", FieldReader.new(container[CPU]).qword).int("fdc_data", own.int("fdc_data", 0))
+          end
+
+          def riot_section(name, section, ram)
+            fields = FieldReader.new(section)
+            ora, ddra, orb, ddrb, edge, flags, counter = fields.bytes(7)
+            divider = fields.word
+            fields.skip(2)
+            irq = fields.flag?
+            Keyed.section(name) do |out|
+              out.bytes("ram", ram).int("ora", ora).int("ddra", ddra).int("orb", orb).int("ddrb", ddrb)
+              out.bool("edge_irq_enabled", edge.anybits?(IRQ_EDGE)).bool("rising_edge", edge.anybits?(RISING))
+              out.bool("pa7_flag", flags.anybits?(PA7_FLAG)).int("timer.counter", counter)
+              out.int("timer.interval", DIVIDERS.index(divider) || 0).int("timer.prescale", [divider, 1].max)
+              out.bool("timer.flag", flags.anybits?(TIMER_FLAG)).bool("timer.expired", flags.anybits?(TIMER_FLAG))
+              out.bool("timer.irq_enabled", irq)
+            end
+          end
+
+          # A unit of `model` switched on and run into its controller's idle
+          # loop, both processors between instructions, as keyed modules
+          # named for device 8, run once a model.
+          def reference(model)
+            @references ||= {}
+            @references[model] ||= booted(model)
+          end
+
+          def booted(model)
+            unit = model == "8250" ? Drives::Model8250.new : Drives::Model8050.new
+            Drives::Model8050::BOOT_CYCLES.times { unit.host_cycle! }
+            unit.cycle! until idle_loop?(unit)
+            unit.save_modules([], "BL-D8")
+          end
+
+          def idle_loop?(unit)
+            cpu = unit.fdc_cpu
+            unit.ip_cpu.boundary? && cpu.boundary? && cpu.program_counter == Drives::Model8050::Idle::FDC_LOOP
+          end
+        end
+      end
+    end
+  end
+end