badline 0.16.1 → 0.17.0

data/lib/badline/chips/riot/fast_forward.rb

@@ -0,0 +1,72 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class RIOT
+      class Timer
+        # Running the timer a stretch of cycles at once, as cycle! would one
+        # by one, for a drive sleeping through its idle loops.
+        module FastForward
+          # quiet_cycles for a timer whose flag can't pull IRQ.
+          QUIET = 1 << 40
+
+          # How many cycles the timer can run without pulling IRQ: until the
+          # count that sets its flag, and forever with its interrupt off.
+          def quiet_cycles
+            return QUIET unless @irq_enabled
+
+            cycles_to_flag - 1
+          end
+
+          # Runs +cycles+ cycles at once.
+          def fast_forward(cycles)
+            return if cycles.zero?
+            return count_expired(cycles) if @expired
+
+            to_flag = cycles_to_flag
+            if cycles < to_flag
+              count_down(cycles)
+            else
+              @counter = 0xff
+              @prescale = @divider
+              @expired = @flag = @fired = true
+              count_expired(cycles - to_flag) if cycles > to_flag
+            end
+          end
+
+          # What the counter and the flag don't hold, for comparing the
+          # timer at two points.
+          def state = [@divider, @expired, @irq_enabled]
+
+          private
+
+          # The cycles until the count that sets the flag: the count through
+          # 0 at the interval, or the next once expired.
+          def cycles_to_flag = @expired ? @counter + 1 : @prescale + (@counter * @divider)
+
+          # Counts at the interval, short of 0.
+          def count_down(cycles)
+            @fired = false
+            if cycles < @prescale
+              @prescale -= cycles
+            else
+              rest = cycles - @prescale
+              @counter -= 1 + (rest / @divider)
+              @prescale = @divider - (rest % @divider)
+            end
+          end
+
+          # Counts every cycle, setting the flag at each pass through 0.
+          def count_expired(cycles)
+            to_wrap = @counter + 1
+            @counter = (@counter - cycles) & 0xff
+            @fired = cycles >= to_wrap && ((cycles - to_wrap) % 256).zero?
+            @flag = true if cycles >= to_wrap
+          end
+        end
+
+        include FastForward
+      end
+    end
+  end
+end

data/lib/badline/chips/riot/keyed_parts.rb

@@ -0,0 +1,69 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class RIOT
+      class Timer
+        # The timer's fields in a keyed snapshot module, under `prefix`, the
+        # divider by its A1-A0 code.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}counter", @counter).int("#{prefix}interval", DIVIDERS.index(@divider))
+            out.int("#{prefix}prescale", @prescale)
+            out.bool("#{prefix}expired", @expired).bool("#{prefix}flag", @flag)
+            out.bool("#{prefix}irq_enabled", @irq_enabled).bool("#{prefix}fired", @fired)
+          end
+
+          def load_fields(input, prefix)
+            @counter = input.byte("#{prefix}counter", @counter)
+            @divider = DIVIDERS[input.masked("#{prefix}interval", DIVIDERS.index(@divider), 0x03)]
+            @prescale = input.int("#{prefix}prescale", @prescale).clamp(1, @divider)
+            @expired = input.bool("#{prefix}expired", @expired)
+            @flag = input.bool("#{prefix}flag", @flag)
+            @irq_enabled = input.bool("#{prefix}irq_enabled", @irq_enabled)
+            @fired = input.bool("#{prefix}fired", @fired)
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The RIOT's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # RAM, the port and direction registers, the edge detector and the
+      # level on PA7, and the timer under timer. The peripheral restores its
+      # own state.
+      module KeyedState
+        def save_fields(out)
+          out.bytes("ram", @ram)
+          out.int("ora", @ora).int("orb", @orb).int("ddra", @ddra).int("ddrb", @ddrb)
+          out.bool("pa7_high", @pa7_high).bool("pa7_active", @pa7_active).bool("pa7_flag", @pa7_flag)
+          out.bool("edge_irq_enabled", @edge_irq_enabled).bool("rising_edge", @rising_edge)
+          @timer.save_fields(out, "timer.")
+          out
+        end
+
+        def load_fields(input)
+          input.bytes_into("ram", @ram)
+          @ora = input.byte("ora", @ora)
+          @orb = input.byte("orb", @orb)
+          @ddra = input.byte("ddra", @ddra)
+          @ddrb = input.byte("ddrb", @ddrb)
+          load_edge_fields(input)
+          @timer.load_fields(input, "timer.")
+        end
+
+        private
+
+        def load_edge_fields(input)
+          @pa7_high = input.bool("pa7_high", @pa7_high)
+          @pa7_active = input.bool("pa7_active", @pa7_active)
+          @pa7_flag = input.bool("pa7_flag", @pa7_flag)
+          @edge_irq_enabled = input.bool("edge_irq_enabled", @edge_irq_enabled)
+          @rising_edge = input.bool("rising_edge", @rising_edge)
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/riot/timer.rb

@@ -0,0 +1,80 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class RIOT
+      # The interval timer of the 6532 and the 6530: an 8-bit counter behind
+      # a prescaler that divides φ2 by 1, 8, 64 or 1024, and the timer's
+      # interrupt flag.
+      #
+      # A write loads the counter and counts it once on the write's own
+      # cycle, so the counter reads one less than written from the cycle
+      # after, and counts again every interval from the write. A write of N
+      # reads N - 1 until cycle T, 0 until cycle N x T, and $FF with the flag
+      # set on cycle N x T: 52 at ÷8 sets the flag on cycle 416. From there
+      # the counter counts every cycle, so it tells how long ago the flag
+      # set, and each count through 0 sets the flag again. Only a write puts
+      # the prescaler back.
+      #
+      # Reading or writing the counter clears the flag, except for a read on
+      # the cycle that sets it. Each access takes A3 as the interrupt enable.
+      class Timer
+        DIVIDERS = [1, 8, 64, 1024].freeze
+
+        attr_reader :counter, :flag
+        attr_accessor :irq_enabled
+
+        def initialize
+          @counter = 0
+          @divider = 1
+          @prescale = 1
+          @expired = true
+          @flag = false
+          @irq_enabled = false
+          @fired = false
+        end
+
+        def irq? = @flag && @irq_enabled
+
+        # +interval+ is A1-A0, picking ÷1, ÷8, ÷64 or ÷1024.
+        def write(value, interval, irq_enabled)
+          @irq_enabled = irq_enabled
+          @flag = false
+          @divider = DIVIDERS[interval]
+          @prescale = @divider
+          @expired = false
+          @counter = value
+          count
+        end
+
+        def read(irq_enabled)
+          @irq_enabled = irq_enabled
+          @flag = false unless @fired
+          @counter
+        end
+
+        def cycle!
+          @fired = false
+          unless @expired
+            @prescale -= 1
+            return unless @prescale.zero?
+
+            @prescale = @divider
+          end
+          count
+        end
+
+        private
+
+        def count
+          @counter = (@counter - 1) & 0xff
+          return unless @counter == 0xff
+
+          @expired = true
+          @flag = true
+          @fired = true
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/riot.rb

@@ -0,0 +1,162 @@
+# frozen_string_literal: true
+
+require "badline/chips/riot/timer"
+require "badline/chips/riot/fast_forward"
+require "badline/chips/riot/keyed_parts"
+
+module Badline
+  module Chips
+    # The MOS 6532 RIOT (RAM, I/O, Timer): 128 bytes of RAM, two 8-bit
+    # ports, A and B, each with a direction register, a 1 making the pin an
+    # output, the interval timer (Timer) and an edge detector on PA7. The
+    # 8050 and 8250's interface processor has two.
+    #
+    # The RS pin picks the RAM (read_ram and write_ram, A6-A0) or the
+    # registers (peek and poke, A4-A0). With A2 low, A1-A0 pick port A, DDRA,
+    # port B and DDRB. With A2 high, a read with A0 low reads the timer and
+    # one with A0 high the interrupt flags. A write with A4 high loads the
+    # timer, A1-A0 picking the divider, and one with A4 low sets the edge
+    # detector, A1 the interrupt enable and A0 the active edge, rising when
+    # set; its data is ignored. A3 is the timer's interrupt enable on every
+    # timer access.
+    #
+    # Port A reads its pins, whatever drives them. Port B reads its output
+    # bits from its output register and its input bits from the pins. An
+    # input pin floats high, and a peripheral pulls lines low through read_a
+    # and read_b, as a VIA's does. PA7 takes its level from outside through
+    # pa7= as well, for the edge detector.
+    #
+    # The edge detector watches the level on PA7, input or output. Its
+    # active edge sets the PA7 flag whether or not its interrupt is enabled,
+    # and so can a change of the active edge. A read of the flags clears it.
+    class RIOT
+      attr_reader :peripheral, :timer, :ram
+
+      def initialize(peripheral: nil)
+        @peripheral = peripheral
+        @ram = Array.new(128, 0)
+        @timer = Timer.new
+        @pa7_high = true
+        @pa7_active = false
+        @pa7_flag = false
+        reset!
+      end
+
+      # The RES line clears the four I/O registers, which leaves every line
+      # an input, disables both interrupts and sets the active edge to
+      # falling. The timer counts on, and the flags stay as they are.
+      def reset!
+        @ora = @orb = @ddra = @ddrb = 0x00
+        @timer.irq_enabled = false
+        @edge_irq_enabled = false
+        @rising_edge = false
+        sense_pa7
+      end
+
+      def irq? = @timer.irq? || (@pa7_flag && @edge_irq_enabled)
+
+      def cycle!
+        @timer.cycle!
+      end
+
+      # Port A as driven by ORA and DDRA, input lines floating high.
+      def port_a_output = driven_lines(@ora, @ddra)
+
+      def port_b_output = driven_lines(@orb, @ddrb)
+
+      # The level something outside drives on PA7.
+      def pa7=(high)
+        @pa7_high = high
+        sense_pa7
+      end
+
+      # How many cycles the RIOT can run with no counter pulling IRQ.
+      def quiet_cycles = @timer.quiet_cycles
+
+      # Runs +cycles+ cycles at once, which moves only the timer.
+      def fast_forward(cycles)
+        @timer.fast_forward(cycles)
+      end
+
+      # Everything the RIOT holds but its timer's counter, for comparing it
+      # at two points.
+      def idle_state
+        [*@ram, @ora, @orb, @ddra, @ddrb, @pa7_high, @pa7_active, @pa7_flag, @edge_irq_enabled, @rising_edge,
+         *@timer.state, @timer.flag]
+      end
+
+      def read_ram(addr) = @ram[addr & 0x7f]
+
+      def write_ram(addr, value)
+        @ram[addr & 0x7f] = value
+      end
+
+      def peek(addr)
+        return read_timer(addr) if addr.anybits?(0x04)
+
+        case addr & 0x03
+        when 0x00 then pins_a
+        when 0x01 then @ddra
+        when 0x02 then read_port_b
+        else @ddrb
+        end
+      end
+
+      def poke(addr, value)
+        return write_timer(addr, value) if addr.anybits?(0x04)
+
+        case addr & 0x03
+        when 0x00 then @ora = value
+        when 0x01 then @ddra = value
+        when 0x02 then @orb = value
+        else @ddrb = value
+        end
+        sense_pa7
+      end
+
+      private
+
+      def driven_lines(register, direction)
+        (register & direction) | (~direction & 0xff)
+      end
+
+      def pins_a
+        lines = @pa7_high ? port_a_output : port_a_output & 0x7f
+        @peripheral ? lines & @peripheral.read_a(lines) : lines
+      end
+
+      def read_port_b
+        lines = port_b_output
+        lines &= @peripheral.read_b(lines) if @peripheral
+        (@orb & @ddrb) | (lines & ~@ddrb & 0xff)
+      end
+
+      # Bit 7 the timer flag, bit 6 the PA7 flag, which the read clears.
+      def read_timer(addr)
+        return @timer.read(addr.anybits?(0x08)) if addr.nobits?(0x01)
+
+        value = (@timer.flag ? 0x80 : 0x00) | (@pa7_flag ? 0x40 : 0x00)
+        @pa7_flag = false
+        value
+      end
+
+      def write_timer(addr, value)
+        if addr.anybits?(0x10)
+          @timer.write(value, addr & 0x03, addr.anybits?(0x08))
+        else
+          @edge_irq_enabled = addr.anybits?(0x02)
+          @rising_edge = addr.anybits?(0x01)
+          sense_pa7
+        end
+      end
+
+      # The detector is active while PA7 sits at the level its active edge
+      # leads to, and becoming active sets the flag.
+      def sense_pa7
+        active = (@pa7_high && port_a_output.anybits?(0x80)) == @rising_edge
+        @pa7_flag = true if active && !@pa7_active
+        @pa7_active = active
+      end
+    end
+  end
+end

data/lib/badline/chips/rriot/keyed_state.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class RRIOT
+      # The RRIOT's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # RAM, the port and direction registers, and the timer under timer.
+      # The ROM is the mask's, and the peripheral restores its own state.
+      module KeyedState
+        def save_fields(out)
+          out.bytes("ram", @ram)
+          out.int("ora", @ora).int("orb", @orb).int("ddra", @ddra).int("ddrb", @ddrb)
+          @timer.save_fields(out, "timer.")
+          out
+        end
+
+        def load_fields(input)
+          input.bytes_into("ram", @ram)
+          @ora = input.byte("ora", @ora)
+          @orb = input.byte("orb", @orb)
+          @ddra = input.byte("ddra", @ddra)
+          @ddrb = input.byte("ddrb", @ddrb)
+          @timer.load_fields(input, "timer.")
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/rriot.rb

@@ -0,0 +1,132 @@
+# frozen_string_literal: true
+
+require "badline/chips/riot"
+require "badline/chips/rriot/keyed_state"
+
+module Badline
+  module Chips
+    # The MOS 6530 RRIOT (ROM, RAM, I/O, Timer): 1 KB of mask ROM, 64 bytes
+    # of RAM, two 8-bit ports, A and B, each with a direction register, a 1
+    # making the pin an output, and the 6532's interval timer (RIOT::Timer).
+    # It has no edge detector. The 8050 and 8250's floppy controller has
+    # one, its ROM the controller's program.
+    #
+    # Which addresses select the ROM, the RAM and the registers is part of
+    # the mask, so the board decodes them and calls read_rom (A9-A0),
+    # read_ram and write_ram (A5-A0), or peek and poke (A3-A0). With A2 low,
+    # A1-A0 pick port A, DDRA, port B and DDRB. With A2 high, a write loads
+    # the timer, A1-A0 picking the divider, and a read with A0 low reads the
+    # timer and one with A0 high the interrupt flag in bit 7, the other bits
+    # 0. A3 is the timer's interrupt enable on every timer access.
+    #
+    # Both ports read their output bits from the output register and their
+    # input bits from the pins. An input pin floats high, and a peripheral
+    # pulls lines low through read_a and read_b, as a VIA's does.
+    #
+    # The timer's interrupt comes out on PB7, which the mask can give to it:
+    # PB7 then reads low while the flag is up with its interrupt enabled,
+    # and the board takes IRQ from irq?. PB5 and PB6 can be chip selects
+    # instead of port lines, which the board decodes.
+    class RRIOT
+      attr_reader :peripheral, :timer, :ram, :rom
+
+      # +rom+ is the 1024 bytes of the mask ROM.
+      def initialize(rom:, peripheral: nil, irq_on_pb7: true)
+        @rom = rom
+        @peripheral = peripheral
+        @irq_on_pb7 = irq_on_pb7
+        @ram = Array.new(64, 0)
+        @timer = RIOT::Timer.new
+        reset!
+      end
+
+      # The RES line clears the four I/O registers, which leaves every line
+      # an input, and disables the interrupt. The timer counts on.
+      def reset!
+        @ora = @orb = @ddra = @ddrb = 0x00
+        @timer.irq_enabled = false
+      end
+
+      def irq? = @irq_on_pb7 && @timer.irq?
+
+      def cycle!
+        @timer.cycle!
+      end
+
+      # Port A as driven by ORA and DDRA, input lines floating high.
+      def port_a_output = driven_lines(@ora, @ddra)
+
+      # Port B as driven by ORB and DDRB, PB7 pulled low by the interrupt.
+      def port_b_output
+        lines = driven_lines(@orb, @ddrb)
+        irq? ? lines & 0x7f : lines
+      end
+
+      # How many cycles the RRIOT can run with no counter pulling IRQ.
+      def quiet_cycles = @timer.quiet_cycles
+
+      # Runs +cycles+ cycles at once, which moves only the timer.
+      def fast_forward(cycles)
+        @timer.fast_forward(cycles)
+      end
+
+      # Everything the RRIOT holds but its timer's counter, for comparing
+      # it at two points.
+      def idle_state = [*@ram, @ora, @orb, @ddra, @ddrb, *@timer.state, @timer.flag]
+
+      def read_rom(addr) = @rom[addr & 0x3ff]
+
+      def read_ram(addr) = @ram[addr & 0x3f]
+
+      def write_ram(addr, value)
+        @ram[addr & 0x3f] = value
+      end
+
+      def peek(addr)
+        return read_timer(addr) if addr.anybits?(0x04)
+
+        case addr & 0x03
+        when 0x00 then read_port_a
+        when 0x01 then @ddra
+        when 0x02 then read_port_b
+        else @ddrb
+        end
+      end
+
+      def poke(addr, value)
+        return @timer.write(value, addr & 0x03, addr.anybits?(0x08)) if addr.anybits?(0x04)
+
+        case addr & 0x03
+        when 0x00 then @ora = value
+        when 0x01 then @ddra = value
+        when 0x02 then @orb = value
+        else @ddrb = value
+        end
+      end
+
+      private
+
+      def driven_lines(register, direction)
+        (register & direction) | (~direction & 0xff)
+      end
+
+      def read_port_a
+        lines = port_a_output
+        lines &= @peripheral.read_a(lines) if @peripheral
+        (@ora & @ddra) | (lines & ~@ddra & 0xff)
+      end
+
+      def read_port_b
+        lines = port_b_output
+        lines &= @peripheral.read_b(lines) if @peripheral
+        (@orb & @ddrb) | (lines & ~@ddrb & 0xff)
+      end
+
+      def read_timer(addr)
+        return @timer.read(addr.anybits?(0x08)) if addr.nobits?(0x01)
+
+        @timer.flag ? 0x80 : 0x00
+      end
+    end
+  end
+end

data/lib/badline/chips/tpi/keyed_state.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class TPI
+      # The registers, the interrupt latches and AIR, the priority
+      # stack, CA and CB, and the levels on the interrupt inputs, in a
+      # keyed snapshot module (BL-TPI1 and BL-TPI2).
+      module KeyedState
+        def save_fields(out)
+          out.ints("ports", [@pra, @prb, @prc]).ints("directions", [@ddra, @ddrb, @ddrc])
+          out.int("control", @control).int("latches", @latches).int("air", @air)
+          out.ints("stack", @stack).bool("ca", @ca).bool("cb", @cb).int("lines", @lines)
+        end
+
+        def load_fields(input)
+          ports = input.ints_into("ports", [@pra, @prb, @prc])
+          @pra = ports[0] & 0xff
+          @prb = ports[1] & 0xff
+          @prc = ports[2] & 0xff
+          directions = input.ints_into("directions", [@ddra, @ddrb, @ddrc])
+          @ddra = directions[0] & 0xff
+          @ddrb = directions[1] & 0xff
+          @ddrc = directions[2] & 0xff
+          @control = input.byte("control", @control)
+          @latches = input.masked("latches", @latches, 0x1f)
+          @air = input.masked("air", @air, 0x1f)
+          @stack.replace(input.ints("stack", []).last(STACK_DEPTH).map { |value| value & 0x1f })
+          @ca = input.bool("ca", @ca)
+          @cb = input.bool("cb", @cb)
+          @lines = input.masked("lines", @lines, 0x1f)
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end