badline 0.16.1 → 0.17.0

data/lib/badline/chips/tpi.rb

@@ -0,0 +1,233 @@
+# frozen_string_literal: true
+
+require "badline/chips/tpi/keyed_state"
+
+module Badline
+  module Chips
+    # The MOS 6525 TPI (tri-port interface): three 8-bit ports, A, B and C,
+    # each with a direction register, a 1 making the pin an output. Its
+    # three address lines repeat the eight registers every 8 bytes:
+    #
+    # 0 - PRA
+    # 1 - PRB
+    # 2 - PRC, or in mode 1 the interrupt latches (bits 0-4) and the levels
+    #     of IRQ, CA and CB (bits 5-7)
+    # 3 - DDRA
+    # 4 - DDRB
+    # 5 - DDRC, which in mode 1 is the interrupt mask, its bits 0-4 enabling
+    #     I0-I4 with a 1, and reads back all eight bits written
+    # 6 - CR: bit 0 MC, the mode, bit 1 IP, the priority, bits 2-3 IE3 and
+    #     IE4, the active edges of I3 and I4 (1 rising), bits 4-5 CA's mode
+    #     and bits 6-7 CB's
+    # 7 - AIR, the active interrupt register, in mode 1
+    #
+    # A port reads its pins: an output's level, and what the peripheral
+    # lets through of an input, which floats high (read_a, read_b and
+    # read_c pull lines low, as a VIA's peripheral does).
+    #
+    # In mode 1 PC0-PC4 are the interrupt inputs I0-I4 (#interrupt_line).
+    # A falling edge on I0-I2, or the edge IE3 and IE4 pick on I3 and I4,
+    # sets the input's latch whether or not its mask bit is set. A write of
+    # 0 to a latch's bit of PRC clears it, and a 1 does nothing. PC5 is
+    # the IRQ output, open drain, low (#irq?) while the AIR holds a bit;
+    # PC6 is CA and PC7 CB (#ca?, #cb?).
+    #
+    # Without priority (IP 0), the AIR holds every unmasked latch that is
+    # set, and a read of it clears them and it. With priority (IP 1) the
+    # inputs rank I4 > I3 > I2 > I1 > I0, and the AIR holds the one highest
+    # unmasked latch that outranks the interrupt in service, the top of a
+    # five-level stack. A read of the AIR pushes it on the stack, clears it
+    # and its latch, and lets IRQ go; a write pops the stack, letting lower
+    # interrupts through again.
+    #
+    # CA: 00 set high by I3's active edge and low by a read of PRA, 01
+    # pulsed low by a read of PRA, 10 low, 11 high. CB: 00 set low by a
+    # write of PRB and high by I4's active edge, 01 pulsed low by a write of
+    # PRB, 10 low, 11 high. A pulse is shorter than a cycle, so CA and CB
+    # read high in mode 01.
+    #
+    # The rules are the MPS 6525 datasheet's (Commodore Semiconductor
+    # Group), pages 2-81 to 2-83.
+    class TPI
+      STACK_DEPTH = 5
+
+      attr_reader :peripheral, :latches, :control, :stack
+
+      def initialize(peripheral: nil)
+        @peripheral = peripheral
+        @lines = 0x1f
+        @stack = []
+        reset!
+      end
+
+      # The RES pin clears every register: mode 0, and every pin an input.
+      def reset!
+        @pra = @prb = @prc = 0
+        @ddra = @ddrb = @ddrc = 0
+        @control = 0
+        @latches = 0
+        @air = 0
+        @stack.clear
+        @ca = @cb = false
+      end
+
+      # The interrupt mask in mode 1: DDRC's bits 0-4.
+      def mask = @ddrc & 0x1f
+
+      # Whether IRQ is pulled low.
+      def irq? = @air != 0
+
+      # The levels of CA and CB in mode 1.
+      def ca? = @ca
+
+      def cb? = @cb
+
+      # The port lines as the chip drives them, inputs floating high.
+      def port_a_output = driven(@pra, @ddra)
+
+      def port_b_output = driven(@prb, @ddrb)
+
+      def port_c_output = mode1? ? pins_c_mode1 : driven(@prc, @ddrc)
+
+      # Something outside drives interrupt input +index+, I0 to I4, +high+
+      # or low. Its active edge sets its latch in mode 1.
+      def interrupt_line(index, high)
+        bit = 1 << index
+        was_high = @lines.anybits?(bit)
+        return if was_high == high
+
+        @lines = high ? @lines | bit : @lines & ~bit
+        return unless mode1? && high == rising_active?(index)
+
+        @latches |= bit
+        @ca = true if index == 3 && ca_mode.zero?
+        @cb = true if index == 4 && cb_mode.zero?
+        update_air
+      end
+
+      def peek(addr)
+        case addr & 0x07
+        when 0 then read_pra
+        when 1 then pins(@prb, @ddrb, @peripheral ? @peripheral.read_b(port_b_output) : 0xff)
+        when 2 then mode1? ? pins_c_mode1 : read_pins_c
+        when 3 then @ddra
+        when 4 then @ddrb
+        when 5 then @ddrc
+        when 6 then @control
+        else read_air
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x07
+        when 0 then @pra = value
+        when 1 then write_prb(value)
+        when 2 then write_prc(value)
+        when 3 then @ddra = value
+        when 4 then @ddrb = value
+        when 5 then write_ddrc(value)
+        when 6 then write_control(value)
+        else pop_air
+        end
+      end
+
+      private
+
+      def mode1? = @control.anybits?(0x01)
+
+      def priority? = @control.anybits?(0x02)
+
+      def ca_mode = (@control >> 4) & 0x03
+
+      def cb_mode = (@control >> 6) & 0x03
+
+      # I3 and I4 latch on the edge IE3 and IE4 pick, the others falling.
+      def rising_active?(index)
+        case index
+        when 3 then @control.anybits?(0x04)
+        when 4 then @control.anybits?(0x08)
+        else false
+        end
+      end
+
+      def driven(register, direction) = (register & direction) | (~direction & 0xff)
+
+      def pins(register, direction, inputs) = (register & direction) | (inputs & ~direction & 0xff)
+
+      def read_pra
+        @ca = false if mode1? && ca_mode.zero?
+        pins(@pra, @ddra, @peripheral ? @peripheral.read_a(port_a_output) : 0xff)
+      end
+
+      def read_pins_c
+        pins(@prc, @ddrc, @peripheral ? @peripheral.read_c(port_c_output) : 0xff)
+      end
+
+      # The latches, IRQ's level, CA's and CB's.
+      def pins_c_mode1
+        @latches | (irq? ? 0 : 0x20) | (@ca ? 0x40 : 0) | (@cb ? 0x80 : 0)
+      end
+
+      def write_prb(value)
+        @prb = value
+        @cb = false if mode1? && cb_mode.zero?
+      end
+
+      def write_prc(value)
+        return @prc = value unless mode1?
+
+        @latches &= value | 0xe0
+        update_air
+      end
+
+      def write_ddrc(value)
+        @ddrc = value
+        update_air
+      end
+
+      def write_control(value)
+        @control = value
+        @ca = ca_mode.anybits?(0x01) unless ca_mode.zero?
+        @cb = cb_mode.anybits?(0x01) unless cb_mode.zero?
+        update_air
+      end
+
+      def read_air
+        value = @air
+        return value unless mode1?
+
+        @latches &= ~value
+        @air = 0
+        if priority?
+          @stack.shift if @stack.length == STACK_DEPTH
+          @stack << value
+        end
+        update_air
+        value
+      end
+
+      def pop_air
+        return unless mode1?
+
+        @stack.pop
+        update_air
+      end
+
+      # The AIR's bits from the latches, the mask and, with priority, the
+      # interrupt in service.
+      def update_air
+        pending = mode1? ? @latches & mask : 0
+        return @air = pending unless priority?
+
+        highest = highest_bit(pending)
+        @air = highest > (@stack.last || 0) ? highest : 0
+      end
+
+      def highest_bit(bits)
+        bit = 0x10
+        bit >>= 1 while bit.positive? && bits.nobits?(bit)
+        bit
+      end
+    end
+  end
+end

data/lib/badline/chips/vic/bank.rb

@@ -10,6 +10,13 @@ module Badline
       # The machine's bus pushes in what the VIC sees through #connect,
       # #map_character_rom and #map whenever it changes. Until then the bank
       # has a CIA 2, RAM, colour RAM and character ROM of its own.
+      #
+      # The P500 wires the VIC another way (#map_video_bus): its phi1
+      # reads go to the character ROM while VICDOTSEL is high, and its phi2
+      # reads to the 1K static video matrix while STATVID is high, VA12
+      # high picking the matrix and VA12 low reading 0. Otherwise both go to
+      # the DRAM's 16K bank that VA14 and VA15 pick (#video_bus_lines). The
+      # colour nibbles come from the colour RAM in every phi2 read.
       class Bank
         include Addressable
 
@@ -30,6 +37,11 @@ module Badline
           map(Memory.new([], length: 2**16, start: 0))
           @lines = 0b11
           @swapped = false
+          @video_bus = false
+          @matrix = @ram
+          @statvid = false
+          @dotsel = false
+          @video_base = 0
         end
 
         # CIA 2, whose port A picks the bank, and the colour RAM, read from
@@ -57,9 +69,31 @@ module Badline
             @base = base
             @starts = BANK_STARTS.map { |start| base + start }.freeze
           end
-          @phi1_ultimax = phi1_ultimax
-          @ultimax = ultimax
           @romh = romh
+          @phi1_other = phi1_ultimax
+          @phi2_other = ultimax
+        end
+
+        # The P500's video bus: +dram+ is segment 0's 64K, +matrix+ the
+        # static video matrix, read from its start address on, and
+        # +color_ram+ the colour RAM, read from +color_base+ on. The
+        # character ROM is the one #map_character_rom gives, read from
+        # +base+ on.
+        def map_video_bus(dram, matrix, color_ram, color_base)
+          @ram = dram
+          @matrix = matrix
+          @color_ram = color_ram
+          @color_base = color_base
+          @video_bus = true
+          @phi1_other = true
+          @phi2_other = true
+        end
+
+        # STATVID, VICDOTSEL and VA14-VA15, as the P500's TPIs drive them.
+        def video_bus_lines(statvid, dotsel, bank)
+          @statvid = statvid
+          @dotsel = dotsel
+          @video_base = bank << 14
         end
 
         # On the 8565, a port A write that swaps the two bank lines, driving
@@ -74,7 +108,7 @@ module Badline
         end
 
         def peek(offset)
-          return ultimax_peek(offset) if @phi1_ultimax
+          return phi1_other(offset) if @phi1_other
 
           bits = bank_switch_register
           if (bits & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
@@ -88,7 +122,13 @@ module Badline
         # memory configuration the CPU does in that half. No cartridge drives
         # Ultimax mode in the first half alone, so otherwise it reads as #peek.
         def peek_phi2(offset)
-          @ultimax ? ultimax_peek(offset) : peek(offset)
+          @phi2_other ? phi2_other(offset) : peek(offset)
+        end
+
+        # A sprite's s-access in phi2: on the P500's video bus as the other
+        # phi2 reads, and otherwise as #peek.
+        def peek_sprite(offset)
+          @video_bus ? phi2_other(offset) : peek(offset)
         end
 
         def peek_color(offset)
@@ -101,7 +141,7 @@ module Badline
 
         # True if the VIC reads the character ROM at this offset.
         def character_rom?(offset)
-          !@phi1_ultimax && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
+          !@phi1_other && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
         end
 
         def start
@@ -110,6 +150,21 @@ module Badline
 
         private
 
+        def phi1_other(offset)
+          return ultimax_peek(offset) unless @video_bus
+          return @character_rom.peek(@character_base + (offset & 0x0fff)) if @dotsel
+
+          @ram.peek(@video_base + offset)
+        end
+
+        def phi2_other(offset)
+          return ultimax_peek(offset) unless @video_bus
+          return @ram.peek(@video_base + offset) unless @statvid
+          return 0 if offset.nobits?(0x1000)
+
+          @matrix.peek(@matrix.start + (offset & 0x03ff))
+        end
+
         # In Ultimax mode the cartridge ROMH replaces the character ROM
         # shadow, visible at $3000-$3FFF of the window. The MAX is in
         # Ultimax mode with no cartridge too.

data/lib/badline/chips/vic/sprite.rb

@@ -322,12 +322,13 @@ module Badline
         end
 
         # The three s-accesses step MC through the sprite's block, wrapping
-        # within it.
+        # within it. The first and third fall in phi2 and the second in
+        # phi1 (Bank#peek_sprite).
         def row_bits(counter)
           base = pointer * 64
-          (@bank.peek(base + counter) << 16) |
+          (@bank.peek_sprite(base + counter) << 16) |
             (@bank.peek(base + ((counter + 1) & MC_MASK)) << 8) |
-            @bank.peek(base + ((counter + 2) & MC_MASK))
+            @bank.peek_sprite(base + ((counter + 2) & MC_MASK))
         end
 
         def pointer = @bank.peek(@registers.screen_base + 0x3f8 + index)

data/lib/badline/drives/datasette/keyed_state.rb

@@ -10,7 +10,8 @@ module Badline
       # bytes and how far it has played. A tape that isn't in leaves tape.* out. A datasette that
       # times the read line's level adds when in the countdown the line
       # rises, and whether a recording's low half wave is on the tape. The
-      # sense and flag handlers don't fire on load.
+      # sense and flag handlers don't fire on load, and the running handler
+      # does when the load starts or stops the tape.
       module KeyedState
         def save_fields(out)
           out.bool("playing", @playing).bool("motor", @motor).int("countdown", @countdown)
@@ -33,6 +34,13 @@ module Badline
           @write_high = input.bool("write_high", @write_high)
           @rise_at = input.int("rise_at", @rise_at)
           @low_recorded = input.bool("low_recorded", @low_recorded)
+          load_tape(input)
+          update_running
+        end
+
+        private
+
+        def load_tape(input)
           bytes = input.bytes("tape.bytes", "".b).bytes
           return @tape = nil if bytes.empty?
 

data/lib/badline/drives/datasette.rb

@@ -14,7 +14,6 @@ module Badline
       # What inserting a tape raises on a machine without a cassette port.
       class Missing < ArgumentError; end
       attr_reader :tape
-      attr_writer :motor
 
       def initialize(tape = nil, level: false)
         @tape = tape
@@ -30,6 +29,8 @@ module Badline
         @low_recorded = false
         @flag_handler = nil
         @sense_handler = nil
+        @running_handler = nil
+        @running = false
       end
 
       # Falling edges on the tape read line.
@@ -42,6 +43,17 @@ module Badline
         @sense_handler = handler
       end
 
+      # Whether the tape runs (#running?), each time that changes, a
+      # snapshot's load included.
+      def on_running_change(&handler)
+        @running_handler = handler
+      end
+
+      def motor=(on)
+        @motor = on
+        update_running
+      end
+
       # Whether the machine has a datasette at its cassette port. The SX-64
       # has none: its keys stay up and it takes no tape.
       def connected? = @connected
@@ -56,11 +68,13 @@ module Badline
 
         @tape = tape
         rewind
+        update_running
       end
 
       def eject
         stop!
         @tape = nil
+        update_running
       end
 
       def rewind
@@ -117,7 +131,8 @@ module Badline
 
       def motor? = @motor
 
-      def running? = @playing && @motor && !@tape.nil?
+      # Whether the tape moves: a key down, the motor on and a tape in.
+      def running? = @running
 
       # The tape read line's level, on a datasette built with +level: true+.
       # Each pulse holds it low for its first half and high for its second,
@@ -131,7 +146,7 @@ module Badline
       end
 
       def cycle!
-        return unless running?
+        return unless @running
         return @since += 1 if @recording
 
         next_pulse if @countdown.zero?
@@ -175,9 +190,18 @@ module Badline
 
         finish_recording unless down
         @playing = down
+        update_running
         @sense_handler&.call
       end
 
+      def update_running
+        running = @playing && @motor && !@tape.nil?
+        return if running == @running
+
+        @running = running
+        @running_handler&.call
+      end
+
       # Releasing the keys ends a recording, and writes the tape out.
       def finish_recording
         return unless @recording

data/lib/badline/drives/model8050/disk.rb

@@ -0,0 +1,163 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # A .d80 or .d82 image as the floppy controller finds it on the disk:
+      # each track a ring of byte cells, each cell ten bit cells the GCR ROM
+      # turns into a data byte (Track::SYNC for a run of ones), so the
+      # mechanism needs no GCR. A track is laid out as the DOS's format code
+      # writes it ($C000-$C363 of DOS 2.7, run on the controller), sector
+      # after sector:
+      #
+      #   4 sync, $08, checksum, sector, track, ID 2, ID 1, $0F,
+      #   19 x $0F, 5 sync, $07, 256 data bytes, checksum, then $00
+      #
+      # the header checksum the EOR of the track, sector and IDs, and the
+      # data block's that of its bytes. The $00 gaps share out what the
+      # track has left over.
+      #
+      # Tracks come off the image as the head first reaches them. What the
+      # head writes goes back to the image when the motor stops (flush):
+      # every data block found on a written track whose header and checksum
+      # read cleanly.
+      class Disk
+        SYNC = 0x100
+
+        attr_reader :image
+
+        def initialize(image)
+          @image = image
+          @tracks = {}
+          @written = {}
+        end
+
+        def write_protected? = @image.read_only?
+
+        # The image's host file.
+        def path = @image.path
+
+        # How many tracks a side holds: 77.
+        def side_tracks = Storage::D80Image::SIDE_TRACKS
+
+        def sides = @image.is_a?(Storage::D82Image) ? 2 : 1
+
+        # The cells of +track+, 1 to 77 on the first side and 78 to 154 on
+        # the second, or nil past the disk's last.
+        def track(number)
+          return nil unless number.between?(1, side_tracks * sides)
+
+          @tracks[number] ||= build(number)
+        end
+
+        # The cells a track of the zone holds in one turn at 300 rpm: the
+        # 200,000 cycles of a turn over the zone's ten bit cells a byte at
+        # 6 MHz / (16 - zone).
+        def self.cells_in(zone) = 120_000 / (16 - zone)
+
+        # The zone a track is recorded in, 3 outermost to 0 innermost.
+        def self.zone_of(track)
+          cylinder = ((track - 1) % Storage::D80Image::SIDE_TRACKS) + 1
+          3 - Storage::D80Image::ZONE_LAST_TRACKS.count { |last| cylinder > last }
+        end
+
+        # The head wrote to +track+.
+        def written(number)
+          @written[number] = true
+        end
+
+        # Stores the blocks the head wrote in the image.
+        def flush
+          return if @written.empty?
+
+          blocks = []
+          @written.each_key { |number| blocks.concat(read_blocks(@tracks[number])) }
+          @written.clear
+          @image.store_blocks(blocks) unless blocks.empty?
+        end
+
+        private
+
+        def build(number)
+          id1, id2 = disk_id
+          cells = []
+          sectors = @image.sectors_in(number)
+          sectors.times do |sector|
+            data = @image.read_block(number, sector)
+            cells.push(SYNC, SYNC, SYNC, SYNC, 0x08, number ^ sector ^ id1 ^ id2, sector, number, id2, id1)
+            cells.concat(Array.new(20, 0x0f))
+            cells.push(SYNC, SYNC, SYNC, SYNC, SYNC, 0x07)
+            cells.concat(data)
+            cells << checksum(data)
+          end
+          pad(cells, sectors, self.class.cells_in(self.class.zone_of(number)))
+        end
+
+        # Shares the $00 gap out after each sector.
+        def pad(cells, sectors, length)
+          sector_length = cells.length / sectors
+          gap = (length - cells.length) / sectors
+          padded = []
+          sectors.times do |sector|
+            padded.concat(cells[sector * sector_length, sector_length])
+            padded.concat(Array.new(sector == sectors - 1 ? length - padded.length : gap, 0x00))
+          end
+          padded
+        end
+
+        def checksum(bytes)
+          sum = 0
+          bytes.each { |byte| sum ^= byte }
+          sum
+        end
+
+        # The ID the header block holds at $18.
+        def disk_id
+          header = @image.read_block(*@image.header_block)
+          [header[0x18], header[0x19]]
+        end
+
+        # Every block whose header and data read cleanly off +cells+, as
+        # [track, sector, data, nil].
+        def read_blocks(cells)
+          blocks = []
+          index = 0
+          length = cells.length
+          while (index = next_block(cells, index, 0x08))
+            header = Array.new(5) { |offset| cells[(index + offset) % length] }
+            index = next_block(cells, index, 0x07)
+            break unless index
+
+            block = data_block(cells, index, header)
+            blocks << block if block
+            break if index + 260 >= length
+          end
+          blocks
+        end
+
+        # The cell after the next sync run followed by +mark+, from
+        # +index+, or nil.
+        def next_block(cells, index, mark)
+          length = cells.length
+          while index < length
+            return index + 2 if cells[index] == SYNC && cells[(index + 1) % length] == mark
+
+            index += 1
+          end
+          nil
+        end
+
+        def data_block(cells, index, header)
+          checksum, sector, track, id2, id1 = header
+          return nil unless checksum == (track ^ sector ^ id1 ^ id2)
+
+          length = cells.length
+          data = Array.new(256) { |offset| cells[(index + offset) % length] }
+          return nil if data.include?(SYNC) || checksum(data) != cells[(index + 256) % length]
+
+          [track, sector, data, nil]
+        end
+      end
+    end
+  end
+end