badline 0.16.1 → 0.17.0

data/lib/badline/drives/model8050/mechanism.rb

@@ -0,0 +1,230 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The unit's two drives as the floppy controller sees them through
+      # the VIA and the 6530 (schematic 8050001, sheets 2 and 3).
+      #
+      # VIA port B runs the drives: PB5 drive 0's motor and PB4 drive 1's,
+      # each on while low, PB2-3 drive 0's stepper phases and PB0-1 drive
+      # 1's, and PB7 reads SYNC, low while ten one bits sit in the shift
+      # register. The 6530's port B picks the drive on PB0, the zone on
+      # PB1-2 and the side on PB4, low for the second, and reads write
+      # protect on PB3, high while the disk can't be written, and the sides
+      # on PB6, low for two, which jumper E3 grounds on the 8250. Its port
+      # A holds the byte to write.
+      #
+      # Each phase change moves the head a track: the controller steps
+      # through the Gray code 00, 10, 11, 01 outward and back the other way
+      # inward ($FF9C), and bumps the head against track 1 with 92 steps
+      # out.
+      #
+      # A turning disk passes one byte cell under the head every ten bit
+      # cells, at 6 MHz divided by 16 less the track's zone, and the byte
+      # cells come round 300 times a minute (Disk). Each data cell ends in
+      # byte ready, which latches the GCR ROM's byte into VIA port A through
+      # CA1 and pulses the controller's SO pin; a sync cell holds SYNC low
+      # for the cell after it instead. While the VIA's CB2 is low the drive
+      # writes: each cell takes the 6530's port A, or a sync while CA2 is
+      # high, and still ends in byte ready.
+      #
+      # A disk going in or out passes the write-protect sensor, which the
+      # controller watches for a disk change: it reads high for a while.
+      class Mechanism
+        WRITE_PROTECT = 0x08
+        ONE_SIDE = 0x40
+
+        # The cycles the write-protect sensor reads high as a disk goes in
+        # or out, ten of the controller's 5 ms interrupts.
+        CHANGE_CYCLES = 50_000
+
+        attr_reader :sides, :data_in, :cylinders, :so_pending
+        attr_accessor :via, :rriot
+
+        def initialize(sides:)
+          @sides = sides
+          @via = nil
+          @rriot = nil
+          @disks = [nil, nil]
+          @cylinders = [0, 0]
+          @phases = [0, 0]
+          @positions = [0, 0]
+          @clocks = [0, 0]
+          @changing = [0, 0]
+          @motors = [false, false]
+          @so_pending = false
+          @data_in = 0xff
+          @syncs = [false, false]
+          @ca1_low = false
+        end
+
+        # The Disk in +drive+, 0 or 1, or nil.
+        def disk(drive = 0) = @disks[drive]
+
+        def insert(disk, drive = 0)
+          @disks[drive]&.flush
+          @disks[drive] = disk
+          @changing[drive] = CHANGE_CYCLES
+        end
+
+        def flush
+          @disks.each { |disk| disk&.flush }
+        end
+
+        def motor_on?(drive = 0) = @motors[drive]
+
+        # The track under +drive+'s head on the side the 6530 picks.
+        def track(drive = 0)
+          side = drive == selected_drive ? selected_side : 0
+          @cylinders[drive] + 1 + (side * Storage::D80Image::SIDE_TRACKS)
+        end
+
+        def cycle!
+          if @ca1_low
+            @ca1_low = false
+            @via.ca1 = true
+          end
+          drives = @via.port_b_output
+          turn(0, drives.nobits?(0x20), (drives >> 2) & 0x03)
+          turn(1, drives.nobits?(0x10), drives & 0x03)
+        end
+
+        # Whether a cycle would change nothing: both motors off, no disk
+        # going in or out, and no byte ready under way.
+        def quiet?
+          !@motors[0] && !@motors[1] && @changing[0].zero? && @changing[1].zero? && !@ca1_low && !@so_pending
+        end
+
+        # What the drives hold, for comparing them at two points.
+        def idle_state = [*@cylinders, *@phases, *@motors, *@syncs, @data_in]
+
+        # Whether byte ready pulses the controller's SO pin this cycle,
+        # which takes the pulse.
+        def take_so
+          so = @so_pending
+          @so_pending = false
+          so
+        end
+
+        # Whether ten one bits sit in the shift register, off the selected
+        # drive's head.
+        def sync? = @syncs[selected_drive]
+
+        # The 6530's port B inputs.
+        def status_lines
+          lines = 0xff
+          lines &= ~WRITE_PROTECT unless write_protected?(selected_drive)
+          @sides == 2 ? lines & ~ONE_SIDE : lines
+        end
+
+        private
+
+        def selected_drive = @rriot.port_b_output & 0x01
+
+        def selected_side = @sides == 2 && @rriot.port_b_output.nobits?(0x10) ? 1 : 0
+
+        def write_protected?(drive)
+          return true if @changing[drive].positive?
+
+          disk = @disks[drive]
+          disk ? disk.write_protected? : false
+        end
+
+        def turn(drive, motor, phase)
+          @changing[drive] -= 1 if @changing[drive].positive?
+          step(drive, phase) if phase != @phases[drive]
+          motor_off(drive) if @motors[drive] && !motor
+          @motors[drive] = motor
+          return @syncs[drive] = false unless motor && @disks[drive]
+
+          clock = @clocks[drive] + 6
+          byte = 10 * (16 - Disk.zone_of(track(drive)))
+          if clock >= byte
+            clock -= byte
+            pass_cell(drive)
+          end
+          @clocks[drive] = clock
+        end
+
+        # Gray code index of a phase pair: 00, 10, 11, 01.
+        def phase_index(phase) = [0, 3, 1, 2][phase]
+
+        def step(drive, phase)
+          change = (phase_index(phase) - phase_index(@phases[drive])) & 0x03
+          @phases[drive] = phase
+          cylinder = @cylinders[drive]
+          if change == 1
+            cylinder -= 1
+          elsif change == 3
+            cylinder += 1
+          end
+          @cylinders[drive] = cylinder.clamp(0, Storage::D80Image::SIDE_TRACKS - 1)
+        end
+
+        def motor_off(drive)
+          @disks[drive]&.flush
+        end
+
+        # A cell has passed under +drive+'s head.
+        def pass_cell(drive)
+          disk = @disks[drive]
+          number = track(drive)
+          cells = disk.track(number)
+          return unless cells
+
+          position = @positions[drive] % cells.length
+          @positions[drive] = position + 1
+          return unless drive == selected_drive
+
+          writing? ? write_cell(drive, disk, number, cells, position) : read_cell(drive, cells, position)
+        end
+
+        def writing? = (@via.pcr & 0xe0) == 0xc0
+
+        def read_cell(drive, cells, position)
+          cell = cells[position]
+          @syncs[drive] = cell == Disk::SYNC
+          byte_ready(cell) unless cell == Disk::SYNC
+        end
+
+        def write_cell(drive, disk, number, cells, position)
+          cells[position] = @via.pcr.allbits?(0x0e) ? Disk::SYNC : @rriot.port_a_output
+          disk.written(number)
+          @syncs[drive] = false
+          byte_ready(@data_in)
+        end
+
+        def byte_ready(byte)
+          @data_in = byte
+          @via.ca1 = false
+          @ca1_low = true
+          @so_pending = true
+        end
+      end
+
+      # VIA port A reads the decoded byte, and PB7 SYNC, low while the
+      # shift register holds a sync.
+      class ReadLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = @mechanism.data_in
+
+        def read_b(_lines) = @mechanism.sync? ? 0x7f : 0xff
+      end
+
+      # The 6530's port B inputs from the drives.
+      class StatusLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = 0xff
+
+        def read_b(_lines) = @mechanism.status_lines
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/parts.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # Each chip a class of its own, so each keeps one type of peripheral.
+
+      # UC1, on the IEEE-488 data lines.
+      class DataRIOT < Chips::RIOT
+      end
+
+      # UE1, on the control lines, the jumpers and the LEDs.
+      class ControlRIOT < Chips::RIOT
+      end
+
+      # UM3, the controller's VIA, at $0040.
+      class ControllerVIA < Chips::VIA
+      end
+
+      # UK3, the controller's 6530, its ROM the controller's program.
+      class ControllerRRIOT < Chips::RRIOT
+      end
+
+      # The interface processor's 6502, UN1, on the IPBus.
+      class IPCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The floppy controller's 6502, UH3, on the FDCBus.
+      class FDCCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050.rb

@@ -0,0 +1,243 @@
+# frozen_string_literal: true
+
+require "badline/chips/riot"
+require "badline/chips/rriot"
+require "badline/drives/ieee_bus"
+require "badline/drives/engine"
+require "badline/drives/model8050/ip_bus"
+require "badline/drives/model8050/fdc_bus"
+require "badline/drives/model8050/parts"
+require "badline/drives/model8050/ieee_port"
+require "badline/drives/model8050/disk"
+require "badline/drives/model8050/mechanism"
+require "badline/drives/model8050/idle"
+require "badline/drives/model8050/keyed_state"
+
+module Badline
+  module Drives
+    # The 8050 dual disk drive of the PET and CBM-II, two drives on one
+    # IEEE-488 unit (schematic 8050001; the 8050/8250 service manual).
+    #
+    # Two 6502s share the board, clocked at 1 MHz from one 12 MHz crystal
+    # on opposite phases. The interface processor (IP) runs DOS 2.7 from
+    # 16 KB of ROM at $C000, with two 6532s (IPBus): their RAM is its zero
+    # page and stack, and their ports face the IEEE-488 bus (IEEEPort). The
+    # floppy controller (FDC) runs the 1 KB program in its 6530's ROM, with
+    # a VIA and the 6530 facing the drives (FDCBus, Mechanism). The two
+    # meet in 4 KB of common RAM, which each reaches in its own half of
+    # the cycle: the IP leaves jobs there, and the FDC runs them.
+    #
+    # Reset starts both. The FDC waits on the common RAM for the IP, which
+    # tests it, copies the FDC's start-up code into it ($C370) and waits for
+    # the FDC to answer, before both settle into their idle loops.
+    #
+    # The drive clocks against the host through a phase accumulator, as
+    # Drives::Engine::Core does: each host cycle adds 1 MHz of phase, and
+    # every whole host period in it runs a cycle of both processors. While
+    # both processors idle, it sleeps instead (Idle), and the readers of its
+    # parts catch it up first.
+    class Model8050
+      include Idle
+
+      CLOCK_HZ = 1_000_000
+
+      # The host cycles by which a unit switched on with the machine has
+      # run the IP's RAM test and the FDC's start-up and reads its jumpers.
+      BOOT_CYCLES = 1_500_000
+
+      attr_reader :device, :ieee_bus
+
+      def ip_cpu = settled(@ip_cpu)
+
+      def fdc_cpu = settled(@fdc_cpu)
+
+      def ip_bus = settled(@ip_bus)
+
+      def fdc_bus = settled(@fdc_bus)
+
+      def common = settled(@common)
+
+      def data_riot = settled(@data_riot)
+
+      def control_riot = settled(@control_riot)
+
+      def via = settled(@via)
+
+      def rriot = settled(@rriot)
+
+      def mechanism = settled(@mechanism)
+
+      def cycles
+        settle!
+        @cycles
+      end
+
+      attr_writer :host_clock_hz
+
+      def model_name = "8050"
+
+      # The sides each drive's disk has.
+      def sides = 1
+
+      # +dos_rom+ covers $C000-$FFFF and +fdc_rom+ is the 6530's mask, each
+      # defaulting to the image in the ROM path: DOS 2.7 and the mask for
+      # MPI mechanisms. +device+ is the number the jumpers set, 8 to 15.
+      def initialize(dos_rom: nil, fdc_rom: nil, host_clock_hz: CLOCK_HZ, device: 8)
+        @device = device
+        @host_clock_hz = host_clock_hz
+        @phase = 0
+        @cycles = 0
+        build_ip(dos_rom || ROM.load("8050/dos-2.7.rom", 0xc000))
+        build_fdc(fdc_rom || ROM.read("8050/fdc-901869-01.rom"))
+        @ip_cpu = IPCPU.new(@ip_bus)
+        @fdc_cpu = FDCCPU.new(@fdc_bus)
+        init_idle
+        @ieee_bus.attach(self)
+      end
+
+      # Plugs the unit into an IEEE-488 bus, leaving the one it was on.
+      def connect(ieee_bus)
+        settle!
+        @ieee_bus.detach(self)
+        @ieee_bus = ieee_bus
+        @ieee_port.bus = ieee_bus
+        ieee_bus.attach(self)
+      end
+
+      # The lines the unit pulls on the bus while ATN is low or not
+      # (IEEEPort).
+      def ieee_low_lines(atn) = @ieee_port.ieee_low_lines(atn)
+
+      # The controller pushed its lines into the bus.
+      def host_written! = nil
+
+      # Which LEDs are lit: bit 0 drive 1's, bit 1 drive 0's, bit 2 the
+      # error LED. They hold still while the unit sleeps, so reading them
+      # leaves it asleep.
+      def leds = @ieee_port.leds
+
+      def led_on? = leds.anybits?(0x03)
+
+      # Puts a Disk in +drive+, 0 or 1. Nil takes the disk out.
+      def insert(disk, drive: 0)
+        settle!
+        @mechanism.insert(disk, drive)
+      end
+
+      # Puts in the .d80 or .d82 image at +path+, write-protected with
+      # `read_only`.
+      def insert_image(path, drive: 0, read_only: false)
+        image_class = File.extname(path).casecmp?(".d82") ? Storage::D82Image : Storage::D80Image
+        insert(Disk.new(image_class.new(path, read_only:)), drive:)
+      end
+
+      # The Disk in +drive+, or nil.
+      def disk(drive = 0) = @mechanism.disk(drive)
+
+      # Stores what the heads wrote in the disks' images, as the motors
+      # stopping do.
+      def flush
+        settle!
+        @mechanism.flush
+      end
+
+      def power_led_on? = true
+
+      # Runs the drive cycles that fall in one host cycle, then takes the
+      # controller's lines for the next. Asleep, the unit owes the cycles
+      # instead, and wakes once the controller has moved a line.
+      def host_cycle!
+        phase = @phase + CLOCK_HZ
+        while phase >= @host_clock_hz
+          @asleep ? owe_cycle : run_cycle
+          phase -= @host_clock_hz
+        end
+        @phase = phase
+        settle! if @asleep && @ieee_port.lines_moved?
+        @ieee_port.latch_host
+      end
+
+      def cycle!
+        settle!
+        run_cycle
+      end
+
+      # The bus's IFC line resets both processors and every chip. RAM keeps
+      # its contents.
+      def reset!
+        settle!
+        @data_riot.reset!
+        @control_riot.reset!
+        @via.reset!
+        @rriot.reset!
+        @ip_cpu.reset!
+        @fdc_cpu.reset!
+      end
+
+      def inspect
+        "#<#{self.class.name} cycles=#{@cycles} ip=(#{@ip_cpu.inspect}) fdc=(#{@fdc_cpu.inspect})>"
+      end
+
+      private
+
+      def settled(part)
+        settle!
+        part
+      end
+
+      def run_cycle
+        step
+        watch_loops if @idle_skip
+      end
+
+      def build_ip(rom)
+        @common = Memory.new([], length: 0x1000)
+        @ieee_bus = IEEEBus.new
+        @ieee_port = IEEEPort.new(device: @device, bus: @ieee_bus)
+        @data_riot = DataRIOT.new(peripheral: DataLines.new(@ieee_port))
+        @control_riot = ControlRIOT.new(peripheral: ControlLines.new(@ieee_port))
+        @ieee_port.data_riot = @data_riot
+        @ieee_port.control_riot = @control_riot
+        @ip_bus = IPBus.new(rom:, common: @common, data_riot: @data_riot, control_riot: @control_riot)
+      end
+
+      def build_fdc(rom)
+        @mechanism = Mechanism.new(sides:)
+        @via = ControllerVIA.new(start: 0x0040, peripheral: ReadLines.new(@mechanism))
+        @rriot = ControllerRRIOT.new(rom:, peripheral: StatusLines.new(@mechanism))
+        @fdc_bus = FDCBus.new(common: @common, via: @via, rriot: @rriot)
+        @mechanism.via = @via
+        @mechanism.rriot = @rriot
+      end
+
+      # One cycle of the board: the drives, then the chips, then the IP and
+      # the FDC, each in its own half of the cycle. ATN reaches UE1's PA7 as
+      # the port latched it. UE1 pulls the IP's IRQ, and the VIA and the
+      # 6530 the FDC's. Byte ready sets the FDC's V flag through SO for the
+      # next cycle's instruction step, as on the 1541.
+      def step
+        so = @mechanism.take_so
+        @mechanism.cycle!
+        @control_riot.pa7 = @ieee_port.atn_low?
+        @data_riot.cycle!
+        @control_riot.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @ip_cpu.irq = @control_riot.irq?
+        @ip_cpu.cycle!
+        @fdc_cpu.irq = @via.irq? || @rriot.irq?
+        @fdc_cpu.so! if so
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
+    end
+
+    # The 8250: the 8050's board driving double-sided mechanisms, 154 tracks
+    # a disk, with jumper E3 grounding the 6530's PB6 to say so.
+    class Model8250 < Model8050
+      def model_name = "8250"
+
+      def sides = 2
+    end
+  end
+end

data/lib/badline/frontend/app.rb

@@ -111,16 +111,23 @@ module Badline
         end
       end
 
+      # The window keeps F8, F9, F10, Tab and the snapshot keys for itself,
+      # but for the keys the machine claims (Controls#claims?).
       def handle_key(scancode, down)
-        if [Keys::F8, Keys::F9, Keys::F10].include?(scancode) || (scancode == Keys::TAB && @controls.tab_toggles?)
+        claimed = @controls.claims?(scancode)
+        if !claimed && toggle?(scancode)
           handle_toggle(scancode) if down
-        elsif down && @snapshots.key(scancode)
+        elsif !claimed && down && @snapshots.key(scancode)
           swap(@snapshots.computer)
-        elsif !Snapshots::KEYS.include?(scancode)
+        elsif claimed || !Snapshots::KEYS.include?(scancode)
           @controls.key(scancode, down)
         end
       end
 
+      def toggle?(scancode)
+        [Keys::F8, Keys::F9, Keys::F10].include?(scancode) || (scancode == Keys::TAB && @controls.tab_toggles?)
+      end
+
       # Runs the restored machine in place of the one before: the screen,
       # the drive LED, the controls, the gamepads and the sound go over to
       # it.

data/lib/badline/frontend/boot.rb

@@ -10,7 +10,7 @@ module Badline
     # attach, an --at key names nothing or an event fails, which it warns
     # about.
     def self.run(options)
-      error = Timeline.error(options.timeline, options.family)
+      error = Timeline.error(options.timeline, options.p500? ? :p500 : options.family)
       unless error.empty?
         warn "#{options.program}: #{error}"
         return 1

data/lib/badline/frontend/controls.rb

@@ -8,10 +8,12 @@ module Badline
     #   switches, the arrow cluster and space drive one joystick and WASD
     #   and left shift the other. The arrows start on joystick 2, and
     #   #swap_ports swaps them. The VIC-20's one joystick takes both. The
-    #   PET has no joystick, and its keys go by the character they type
-    #   (PETKeyboard).
-    # - A pot device the pause menu plugs into a C64 control port: a 1351
-    #   mouse or a pair of paddles, which the host mouse drives. Motion
+    #   PET's and the CBM-II's keys go by the character they type
+    #   (PETKeyboard), and the PET and the CBM-II's B series have no
+    #   joystick.
+    # - A pot device the pause menu plugs into a control port of a C64, a
+    #   C128 or a P500: a 1351 mouse or a pair of paddles, which the host
+    #   mouse drives. Motion
     #   turns the paddles or moves the mouse, and the host's left and right
     #   buttons go to whichever lines the device puts them on.
     class Controls
@@ -24,6 +26,21 @@ module Badline
       # The pot device plugged in, one of POTS.
       attr_reader :pot, :arrows_port
 
+      # Whether the machine has joysticks: all but the PET and the CBM-II's
+      # B series.
+      def self.joysticks?(computer)
+        family = computer.family
+        family != :pet && (family != :cbm2 || p500?(computer))
+      end
+
+      # Whether the machine is the CBM-II's P500, which has the B series'
+      # keyboard and two joysticks.
+      def self.p500?(computer) = computer.is_a?(CBM2::P500)
+
+      # Whether the machine's keys go by the character they type: the PET's
+      # and the CBM-II's.
+      def self.symbolic?(computer) = %i[pet cbm2].include?(computer.family)
+
       def initialize(computer)
         @computer = computer
         @joystick = false
@@ -58,9 +75,19 @@ module Badline
         self.joystick_mode = !@joystick if tab_toggles?
       end
 
-      # Whether Tab switches the keys to the joysticks, or on the PET, which
-      # has none, is a key of its own.
-      def tab_toggles? = @computer.family != :pet
+      # Whether Tab switches the keys to the joysticks, or on a machine
+      # without them is a key of its own.
+      def tab_toggles? = Controls.joysticks?(@computer)
+
+      # Whether the machine takes a key the window would otherwise keep for
+      # itself: on the CBM-II, F8, RUN/STOP on F12, Alt with F9 or F10, and
+      # the release of any key it pressed.
+      def claims?(scancode)
+        return false unless @computer.family == :cbm2
+        return true if @pet_keyboard.holds?(scancode) || [Keys::F8, Keys::F12].include?(scancode)
+
+        @pet_keyboard.alt? && [Keys::F9, Keys::F10].include?(scancode)
+      end
 
       # Plugs in one of POTS, in place of the one before.
       def plug(pot)
@@ -116,7 +143,7 @@ module Badline
       # A host key lets go of the key it pressed, though the C128 has
       # switched between C64 and C128 mode since and maps it elsewhere.
       def machine_key(scancode, down)
-        return @pet_keyboard.key(scancode, down) if @computer.family == :pet
+        return @pet_keyboard.key(scancode, down) if Controls.symbolic?(@computer)
 
         @held[scancode] = host_key(scancode) if down || !@held.key?(scancode)
         key = @held[scancode]
@@ -159,7 +186,7 @@ module Badline
       # A fresh pot device on its port, and none on the other. A machine
       # without the ports takes none.
       def attach_pot_device
-        ports = @computer.family == :pet ? nil : @computer.control_ports
+        ports = Controls.p500?(@computer) || !Controls.symbolic?(@computer) ? @computer.control_ports : nil
         if ports.nil?
           @pot = :none
           return
@@ -211,17 +238,26 @@ module Badline
         down ? joystick.press(direction) : joystick.release(direction)
       end
 
-      # The PET's keyboard for a PET, and for any other machine one it never
-      # uses.
+      # The PET's keyboard for a PET or a CBM-II, and for any other machine
+      # one it never uses.
       def pet_keyboard(computer)
-        PETKeyboard.new(computer.keyboard, computer.family == :pet ? computer.model.keyboard : :graphics)
+        layout = case computer.family
+                 when :pet then computer.model.keyboard
+                 when :cbm2 then :cbm2
+                 else :graphics
+                 end
+        PETKeyboard.new(computer.keyboard, layout)
       end
 
       def release_all
-        return @pet_keyboard.release_all if @computer.family == :pet
+        if Controls.symbolic?(@computer)
+          @pet_keyboard.release_all
+        else
+          Keys::ARROWS.each_key { |scancode| @computer.keyboard.release(host_key(scancode)) }
+          Keys::WASD.each_key { |scancode| @computer.keyboard.release(host_key(scancode)) }
+        end
+        return unless Controls.joysticks?(@computer)
 
-        Keys::ARROWS.each_key { |scancode| @computer.keyboard.release(host_key(scancode)) }
-        Keys::WASD.each_key { |scancode| @computer.keyboard.release(host_key(scancode)) }
         Keys::ARROWS.each_value do |direction|
           @computer.joystick1.release(direction)
           @computer.joystick2.release(direction)

data/lib/badline/frontend/gamepads.rb

@@ -7,8 +7,8 @@ module Badline
     # second one joystick 1. PadPort holds the mapping.
     #
     # The controllers are polled every frame, and rescanned whenever SDL
-    # reports one added or removed. The PET has no joysticks, and the
-    # controllers steer two that nothing reads.
+    # reports one added or removed. The PET and the CBM-II's B series have
+    # no joysticks, and the controllers steer two that nothing reads.
     class Gamepads
       PORTS = [2, 1].freeze
 
@@ -53,7 +53,7 @@ module Badline
       private
 
       def joystick(computer, port)
-        return Input::Joystick.new if computer.family == :pet
+        return Input::Joystick.new unless Controls.joysticks?(computer)
 
         port == 1 ? computer.joystick1 : computer.joystick2
       end