badline 0.12.1 → 0.13.0

data/lib/badline/drive1581/wd1772/tracks.rb

@@ -1,125 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1581
-    class WD1772
-      # The type III commands that take a whole turn, from one index pulse
-      # to the next:
-      #
-      #   11100hE00  read track   every byte under the head (Track#raw)
-      #   11110hEP0  write track  every byte the CPU sends, for a format
-      #
-      # Write track asks for its first byte at once and starts at the index
-      # pulse, giving up with LOST_DATA if the byte hasn't come three bytes
-      # later. $F5 writes a sync mark, an $A1, and the first of a run starts
-      # the CRC over; $F6 writes $C2; $F7 writes the CRC's two bytes. At
-      # the next index pulse the track under the head becomes the fields
-      # found in what went down (Track.parse).
-      module Tracks
-        LATE = 3
-
-        private
-
-        def start_type3
-          @type1 = false
-          @status = 0
-          @drq = false
-          @mode = @command.anybits?(0x10) ? WRITE : READ
-          resume_track unless spinning_up?(TRACK_INDEX)
-        end
-
-        def resume_track
-          if @mode == WRITE
-            if @mechanism.write_protected?
-              @status |= PROTECTED
-              return finish
-            end
-            @drq = true
-          end
-          @phase = @mode == WRITE ? WRITE_TRACK_START : TRACK_INDEX
-          return wait_index(@phase) if @command.nobits?(SETTLE_DELAY)
-
-          @due = @now + SETTLE
-          @settling = true
-        end
-
-        def wait_index(phase)
-          @settling = false
-          @phase = phase
-          @due = next_index
-        end
-
-        def track_index
-          return wait_index(TRACK_INDEX) if @settling
-
-          @bytes = (@mechanism.track || Track.new([])).raw
-          @index = 0
-          @phase = READ_TRACK
-          @due = @now + BYTE
-        end
-
-        def track_byte_read
-          @status |= LOST_DATA if @drq
-          @data = @bytes[@index]
-          @drq = true
-          @index += 1
-          @index == Track::LENGTH ? finish : @due += BYTE
-        end
-
-        def write_track_start
-          return wait_index(WRITE_TRACK_START) if @settling
-
-          @bytes = []
-          @syncs = []
-          @crc = 0xffff
-          @phase = WRITE_TRACK
-          return track_byte_written unless @drq
-
-          @late = true
-          @due = @now + (LATE * BYTE)
-        end
-
-        # The next byte from the data register goes under the head, a 0
-        # where DRQ went unanswered.
-        def track_byte_written
-          return lost if @late && @drq
-          return track_written if @bytes.length >= Track::LENGTH
-
-          @late = false
-          value = @drq ? 0 : @data
-          @status |= LOST_DATA if @drq
-          @drq = true
-          before = @bytes.length
-          lay_byte(value)
-          @due = @now + ((@bytes.length - before) * BYTE)
-        end
-
-        def lay_byte(value)
-          case value
-          when 0xf5
-            @crc = 0xffff unless @syncs.last
-            push_byte(Track::SYNC, true)
-          when 0xf6 then push_byte(0xc2, false)
-          when 0xf7
-            crc = @crc
-            push_byte(crc >> 8, false)
-            push_byte(crc & 0xff, false)
-          else push_byte(value, false)
-          end
-        end
-
-        def push_byte(value, sync)
-          @bytes << value
-          @syncs << sync
-          @crc = Track.crc([value], @crc)
-        end
-
-        def track_written
-          @drq = false
-          @mechanism.write(Track.parse(@bytes.first(Track::LENGTH), @syncs))
-          finish
-        end
-      end
-    end
-  end
-end

data/lib/badline/drive1581/wd1772/turn.rb

@@ -1,73 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1581
-    class WD1772
-      # The disk turning under the head: the index pulses a phase waits
-      # for or counts, and the cycle the head comes to a place round the
-      # track.
-      module Turn
-        # The disk began or stopped turning: a phase waiting on the turn
-        # starts its wait again.
-        def spin_changed
-          case @phase
-          when SPIN_UP, MOTOR_IDLE, INDEX_INTERRUPT then count_index
-          when SEARCH then begin_search
-          when TRACK_INDEX, WRITE_TRACK_START then wait_index(@phase)
-          end
-        end
-
-        private
-
-        # The motor starts: with h clear and the motor off, the command waits
-        # out six index pulses first, and the phase comes after them.
-        def spinning_up?(phase)
-          spin_up = !@motor_on && @command.nobits?(NO_SPIN_UP)
-          @motor_on = true
-          return false unless spin_up
-
-          @after_spin_up = phase
-          @phase = SPIN_UP
-          @count = 6
-          count_index
-          true
-        end
-
-        # Waits for @count index pulses, or for the disk to turn.
-        def count_index
-          @due = next_index
-        end
-
-        def index_counted
-          @count -= 1
-          return @due += Mechanism::REVOLUTION if @count.positive?
-
-          case @phase
-          when SPIN_UP then spun_up
-          when MOTOR_IDLE
-            @motor_on = false
-            idle
-          else
-            @intrq = true
-            idle
-          end
-        end
-
-        # The cycle the next index pulse starts, or NEVER while no disk turns.
-        def next_index = at_angle(0)
-
-        # The cycle the head next comes to +angle+, from the index.
-        def at_angle(angle)
-          return NEVER unless @mechanism.spinning?
-
-          delta = (angle - @mechanism.angle(@now)) % Mechanism::REVOLUTION
-          @now + (delta.zero? ? Mechanism::REVOLUTION : delta)
-        end
-
-        # The cycle the byte at +position+ round the track has passed under
-        # the head.
-        def byte_end(position) = at_angle(((position + 1) % Track::LENGTH) * BYTE)
-      end
-    end
-  end
-end

data/lib/badline/drive1581/wd1772.rb

@@ -1,216 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/drive1581/wd1772/registers"
-require "badline/drive1581/wd1772/turn"
-require "badline/drive1581/wd1772/stepping"
-require "badline/drive1581/wd1772/sectors"
-require "badline/drive1581/wd1772/sector_writes"
-require "badline/drive1581/wd1772/tracks"
-require "badline/drive1581/wd1772/state"
-
-module Badline
-  class Drive1581
-    # The WD1772 floppy disk controller at $6000, as the WD177x data sheet
-    # describes it, working on the Mechanism's Track at sector level: it
-    # finds ID and data fields where they lie round the turn and moves
-    # their bytes at the MFM double-density rate, a byte every 32 µs, but
-    # keeps no flux or bitstream.
-    #
-    #   $6000  status (read), command (write)
-    #   $6001  track
-    #   $6002  sector
-    #   $6003  data
-    #
-    # It runs on the drive's clock, 2 MHz here, so the data sheet's times,
-    # given for 8 MHz on the chip's clock pin, come out as BYTE cycles a
-    # byte, STEP_RATES between steps and SETTLE for the head to settle.
-    #
-    # A command runs as a chain of phases, each due at a cycle (@due): a
-    # step, an index pulse, the end of a byte under the head. Between them
-    # nothing happens, so cycle! only counts. BUSY sets as the command is
-    # written, and the chip takes it up START cycles later, 16 µs, so a
-    # command with nothing to do, such as a seek to the track the head is
-    # on, still shows BUSY to the DOS, which polls for it before waiting
-    # for it to clear.
-    #
-    # The 1581 leaves INTRQ and DRQ unconnected and polls the status
-    # register instead (schematic sheet 2), but both are here (intrq?,
-    # drq?). Its DOS sets h in every command, so the motor spin-up wait
-    # never runs; the spindle follows the 8520's /MOTOR line instead.
-    class WD1772
-      include Registers
-      include Turn
-      include Stepping
-      include Sectors
-      include SectorWrites
-      include Tracks
-      include State
-
-      BYTE = 64
-      START = 32
-      STEP_RATES = [12_000, 24_000, 4_000, 6_000].freeze
-      SETTLE = 30_000
-
-      NEVER = 1 << 60
-
-      # Status bits. Bits 1 and 2 report the index pulse and track 0 after
-      # a type I command, and DRQ and lost data after the others; bit 5
-      # reports spin-up after a type I command and a deleted data mark
-      # after a read.
-      BUSY = 0x01
-      INDEX = 0x02
-      DATA_REQUEST = 0x02
-      TRACK0 = 0x04
-      LOST_DATA = 0x04
-      CRC_ERROR = 0x08
-      NOT_FOUND = 0x10
-      SPUN_UP = 0x20
-      DELETED = 0x20
-      PROTECTED = 0x40
-      MOTOR_ON = 0x80
-
-      # Command flags.
-      NO_SPIN_UP = 0x08
-      VERIFY = 0x04
-      SETTLE_DELAY = 0x04
-      MULTIPLE = 0x10
-      UPDATE = 0x10
-      DELETED_MARK = 0x01
-
-      # Phases.
-      IDLE = 0
-      SPIN_UP = 1
-      STEPPED = 2
-      SETTLED = 3
-      SEARCH = 4
-      READ_DATA = 5
-      WRITE_GATE = 6
-      WRITE_DATA = 7
-      READ_TRACK = 8
-      TRACK_INDEX = 9
-      WRITE_TRACK = 10
-      MOTOR_IDLE = 11
-      INDEX_INTERRUPT = 12
-      SETTLE_SEARCH = 13
-      READ_ADDRESS = 14
-      WRITE_TRACK_START = 15
-      STARTING = 16
-
-      # What a search for an ID field is for.
-      READ = 0
-      WRITE = 1
-      ADDRESS = 2
-      VERIFY_TRACK = 3
-
-      attr_reader :now, :track, :sector, :data, :command
-
-      def initialize(mechanism)
-        @mechanism = mechanism
-        @now = 0
-        @due = NEVER
-        @phase = IDLE
-        reset!
-      end
-
-      # The MR line: the registers as the data sheet leaves them, $03 in
-      # the command register and 1 in the sector register, and no command
-      # running.
-      def reset!
-        @command = 0x03
-        @track = 0
-        @sector = 1
-        @data = 0
-        @status = 0
-        @type1 = true
-        @drq = false
-        @intrq = false
-        @motor_on = false
-        @inward = true
-        clear_command
-        idle
-      end
-
-      def cycle!
-        @now += 1
-        advance if @now == @due
-      end
-
-      # How many cycles can go by before the next phase is due.
-      def quiet_cycles = @due - @now - 1
-
-      # Runs +cycles+ cycles at once, as many as quiet_cycles allows.
-      def fast_forward(cycles)
-        @now += cycles
-      end
-
-      def busy? = @phase != IDLE && @phase != MOTOR_IDLE && @phase != INDEX_INTERRUPT
-
-      def drq? = @drq
-
-      def intrq? = @intrq
-
-      def motor_on? = @motor_on
-
-      private
-
-      # A command ends: INTRQ, and the motor turns off after nine more
-      # index pulses unless a command comes first.
-      def finish
-        @intrq = true
-        @phase = MOTOR_IDLE
-        @count = 9
-        count_index
-      end
-
-      # What a command keeps between its phases.
-      def clear_command
-        @steps = 0
-        @count = 0
-        @after_spin_up = IDLE
-        @mode = 0
-        @deadline = NEVER
-        @id_at = NEVER
-        @found = -1
-        @bytes = []
-        @syncs = []
-        @index = 0
-        @crc = 0xffff
-        @crc_good = true
-        @write_id = 0
-        @size = 0
-        @gate_open = false
-        @late = false
-        @settling = false
-      end
-
-      def idle
-        @phase = IDLE
-        @due = NEVER
-      end
-
-      def advance
-        case @phase
-        when STARTING then start_command
-        when SPIN_UP, MOTOR_IDLE, INDEX_INTERRUPT then index_counted
-        when STEPPED then step_done
-        when SETTLED then verify_track
-        when SETTLE_SEARCH then begin_search
-        when SEARCH then id_passed
-        when READ_DATA, READ_ADDRESS then byte_read
-        else advance_write
-        end
-      end
-
-      def advance_write
-        case @phase
-        when WRITE_GATE then write_gate
-        when WRITE_DATA then byte_written
-        when READ_TRACK then track_byte_read
-        when TRACK_INDEX then track_index
-        when WRITE_TRACK_START then write_track_start
-        when WRITE_TRACK then track_byte_written
-        end
-      end
-    end
-  end
-end

data/lib/badline/drive1581.rb

@@ -1,233 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/drive"
-require "badline/drive1581/track"
-require "badline/drive1581/track_bytes"
-require "badline/drive1581/disk"
-require "badline/drive1581/mechanism"
-require "badline/drive1581/wd1772"
-require "badline/drive1581/cpu"
-require "badline/drive1581/serial_port"
-require "badline/drive1581/bus"
-
-module Badline
-  # The 1581 3.5" disk drive: a 6502 at 2 MHz with 8 KB of RAM, an 8520
-  # for the serial bus and the mechanism's lines, a WD1772 for the MFM
-  # disk, and the DOS in 32 KB of ROM (1581 Service Manual). Drive::Core
-  # clocks it against the host.
-  #
-  # The 8520's port B faces the serial bus as VIA 1's does on the 1541,
-  # with the same bits, and ATN reaches its FLAG pin, so ATN going low
-  # interrupts the DOS. Its SP and CNT carry fast serial on DATA and SRQ,
-  # through buffers PB5 turns round (Drive::FastSerial), as the 1571's
-  # 6526 does. The ATN acknowledge differs: a NAND of ATN IN and
-  # ATN ACK pulls DATA, so DATA follows ATN only while ATN is asserted
-  # and PB4 is high, where the 1541's XOR pulls it whenever the two
-  # differ (IECBus::DRIVE_ATN_GATED). Port A drives the motor, the side
-  # and the two LEDs, and reads the switches and the mechanism's /RDY and
-  # /DISK CHNG (SerialPort). Timer B interrupts every 10 ms for the
-  # controller code that runs the WD1772.
-  #
-  # The 8520 differs from the 6526 in its TOD, a 24-bit binary event
-  # counter where the 6526 keeps a BCD clock. The 1581 holds the TOD pin
-  # high when it carries a WD1772 (jumper J1 out), so the counter never
-  # counts, and the DOS's one use of it, writing $00 to the low byte and
-  # reading it back 20 µs later to tell a WD1770 from a WD1772, reads $00
-  # on either chip: the drive's CIA gets no TOD pulses (CIA's tod_hz).
-  class Drive1581
-    include Drive::Core
-    include Drive::FastSerial
-
-    CLOCK_HZ = 2_000_000
-
-    # Where the DOS's idle loop starts over (see Drive::Idle).
-    IDLE_LOOP = 0xb105
-
-    # The host cycles, at about 1 MHz, by which a 1581 switched on with the
-    # machine has run its DOS's reset, the RAM test, the ROM checksum and
-    # the controller's half-second wait, and waits on the bus: 2.32 s,
-    # with a margin.
-    BOOT_CYCLES = 2_700_000
-
-    # The 8520's port A outputs.
-    SIDE = 0x01
-    MOTOR = 0x04
-    POWER_LED = 0x20
-    ACTIVITY_LED = 0x40
-
-    # Port B's ATN acknowledge, and the fast serial direction.
-    ATN_ACK = 0x10
-    FAST_SERIAL_OUT = 0x20
-
-    def cia
-      settle!
-      @cia
-    end
-
-    def fdc
-      settle!
-      @fdc
-    end
-
-    def model_name = "1581"
-
-    # +rom+ covers $8000-$FFFF, and defaults to the DOS image in the ROM
-    # path. +device+ is the number the switches on port A's PA3 and PA4
-    # set, 8 to 11.
-    def initialize(rom: nil, host_clock_hz: Drive1541::CLOCK_HZ, device: 8, debug: false)
-      @device = device
-      @clock_hz = CLOCK_HZ
-      @mechanism = Mechanism.new
-      @fdc = WD1772.new(@mechanism)
-      @serial_port = SerialPort.new(@mechanism, device:)
-      @cia = CIA.new(start: 0x4000, peripheral: @serial_port, tod_hz: 0)
-      @bus = Bus.new(rom: rom || ROM.load("dos1581.rom", 0x8000), cia: @cia, fdc: @fdc, drive: self)
-      @cpu = CPU.new(@bus, debug:)
-      @idle_loop = IDLE_LOOP
-      @host_clock_hz = host_clock_hz
-      @phase = 0
-      @cycles = 0
-      @serial_bus = nil
-      @atn = false
-      @activity = false
-      @power = false
-      init_fast_serial
-      init_idle(debug)
-      ports_written
-      connect(IECBus.new)
-    end
-
-    # The serial bus's RESET line reaches the CPU, the 8520 and the
-    # WD1772. RAM keeps its contents.
-    def reset!
-      settle!
-      @cia.reset!
-      @fdc.reset!
-      ports_written
-      @cpu.reset!
-    end
-
-    def insert(disk)
-      settle!
-      @mechanism.insert(disk, @fdc.now)
-      @fdc.spin_changed
-    end
-
-    # Puts in a Disk from the .d81 image at +path+, write-protected with
-    # `read_only`.
-    def insert_image(path, read_only: false)
-      insert(Disk.open(path, read_only:))
-    end
-
-    # Whether the activity LED is lit. The power LED stays lit, and
-    # flashes on an error.
-    def led_on? = @activity
-
-    def power_led_on? = @power
-
-    # The 8520's port B as it drives the serial bus, in VIA 1's bits, the
-    # ATN acknowledge turned round for the NAND that gates it, with the
-    # fast serial pins above it. It holds still while the drive sleeps, so
-    # reading it leaves the drive asleep.
-    def serial_output
-      lines = @cia.port_b_lines
-      output = (lines & (IECBus::DRIVE_DATA_OUT | IECBus::DRIVE_CLK_OUT)) | IECBus::DRIVE_ATN_GATED | @fast_output
-      lines.anybits?(ATN_ACK) ? output : output | IECBus::DRIVE_ATNA
-    end
-
-    # The 8520's ports drive the motor, the side, the LEDs and the fast
-    # serial buffers: the drive follows them after every write to a port
-    # or direction register.
-    def ports_written
-      fast_serial_out = @cia.port_b_lines.anybits?(FAST_SERIAL_OUT)
-      turn_fast_serial(fast_serial_out) if fast_serial_out != @fast_serial_out
-      lines = @cia.port_a_lines
-      @mechanism.side = lines.anybits?(SIDE) ? 1 : 0
-      @activity = lines.anybits?(ACTIVITY_LED)
-      @power = lines.anybits?(POWER_LED)
-      motor = lines.nobits?(MOTOR)
-      return if motor == @mechanism.motor_on?
-
-      @mechanism.motor(motor, @fdc.now)
-      @fdc.spin_changed
-    end
-
-    # The drive's whole state, as the 1541's (Drive1541#save_state), with
-    # the 8520 and the WD1772 in place of the VIAs.
-    def save_state(out)
-      settle!
-      out.marker("DRIVE1581")
-      out.int(@phase).int(@cycles).boolean(@atn)
-      @serial_port.save_state(out)
-      @cia.save_state(out)
-      @fdc.save_state(out)
-      @bus.save_state(out)
-      @cpu.save_state(out)
-      @mechanism.save_state(out)
-    end
-
-    def load_state(input)
-      settle!
-      input.marker("DRIVE1581")
-      @phase = input.int
-      @cycles = input.int
-      @atn = input.boolean?
-      @serial_port.load_state(input)
-      @cia.load_state(input)
-      @fdc.load_state(input)
-      @bus.load_state(input)
-      @cpu.load_state(input)
-      @mechanism.load_state(input)
-      @fast_serial_out = @cia.port_b_lines.anybits?(FAST_SERIAL_OUT)
-      ports_written
-      push_fast_output(@fast_serial_out ? fast_pins : 0)
-      forget_orbits
-    end
-
-    private
-
-    # One drive cycle: ATN going low pulls FLAG, the WD1772 and the 8520
-    # clock ahead of the CPU, and the 8520 alone pulls IRQ.
-    def step
-      atn = @serial_port.atn_low?
-      if atn != @atn
-        @atn = atn
-        @cia.flag! if atn
-      end
-      @fdc.cycle!
-      @cia.cycle!
-      drive_fast_serial if @fast_serial_out
-      @cpu.irq = @cia.interrupted?
-      @cpu.cycle!
-      @cycles += 1
-    end
-
-    def hear_atn
-      @atn = @serial_port.atn_low?
-    end
-
-    # A pass of the idle loop reads and writes RAM alone, so it repeats
-    # while the 8520 pulls no IRQ, for as long as the 8520's counters and
-    # the WD1772's next phase leave room: until timer B's next interrupt
-    # for the controller code. Neither chip changes but by the clock, so
-    # only the CPU is compared.
-    def busy_for_pass? = @cia.interrupted?
-
-    def quiet_cycles = [@cia.quiet_cycles, @fdc.quiet_cycles].min
-
-    def idle_state = [*@cpu.idle_state, @bus.data, @atn]
-
-    def fast_forward_chips(cycles)
-      @cia.fast_forward(cycles)
-      @fdc.fast_forward(cycles)
-    end
-
-    # Every timer B interrupt reads the 8520, so no orbit (Drive::Orbit)
-    # comes round, and the drive keeps no anchors.
-    def anchor = nil
-
-    def counter_state(_touched) = []
-
-    def skip_chip_orbits(_cycles, _touched) = nil
-  end
-end