badline 0.12.1 → 0.13.0

data/lib/badline/storage/disk_image.rb

@@ -42,12 +42,9 @@ module Badline
       # Whether the image was opened write-protected.
       def read_only? = @read_only
 
-      # What Storage.reopen needs to open the image again as it stands: its
-      # path, whether it is write-protected, and its bytes with the error
-      # table after them.
-      def save_setup(out)
-        out.int(storage_kind).string(File.expand_path(@path)).boolean(@read_only).blob(@bytes + @errors.to_a)
-      end
+      # The image as its file holds it, with its error table after the
+      # blocks.
+      def contents = @bytes + @errors.to_a
 
       # A LOAD reads only PRG files. An OPEN names the type it wants, or
       # takes the first file of any type with a nil `type`.

data/lib/badline/storage/g64_image.rb

@@ -5,7 +5,7 @@ module Badline
     # A .g64 image: a 1541 disk's flux as raw GCR, track by track, for the
     # true drive to read the way it reads a real disk, copy protection and
     # all. It has no file system of its own, so only the true drive
-    # (Drive1541::Disk.from_g64) can use it. A .g71 holds a 1571 disk the
+    # (Drives::Model1541::Disk.from_g64) can use it. A .g71 holds a 1571 disk the
     # same way, with "GCR-1571" for its signature and 168 half tracks,
     # the first side's 84 and then the second's.
     #
@@ -21,7 +21,7 @@ module Badline
     # A larger one is the offset of a speed map, two bits a byte, four
     # track bytes to a map byte, the first byte's in the top two bits, for
     # a track whose zone changes along it. The drive passes each byte
-    # under the head at its own zone's rate (Drive1541::Track).
+    # under the head at its own zone's rate (Drives::Model1541::Track).
     #
     # The drive writes a track at one zone, so a track written back takes
     # that zone as its speed entry. Writing it puts it in its own block,

data/lib/badline/storage/host_directory.rb

@@ -17,11 +17,6 @@ module Badline
         @path = path
       end
 
-      # What Storage.reopen needs to open the directory again.
-      def save_setup(out)
-        out.int(HOST_DIRECTORY).string(File.expand_path(@path))
-      end
-
       def read_file(name, **)
         entry = find(name)
         return unless entry

data/lib/badline/storage/t64.rb

@@ -20,14 +20,8 @@ module Badline
         raise FormatError, "Missing T64 signature" unless @bytes[0, 3] == SIGNATURE
       end
 
-      # The host file's path, as it was opened.
-      attr_reader :path
-
-      # What Storage.reopen needs to open the archive again: its path and
-      # its bytes.
-      def save_setup(out)
-        out.int(T64_ARCHIVE).string(File.expand_path(@path)).blob(@bytes)
-      end
+      # The host file's path, as it was opened, and its bytes.
+      attr_reader :path, :bytes
 
       def read_file(name, **)
         pattern = Storage.matcher(name)

data/lib/badline/storage/unavailable.rb

@@ -3,7 +3,7 @@
 module Badline
   module Storage
     # Stands in for a directory a detached restore leaves out
-    # (Snapshot::StateReader): it finds no files and refuses every write
+    # (Snapshot::StorageSetup): it finds no files and refuses every write
     # as a write-protected disk does.
     class Unavailable
       def path = ""

data/lib/badline/storage.rb

@@ -11,10 +11,6 @@ require "badline/storage/g64_image"
 require "badline/storage/t64"
 require "badline/storage/tap"
 require "badline/storage/crt_file"
-require "badline/storage/sid_file"
-require "badline/storage/hvsc"
-require "badline/storage/song_lengths"
-require "badline/storage/stil"
 require "badline/storage/unavailable"
 
 module Badline
@@ -36,29 +32,7 @@ module Badline
       end
     end
 
-    # The storage a snapshot's device 8 serves, by the number save_setup
-    # writes first.
-    HOST_DIRECTORY = 0
-    D64 = 1
-    D71 = 2
-    D81 = 3
-    T64_ARCHIVE = 4
-
     class << self
-      # Opens the storage a save_setup wrote: the same directory by its
-      # path, an archive with the bytes it held, or a disk image with the
-      # bytes it held, writes and all. A detached reader gets the image
-      # write-protected, and Unavailable for a directory.
-      def reopen(input)
-        kind = input.int
-        path = input.string
-        case kind
-        when HOST_DIRECTORY then input.detached? ? Unavailable.new : HostDirectory.new(path)
-        when T64_ARCHIVE then T64.new(path, bytes: input.blob)
-        else reopen_image(kind, path, input)
-        end
-      end
-
       # Folds shifted PETSCII letters to their ASCII equivalents.
       def ascii(bytes)
         bytes.map { |b| b.between?(0xc1, 0xda) ? b - 0x80 : b }.pack("C*")
@@ -83,17 +57,6 @@ module Badline
         [base.to_s, FILE_TYPES[type.to_s.strip[0]&.upcase]]
       end
 
-      def reopen_image(kind, path, input)
-        read_only = input.boolean? || input.detached?
-        bytes = input.blob
-        case kind
-        when D64 then D64Image.new(path, read_only:, bytes:)
-        when D71 then D71Image.new(path, read_only:, bytes:)
-        when D81 then D81Image.new(path, read_only:, bytes:)
-        else raise Snapshot::FormatError, "unknown storage #{kind} in the state"
-        end
-      end
-
       # CBM-style filename pattern: "*" and "?" wildcards, case-insensitive.
       # The DOS stops comparing at the first "*", so whatever follows it
       # is ignored.

data/lib/badline/support/c128_checkpoint.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Badline
+  module Support
+    # A Checkpoint of a C128, in either mode: a C64's components, with the
+    # whole 128K of RAM in place of bank 0 and the colour RAM bank the 8502
+    # sees, and besides them the VDC's registers and beam, the VDC's RAM, the
+    # MMU's registers and the Z80.
+    module C128Checkpoint
+      COMPONENTS = %w[cpu ram color_ram display vic cia1 cia2 sid vdc vdc_ram mmu z80].freeze
+
+      def self.take(machine)
+        Checkpoint.new(machine.cycles, [
+                         Checkpoint.fnv1a(Checkpoint.cpu_state(machine.cpu)),
+                         Checkpoint.fnv1a(Checkpoint.ram(machine.ram, 0x20000)),
+                         Checkpoint.fnv1a(Checkpoint.color_ram(machine.address_bus.color_ram, 0xd800)),
+                         Checkpoint.fnv1a(machine.vic.display),
+                         Checkpoint.fnv1a(Checkpoint.vic_state(machine.vic)),
+                         Checkpoint.fnv1a(Checkpoint.cia_state(machine.cia1)),
+                         Checkpoint.fnv1a(Checkpoint.cia_state(machine.cia2)),
+                         Checkpoint.fnv1a(Array.new(0x20) { |reg| machine.sid.register(reg) }),
+                         Checkpoint.fnv1a(machine.vdc.registers + [machine.vdc.frame]),
+                         Checkpoint.fnv1a(machine.vdc.ram),
+                         Checkpoint.fnv1a(machine.mmu.registers),
+                         Checkpoint.fnv1a(z80_state(machine.z80))
+                       ], COMPONENTS)
+      end
+
+      def self.parse(line) = Checkpoint.parse(line, COMPONENTS)
+
+      def self.z80_state(z80)
+        [z80.pc, z80.sp, z80.af, z80.bc, z80.de, z80.hl, z80.ix, z80.iy, z80.af_alt, z80.bc_alt, z80.de_alt,
+         z80.hl_alt, z80.i, z80.r, z80.im, flag(z80.iff1), flag(z80.iff2), flag(z80.halted), z80.cycles]
+      end
+
+      def self.flag(value) = value == true ? 1 : 0
+    end
+  end
+end

data/lib/badline/support/checkpoint.rb

@@ -0,0 +1,108 @@
+# frozen_string_literal: true
+
+module Badline
+  module Support
+    # A digest of the machine's state at one cycle, for comparing two runs of
+    # the same scenario, on two builds or two revisions. Each component is
+    # hashed on its own with 32-bit FNV-1a, so a mismatch names the part of the
+    # machine that went its own way. Nothing is read through a chip's bus
+    # interface, so taking a checkpoint leaves the machine as it was.
+    #
+    # Checkpoint.take digests a C64's components, COMPONENTS.
+    # Vic20Checkpoint and C128Checkpoint digest the other families', each
+    # with a list of its own, which a checkpoint carries as +components+.
+    #
+    # Colour RAM is digested as the four bits each cell stores: the upper
+    # nibble a CPU read sees comes off the open bus.
+    class Checkpoint
+      COMPONENTS = %w[cpu ram color_ram display vic cia1 cia2 sid].freeze
+
+      FNV_OFFSET = 0x811c9dc5
+      FNV_PRIME = 0x01000193
+
+      attr_reader :cycle, :digests, :components
+
+      class << self
+        def take(computer)
+          new(computer.cycles, [
+                fnv1a(cpu_state(computer.cpu)),
+                fnv1a(ram(computer.ram, 0x10000)),
+                fnv1a(color_ram(computer.address_bus.color_ram, 0xd800)),
+                fnv1a(computer.vic.display),
+                fnv1a(vic_state(computer.vic)),
+                fnv1a(cia_state(computer.cia1)),
+                fnv1a(cia_state(computer.cia2)),
+                fnv1a(Array.new(0x20) { |reg| computer.sid.register(reg) })
+              ])
+        end
+
+        # Reads a line written by #to_s, with a digest for each of
+        # `components`.
+        def parse(line, components = COMPONENTS)
+          fields = line.split
+          digests = components.map do |name|
+            field = fields.find { |f| f.start_with?("#{name}=") }
+            raise ArgumentError, "no #{name} digest in #{line.inspect}" unless field
+
+            field.split("=").last.to_i(16)
+          end
+          new(fields.first.to_i, digests, components)
+        end
+
+        def fnv1a(values)
+          hash = FNV_OFFSET
+          values.each { |value| hash = ((hash ^ (value & 0xffffffff)) * FNV_PRIME) & 0xffffffff }
+          hash
+        end
+
+        # The registers and cycle count of a 6502 or an 8502.
+        def cpu_state(cpu)
+          [cpu.program_counter, cpu.a, cpu.x, cpu.y, cpu.stack_pointer, cpu.p, cpu.cycles]
+        end
+
+        # The first `length` bytes of `memory`.
+        def ram(memory, length)
+          Array.new(length) { |addr| memory.peek(addr) }
+        end
+
+        # The 1K of colour RAM at `start`.
+        def color_ram(memory, start)
+          Array.new(0x400) { |offset| memory.nibble(start + offset) }
+        end
+
+        # A VIC-II's or a VIC-I's registers and beam position.
+        def vic_state(vic)
+          vic.register_file + [vic.rasterline, vic.column]
+        end
+
+        def cia_state(cia)
+          start = cia.start
+          [cia.peek(start), cia.peek(start + 1), cia.peek(start + 2), cia.peek(start + 3),
+           cia.timer_a, cia.timer_a_latch, cia.timer_b, cia.timer_b_latch, cia.serial.data,
+           cia.control_a.value, cia.control_b.value, cia.interrupt_status.value,
+           cia.interrupt_control.value] + cia.time_of_day.registers
+        end
+      end
+
+      def initialize(cycle, digests, components = COMPONENTS)
+        @cycle = cycle
+        @digests = digests
+        @components = components
+      end
+
+      # The components whose digests differ from `other`'s.
+      def differences(other)
+        components.each_index.reject { |i| digests[i] == other.digests[i] }.map { |i| components[i] }
+      end
+
+      def ==(other)
+        other.is_a?(Checkpoint) && cycle == other.cycle && components == other.components && digests == other.digests
+      end
+
+      def to_s
+        fields = components.each_index.map { |i| "#{components[i]}=#{digests[i].to_s(16).rjust(8, '0')}" }
+        "#{cycle} #{fields.join(' ')}"
+      end
+    end
+  end
+end

data/lib/badline/support/vic20_checkpoint.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+module Badline
+  module Support
+    # A Checkpoint of a VIC-20: its CPU, the 48K of RAM the bus decodes, the
+    # colour RAM, the VIC-I's display and registers, both VIAs and the
+    # sound. The sound's shift registers and noise LFSR move only while it
+    # records, so a run that wants them digested records it.
+    module Vic20Checkpoint
+      COMPONENTS = %w[cpu ram color_ram display vic via1 via2 sound].freeze
+
+      def self.take(machine)
+        Checkpoint.new(machine.cycles, [
+                         Checkpoint.fnv1a(Checkpoint.cpu_state(machine.cpu)),
+                         Checkpoint.fnv1a(Checkpoint.ram(machine.ram, 0xc000)),
+                         Checkpoint.fnv1a(Checkpoint.color_ram(machine.bus.color_ram, 0)),
+                         Checkpoint.fnv1a(machine.vic.display),
+                         Checkpoint.fnv1a(Checkpoint.vic_state(machine.vic)),
+                         Checkpoint.fnv1a(via_state(machine.via1)),
+                         Checkpoint.fnv1a(via_state(machine.via2)),
+                         Checkpoint.fnv1a(sound_state(machine.sound))
+                       ], COMPONENTS)
+      end
+
+      def self.parse(line) = Checkpoint.parse(line, COMPONENTS)
+
+      def self.via_state(via)
+        [via.port_a_output, via.port_b_output, via.timer1, via.timer1_latch, via.timer2,
+         via.shift_register.data, via.acr, via.pcr, via.interrupt_flags, via.interrupt_enable]
+      end
+
+      def self.sound_state(sound)
+        [sound.volume, sound.shift_register(0), sound.shift_register(1), sound.shift_register(2),
+         sound.shift_register(3), sound.lfsr]
+      end
+    end
+  end
+end

data/lib/badline/support.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+require "badline/support/checkpoint"
+require "badline/support/vic20_checkpoint"
+require "badline/support/c128_checkpoint"

data/lib/badline/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module Badline
-  VERSION = "0.12.1"
+  VERSION = "0.13.0"
 end

data/lib/badline/vic20/attachments.rb

@@ -4,11 +4,11 @@ module Badline
   class Vic20
     # What plugs into the VIC-20 besides its chips: cartridge ROM in the
     # expansion blocks, the disk device 8 serves through the KERNAL traps
-    # (Computer::KernalTraps), and a true 1541 or 1581 on the serial bus
-    # (Computer::TrueDrives).
+    # (C64::KernalTraps), and a true 1541 or 1581 on the serial bus
+    # (C64::TrueDrives).
     module Attachments
-      include Computer::TrueDrives
-      include Computer::KernalTraps
+      include C64::TrueDrives
+      include C64::KernalTraps
 
       # The cycle by which a 1541 switched on with the machine has run its
       # DOS's reset, the RAM test and the ROM checksum, and waits on the
@@ -46,7 +46,7 @@ module Badline
       # A 1581 plugged in, as a 1541 does, holds the machine's on_init
       # handlers back until its DOS has booted.
       def drive1581_attached
-        @init_threshold = [@init_threshold, Drive1581::BOOT_CYCLES].max if @cycles < @init_threshold
+        @init_threshold = [@init_threshold, Drives::Model1581::BOOT_CYCLES].max if @cycles < @init_threshold
       end
     end
   end

data/lib/badline/vic20/bus/saved_state.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module Badline
+  class Vic20
+    class Bus
+      # The bus's state for a snapshot.
+      module SavedState
+        # The RAM, the colour RAM, the byte each side's data lines hold and the
+        # cartridge's ROM chips, for a snapshot. The expansion blocks are how
+        # the machine was built.
+        def save_state(out)
+          out.marker("VIC20 BUS")
+          @ram.save_state(out)
+          out.blob(@color_ram.cells).int(@data).int(@video_data).int(@roms.length)
+          @roms.each do |rom|
+            out.int(rom.start)
+            rom.save_state(out)
+          end
+        end
+
+        def load_state(input)
+          input.marker("VIC20 BUS")
+          @ram.load_state(input)
+          input.blob_into(@color_ram.cells)
+          @data = input.int
+          @video_data = input.int
+          chips = Array.new(input.int) { [input.int, input.blob] }
+          @roms = []
+          chips.each { |chip| @roms << ROM.new(chip[1], length: chip[1].length, start: chip[0]) }
+          map_pages
+        end
+      end
+    end
+  end
+end

data/lib/badline/vic20/bus.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+require "badline/vic20/bus/saved_state"
+
 module Badline
   class Vic20
     # The CPU's bus:
@@ -27,6 +29,7 @@ module Badline
     # Writes to ROM and to empty spots go nowhere.
     class Bus
       include Addressable
+      include SavedState
 
       # The pages each expansion block covers, as [first page, count].
       BLOCKS = {
@@ -215,31 +218,6 @@ module Badline
         @ram.clear!(RAM_POWER_ON)
       end
 
-      # The RAM, the colour RAM, the byte each side's data lines hold and the
-      # cartridge's ROM chips, for a snapshot. The expansion blocks are how
-      # the machine was built.
-      def save_state(out)
-        out.marker("VIC20 BUS")
-        @ram.save_state(out)
-        out.blob(@color_ram.cells).int(@data).int(@video_data).int(@roms.length)
-        @roms.each do |rom|
-          out.int(rom.start)
-          rom.save_state(out)
-        end
-      end
-
-      def load_state(input)
-        input.marker("VIC20 BUS")
-        @ram.load_state(input)
-        input.blob_into(@color_ram.cells)
-        @data = input.int
-        @video_data = input.int
-        chips = Array.new(input.int) { [input.int, input.blob] }
-        @roms = []
-        chips.each { |chip| @roms << ROM.new(chip[1], length: chip[1].length, start: chip[0]) }
-        map_pages
-      end
-
       # Whether +block+ (BLOCKS) holds RAM.
       def ram?(block) = @blocks.include?(block)
 

data/lib/badline/vic20/cpu.rb

@@ -4,7 +4,7 @@ module Badline
   class Vic20
     # The VIC-20's 6502, on the Vic20::Bus.
     class CPU
-      include Badline::CPU::Core
+      include Badline::Chips::CPU::Core
     end
   end
 end

data/lib/badline/vic20/port_wiring.rb

@@ -16,12 +16,12 @@ module Badline
     # on VIA 1's PA6, its motor runs while VIA 1's CA2 is low, and VIA 2's
     # PB3 drives its write line, the same pin as a keyboard column.
     module PortWiring
-      # The lines the machine pulls, as IECBus host lines.
+      # The lines the machine pulls, as Drives::SerialBus host lines.
       def serial_lines
         lines = 0
-        lines |= IECBus::HOST_ATN_OUT if @via1.port_a_output.anybits?(0x80)
-        lines |= IECBus::HOST_CLK_OUT if @via2.ca2_output
-        lines |= IECBus::HOST_DATA_OUT if @via2.cb2_output
+        lines |= Drives::SerialBus::HOST_ATN_OUT if @via1.port_a_output.anybits?(0x80)
+        lines |= Drives::SerialBus::HOST_CLK_OUT if @via2.ca2_output
+        lines |= Drives::SerialBus::HOST_DATA_OUT if @via2.cb2_output
         lines
       end
 

data/lib/badline/vic20/saved_state.rb

@@ -1,23 +1,17 @@
 # frozen_string_literal: true
 
+require "badline/snapshot/vic20_setup"
+
 module Badline
   class Vic20
-    MARKER = "VIC20"
-
-    # The RAM expansion of the machine a State from #snapshot was taken
-    # of, a key of Bus::RAM_CONFIGURATIONS.
-    def self.setup(state)
-      input = Snapshot::StateReader.new(state)
-      input.marker(MARKER)
-      input.check_stamp
-      SavedState.read_ram(input)
-    end
+    # How the machine a State from #snapshot was taken of was built.
+    def self.setup(state) = Snapshot::Vic20Setup.from(state)
 
     # A new machine, built as the one a State from #snapshot was taken of,
     # at that state.
-    def self.restored(state) = new(ram: setup(state)).apply_state(state)
+    def self.restored(state) = setup(state).build.apply_state(state)
 
-    # The whole machine's state for a snapshot, as Computer's: the
+    # The whole machine's state for a snapshot, as C64's: the
     # machine's own latches, the bus with its RAM and cartridge ROM, the
     # VIC with its sound, both VIAs, the CPU, the datasette and its tape,
     # the disk device 8 serves through the traps, and a true 1541. The
@@ -26,14 +20,6 @@ module Badline
     # and callbacks, whether the display renders, whether the sound
     # records, and whether the datasette records.
     module SavedState
-      RAM_CONFIGURATIONS = Bus::RAM_CONFIGURATIONS.keys.freeze
-
-      def self.read_ram(input)
-        RAM_CONFIGURATIONS.fetch(input.int)
-      rescue IndexError
-        raise Snapshot::FormatError, "the state names a VIC-20 RAM expansion badline doesn't know"
-      end
-
       # How many more on_init handlers the machine a State was taken of had
       # yet to run than this one has. Nil until the machine is restored.
       attr_reader :init_handlers_lost
@@ -49,7 +35,7 @@ module Badline
       # Raises Snapshot::FormatError for a state of another machine or RAM
       # expansion.
       def restore(state)
-        check_ram(Vic20.setup(state))
+        check_setup(Vic20.setup(state))
         Vic20.restored(state)
         apply_state(state)
       end
@@ -64,8 +50,8 @@ module Badline
       end
 
       def save_state(out)
-        out.marker(MARKER).stamp
-        out.int(RAM_CONFIGURATIONS.index(@ram_configuration))
+        out.marker(Snapshot::Vic20Setup::MARKER).stamp
+        Snapshot::Vic20Setup.new(ram: @ram_configuration).write(out)
         out.int(@cycles).boolean(@nmi_asserted).boolean(!@pending_keys.nil?)
         out.ints(@pending_keys) if @pending_keys
         out.int(@cycles <= @init_threshold ? @init_handlers.length : 0)
@@ -76,15 +62,15 @@ module Badline
         @via2.save_state(out)
         @cpu.save_state(out)
         @datasette.save_state(out)
-        save_trap_drive(out)
+        save_trap_dos(out)
         save_drive1541(out)
         save_drive1581(out)
       end
 
       def load_state(input)
-        input.marker(MARKER)
+        input.marker(Snapshot::Vic20Setup::MARKER)
         input.check_stamp
-        check_ram(SavedState.read_ram(input))
+        check_setup(Snapshot::Vic20Setup.read(input))
         @cycles = input.int
         @nmi_asserted = input.boolean?
         @pending_keys = nil
@@ -98,7 +84,7 @@ module Badline
         @cpu.load_state(input)
         via_written
         @datasette.load_state(input)
-        load_trap_drive(input)
+        load_trap_dos(input)
         load_drive1541(input)
         load_drive1581(input)
       end
@@ -114,10 +100,10 @@ module Badline
         @drive1541.save_state(out)
       end
 
-      def check_ram(ram)
-        return if ram == @ram_configuration
+      def check_setup(setup)
+        return if setup.ram == @ram_configuration
 
-        raise Snapshot::FormatError, "the state is of a VIC-20 with #{ram} RAM, not #{@ram_configuration}"
+        raise Snapshot::FormatError, "the state is of a VIC-20 with #{setup.ram} RAM, not #{@ram_configuration}"
       end
     end
   end

data/lib/badline/vic20/user_via_ports.rb

@@ -38,8 +38,8 @@ module Badline
       def serial_inputs
         low = @serial_bus.low_lines
         value = 0x03
-        value &= ~0x01 if low.anybits?(IECBus::CLK)
-        value &= ~0x02 if low.anybits?(IECBus::DATA)
+        value &= ~0x01 if low.anybits?(Drives::SerialBus::CLK)
+        value &= ~0x02 if low.anybits?(Drives::SerialBus::DATA)
         value
       end
     end

data/lib/badline/vic20.rb

@@ -6,8 +6,8 @@ require "badline/vic20/cpu"
 require "badline/vic20/keyboard_via_ports"
 require "badline/vic20/port_wiring"
 require "badline/vic20/user_via_ports"
-require "badline/vic20/vic"
-require "badline/vic20/sound"
+require "badline/chips/vic_i"
+require "badline/chips/vic_i/sound"
 require "badline/vic20/saved_state"
 
 module Badline
@@ -36,6 +36,11 @@ module Badline
 
     def ram = @bus.ram
 
+    # Reads and writes memory as the CPU sees it, through the bus.
+    def peek(addr) = @bus.peek(addr)
+
+    def poke(addr, value) = @bus.poke(addr, value)
+
     def family = :vic20
 
     # The one control port's joystick, which the front end's second
@@ -48,26 +53,26 @@ module Badline
     # +ram+ names the RAM expansion, one of Bus::RAM_CONFIGURATIONS.
     def initialize(ram: :unexpanded, debug: false)
       @ram_configuration = ram
-      @vic = VIC.new
-      @keyboard = Keyboard.new(matrix: KeyboardVIAPorts::MATRIX)
-      @joystick1 = Joystick.new
-      @iec_bus = IECBus.new
-      @datasette = Datasette.new
-      @via1 = VIA.new(start: 0x9000, peripheral: UserVIAPorts.new(joystick: @joystick1, serial_bus: @iec_bus,
-                                                                  datasette: @datasette))
+      @vic = Chips::VICI.new
+      @keyboard = Input::Keyboard.new(matrix: KeyboardVIAPorts::MATRIX)
+      @joystick1 = Input::Joystick.new
+      @iec_bus = Drives::SerialBus.new
+      @datasette = Drives::Datasette.new
+      @via1 = Chips::VIA.new(start: 0x9000, peripheral: UserVIAPorts.new(joystick: @joystick1, serial_bus: @iec_bus,
+                                                                         datasette: @datasette))
       keyboard_ports = KeyboardVIAPorts.new(keyboard: @keyboard, joystick: @joystick1)
-      @via2 = VIA.new(start: 0x9000, peripheral: keyboard_ports)
+      @via2 = Chips::VIA.new(start: 0x9000, peripheral: keyboard_ports)
       keyboard_ports.connect(@via2)
       @bus = Bus.new(vic: @vic, via1: @via1, via2: @via2, blocks: Bus::RAM_CONFIGURATIONS.fetch(ram))
       @vic.connect(@bus)
       @cpu = CPU.new(@bus, debug:)
       @cycles = 0
-      @sound = Sound.new(self, @vic.profile.clock_hz)
+      @sound = Chips::VICI::Sound.new(self, @vic.profile.clock_hz)
       @vic.sound = @sound
       @nmi_asserted = false
       @init_handlers = []
       @pending_keys = nil
-      @drive = nil
+      @dos = nil
       @serial_trap = nil
       @save_trap = nil
       @capture_output = nil
@@ -111,7 +116,7 @@ module Badline
     # xvic draws them.
     def timing
       profile = @vic.profile
-      width = profile.cycles_per_line * VIC::PIXELS_PER_CYCLE
+      width = profile.cycles_per_line * Chips::VICI::PIXELS_PER_CYCLE
       blanked = profile.blanked_lines
       Timing.new(clock_hz: profile.clock_hz, cycles_per_line: profile.cycles_per_line,
                  lines_per_frame: profile.lines_per_frame,
@@ -148,7 +153,7 @@ module Badline
       @via1.reset!
       @via2.reset!
       via_written
-      @drive&.reset!
+      @dos&.reset!
       @drive1541&.reset!
       @drive1581&.reset!
       @nmi_asserted = false