badline 0.12.1 → 0.13.0

data/lib/badline/chips/cpu/instruction_set/flag.rb

@@ -0,0 +1,67 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Flag
+          # Clear carry flag.
+          #
+          # Opcodes:
+          #   $18 - implied - 2 cycles
+          def clc(_addr, _value)
+            status.carry = false
+          end
+
+          # Clear decimal mode flag.
+          #
+          # Opcodes:
+          #   $D8 - implied - 2 cycles
+          def cld(_addr, _value)
+            status.decimal = false
+          end
+
+          # Clear interrupt disable flag.
+          #
+          # Opcodes:
+          #   $58 - implied - 2 cycles
+          def cli(_addr, _value)
+            status.interrupt = false
+          end
+
+          # Clear overflow flag.
+          #
+          # Opcodes:
+          #   $B8 - implied - 2 cycles
+          def clv(_addr, _value)
+            status.overflow = false
+          end
+
+          # Set carry flag.
+          #
+          # Opcodes:
+          #   $38 - implied - 2 cycles
+          def sec(_addr, _value)
+            status.carry = true
+          end
+
+          # Set decimal mode flag.
+          #
+          # Opcodes:
+          #   $F8 - implied - 2 cycles
+          def sed(_addr, _value)
+            status.decimal = true
+          end
+
+          # Set interrupt disable flag.
+          #
+          # Opcodes:
+          #   $78 - implied - 2 cycles
+          def sei(_addr, _value)
+            status.interrupt = true
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/illegal.rb

@@ -0,0 +1,274 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        # Illegal opcodes
+        module Illegal
+          # Combination of AND and LSR.
+          #
+          # Opcodes:
+          #   $4B - immediate - 2 cycles
+          def alr(_addr, value)
+            @a &= value
+            status.carry = @a[0]
+            @a = (@a >> 1) & 0xff
+            update_number_flags(@a)
+          end
+
+          # Combination of AND where carry is set to bit 7 of result.
+          #
+          # Opcodes:
+          #   $0B, $2B - immediate - 2 cycles
+          def anc(addr, value)
+            self.and(addr, value)
+            status.carry = status.negative
+          end
+
+          # Unstable instruction. AND's value with A|magic_const and X.
+          # Magic constant varies by CPU. A VIC stall between the opcode and
+          # operand fetches clears its bits 0 and 4.
+          #
+          # Opcodes:
+          #   $8B - immediate - 2 cycles
+          def ane(_addr, value)
+            magic_const = stalled_before_this_cycle? ? @ane_constant & 0xee : @ane_constant
+            @a = (a | magic_const) & x & value
+            update_number_flags(@a)
+          end
+
+          # Combination of AND and ROR.
+          #
+          # Opcodes:
+          #   $6B - immediate - 2 cycles
+          def arr(_addr, value)
+            tmp = a & value
+            result = (tmp >> 1) | (status.carry? ? 0x80 : 0)
+            status.zero = result.zero?
+            status.negative = status.carry
+
+            if status.decimal?
+              status.overflow = (result ^ tmp).anybits?(0x40)
+
+              # Low nibble
+              result = (result & 0xf0) | ((result + 0x06) & 0x0f) if ((tmp & 0x0f) + (tmp & 0x01)) > 0x05
+
+              # High nibble + carry
+              if ((tmp & 0xf0) + (tmp & 0x10)) > 0x50
+                result = (result & 0x0f) | ((result + 0x60) & 0xf0)
+                status.carry = true
+              else
+                status.carry = false
+              end
+            else
+              status.carry = tmp[7] == 1
+              status.overflow = tmp[7] ^ tmp[6]
+            end
+
+            @a = result
+          end
+
+          # Combination of DEC and CMP operations.
+          #
+          # Opcodes:
+          #   $C3 - indirect_x - 8 cycles
+          #   $C7 - zeropage   - 5 cycles
+          #   $CF - absolute   - 6 cycles
+          #   $D3 - indirect_y - 8 cycles
+          #   $D7 - zeropage_x - 6 cycles
+          #   $DB - absolute_y - 7 cycles
+          #   $DF - absolute_x - 7 cycles
+          def dcp(addr, value)
+            cmp(addr, dec(addr, value))
+          end
+
+          # Combination of INC and SBC operations.
+          #
+          # Opcodes:
+          #   $E3 - indirect_x - 8 cycles
+          #   $E7 - zeropage   - 5 cycles
+          #   $EF - absolute   - 6 cycles
+          #   $F3 - indirect_y - 8 cycles
+          #   $F7 - zeropage_x - 6 cycles
+          #   $FB - absolute_y - 7 cycles
+          #   $FF - absolute_x - 7 cycles
+          def isc(addr, value)
+            sbc(addr, inc(addr, value))
+          end
+
+          # Loads A and S with value AND stack pointer.
+          #
+          # Opcodes:
+          #   $BB - absolute_y - 4 cycles
+          def las(_addr, value)
+            @a = @x = @stack_pointer = value & stack_pointer
+            update_number_flags(@a)
+          end
+
+          # Combination of LDA and LDX with same value.
+          #
+          # Opcodes:
+          #   $A3 - indirect_x - 6 cycles
+          #   $A7 - zeropage   - 3 cycles
+          #   $AF - absolute   - 4 cycles
+          #   $B3 - indirect_y - 5+ cycles
+          #   $B7 - zeropage_y - 4 cycles
+          #   $BF - absolute_y - 4+ cycles
+          def lax(_addr, value)
+            @a = @x = value
+
+            update_number_flags(@a)
+          end
+
+          # Unstable immediate form of LAX. Loads A and X with
+          # (A | magic_const) AND value. Magic constant varies by CPU.
+          #
+          # Opcodes:
+          #   $AB - immediate - 2 cycles
+          def lxa(_addr, value)
+            magic_const = 0xee
+            @a = @x = (a | magic_const) & value
+            update_number_flags(@a)
+          end
+
+          # Special no-operation instruction that does not consume a CPU cycle,
+          # unlike the standard NOP. Used by some illegal opcodes.
+          #
+          # Opcodes:
+          #   $80, $82, $89, $C2, $E2 - immediate - 2 cycles
+          def nop_nocycle(_addr, _value); end
+
+          # Combination of ROL and AND operations.
+          #
+          # Opcodes:
+          #   $23 - indirect_x - 8 cycles
+          #   $27 - zeropage   - 5 cycles
+          #   $2F - absolute   - 6 cycles
+          #   $33 - indirect_y - 8 cycles
+          #   $37 - zeropage_x - 6 cycles
+          #   $3B - absolute_y - 7 cycles
+          #   $3F - absolute_x - 7 cycles
+          def rla(addr, value)
+            self.and(addr, rol(addr, value))
+          end
+
+          # Combination of ROR and ADC operations.
+          #
+          # Opcodes:
+          #   $63 - indirect_x - 8 cycles
+          #   $67 - zeropage   - 5 cycles
+          #   $6F - absolute   - 6 cycles
+          #   $73 - indirect_y - 8 cycles
+          #   $77 - zeropage_x - 6 cycles
+          #   $7B - absolute_y - 7 cycles
+          #   $7F - absolute_x - 7 cycles
+          def rra(addr, value)
+            adc(addr, ror(addr, value))
+          end
+
+          # Store A AND X.
+          #
+          # Opcodes:
+          #   $83 - indirect_x - 6 cycles
+          #   $87 - zeropage   - 3 cycles
+          #   $8F - absolute   - 4 cycles
+          #   $97 - zeropage_y - 4 cycles
+          def sax(addr, _value)
+            write_byte(addr, @a & @x)
+          end
+
+          # AND X register with accumulator and subtract value.
+          #
+          # Opcodes:
+          #   $CB - immediate - 2 cycles
+          def sbx(_addr, value)
+            result = (@x & @a) - value
+            status.carry = result >= 0
+            @x = result & 0xff
+            update_number_flags(@x)
+          end
+
+          # Stores A AND X AND (high byte of base address + 1) at addr.
+          #
+          # Opcodes:
+          #   $93 - indirect_y - 6 cycles
+          #   $9F - absolute_y - 5 cycles
+          def sha(addr, _value)
+            store_high_and(a & x, addr)
+          end
+
+          # Stores X AND (high byte of base address + 1) at addr.
+          #
+          # Opcodes:
+          #   $9E - absolute_y - 5 cycles
+          def shx(addr, _value)
+            store_high_and(x, addr)
+          end
+
+          # Stores Y AND (high byte of base address + 1) at addr.
+          #
+          # Opcodes:
+          #   $9C - absolute_x - 5 cycles
+          def shy(addr, _value)
+            store_high_and(y, addr)
+          end
+
+          # Combination of ASL and ORA operations.
+          #
+          # Opcodes:
+          #   $03 - indirect_x - 8 cycles
+          #   $07 - zeropage   - 5 cycles
+          #   $0F - absolute   - 6 cycles
+          #   $13 - indirect_y - 8 cycles
+          #   $17 - zeropage_x - 6 cycles
+          #   $1B - absolute_y - 7 cycles
+          #   $1F - absolute_x - 7 cycles
+          def slo(addr, value)
+            ora(addr, asl(addr, value))
+          end
+
+          # Combination of LSR and EOR operations.
+          #
+          # Opcodes:
+          #   $43 - indirect_x - 8 cycles
+          #   $47 - zeropage   - 5 cycles
+          #   $4F - absolute   - 6 cycles
+          #   $53 - indirect_y - 8 cycles
+          #   $57 - zeropage_x - 6 cycles
+          #   $5B - absolute_y - 7 cycles
+          #   $5F - absolute_x - 7 cycles
+          def sre(addr, value)
+            eor(addr, lsr(addr, value))
+          end
+
+          # Stores A AND X in SP, then stores SP AND (high byte of base + 1) at
+          # addr.
+          #
+          # Opcodes:
+          #   $9B - absolute_y - 5 cycles
+          def tas(addr, _value)
+            @stack_pointer = @a & @x
+            store_high_and(stack_pointer, addr)
+          end
+
+          private
+
+          # A VIC stall right before the dummy read, the second-to-last cycle,
+          # drops the & (H+1) from the stored value but not from the high byte
+          # of a page-crossing target.
+          def store_high_and(register, addr)
+            base_high = if boundary_crossed
+                          (high_byte(addr) - 1) & 0xff
+                        else
+                          high_byte(addr)
+                        end
+            result = register & ((base_high + 1) & 0xff)
+            target = boundary_crossed ? uint16(low_byte(addr), result) : addr
+            write_byte(target, stalled_before_previous_cycle? ? register : result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/inc_dec.rb

@@ -0,0 +1,73 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module IncDec
+          # Decrements memory location by one.
+          #
+          # Opcodes:
+          #   $C6 - zeropage   - 5 cycles
+          #   $CE - absolute   - 6 cycles
+          #   $D6 - zeropage_x - 6 cycles
+          #   $DE - absolute_x - 7 cycles
+          def dec(addr, value)
+            result = (value - 1) & 0xff
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Decrements X register by one.
+          #
+          # Opcodes:
+          #   $CA - implied - 2 cycles
+          def dex(_addr, _value)
+            @x = (@x - 1) & 0xff
+            update_number_flags(@x)
+          end
+
+          # Decrements Y register by one.
+          #
+          # Opcodes:
+          #   $88 - implied - 2 cycles
+          def dey(_addr, _value)
+            @y = (@y - 1) & 0xff
+            update_number_flags(@y)
+          end
+
+          # Increments memory location by one.
+          #
+          # Opcodes:
+          #   $E6 - zeropage   - 5 cycles
+          #   $EE - absolute   - 6 cycles
+          #   $F6 - zeropage_x - 6 cycles
+          #   $FE - absolute_x - 7 cycles
+          def inc(addr, value)
+            result = (value + 1) & 0xff
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Increments X register by one.
+          #
+          # Opcodes:
+          #   $E8 - implied - 2 cycles
+          def inx(_addr, _value)
+            @x = (@x + 1) & 0xff
+            update_number_flags(@x)
+          end
+
+          # Increments Y register by one.
+          #
+          # Opcodes:
+          #   $C8 - implied - 2 cycles
+          def iny(_addr, _value)
+            @y = (@y + 1) & 0xff
+            update_number_flags(@y)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/stack.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Stack
+          # Push accumulator onto the stack.
+          #
+          # Opcodes:
+          #   $48 - implied - 3 cycles
+          def pha(_addr, _value)
+            stack_push(@a)
+          end
+
+          # Push processor status onto the stack.
+          #
+          # Opcodes:
+          #   $08 - implied - 3 cycles
+          def php(_addr, _value)
+            stack_push(p | 0b00010000)
+          end
+
+          # Pull accumulator from stack.
+          #
+          # Opcodes:
+          #   $68 - implied - 4 cycles
+          def pla(_addr, _value)
+            @a = stack_pull
+            update_number_flags(@a)
+          end
+
+          # Pull processor status from stack.
+          #
+          # Opcodes:
+          #   $28 - implied - 4 cycles
+          def plp(_addr, _value)
+            status.value = stack_pull & 0b11101111
+          end
+
+          private
+
+          def stack_pull
+            @stack_pointer = (@stack_pointer + 1) & 0xff
+            @memory.peek(stack_address)
+          end
+
+          def stack_push(value)
+            write_byte(stack_address, value)
+            @stack_pointer = (@stack_pointer - 1) & 0xff
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/transfer.rb

@@ -0,0 +1,141 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Transfer
+          # +begin_src ruby
+          # Load accumulator with memory.
+          #
+          # Opcodes:
+          #   $A1 - indirect_x - 6 cycles
+          #   $A5 - zeropage   - 3 cycles
+          #   $A9 - immediate  - 2 cycles
+          #   $AD - absolute   - 4 cycles
+          #   $B1 - indirect_y - 5+ cycles
+          #   $B5 - zeropage_x - 4 cycles
+          #   $B9 - absolute_y - 4+ cycles
+          #   $BD - absolute_x - 4+ cycles
+          def lda(_addr, value)
+            @a = value
+            update_number_flags(@a)
+          end
+
+          # Load X register with memory.
+          #
+          # Opcodes:
+          #   $A2 - immediate  - 2 cycles
+          #   $A6 - zeropage   - 3 cycles
+          #   $AE - absolute   - 4 cycles
+          #   $B6 - zeropage_y - 4 cycles
+          #   $BE - absolute_y - 4+ cycles
+          def ldx(_addr, value)
+            @x = value
+            update_number_flags(@x)
+          end
+
+          # Load Y register with memory.
+          #
+          # Opcodes:
+          #   $A0 - immediate  - 2 cycles
+          #   $A4 - zeropage   - 3 cycles
+          #   $AC - absolute   - 4 cycles
+          #   $B4 - zeropage_x - 4 cycles
+          #   $BC - absolute_x - 4+ cycles
+          def ldy(_addr, value)
+            @y = value
+            update_number_flags(@y)
+          end
+
+          # Store accumulator in memory.
+          #
+          # Opcodes:
+          #   $81 - indirect_x - 6 cycles
+          #   $85 - zeropage   - 3 cycles
+          #   $8D - absolute   - 4 cycles
+          #   $91 - indirect_y - 6 cycles
+          #   $95 - zeropage_x - 4 cycles
+          #   $99 - absolute_y - 5 cycles
+          #   $9D - absolute_x - 5 cycles
+          def sta(addr, _value)
+            write_byte(addr, @a)
+          end
+
+          # Store X register in memory.
+          #
+          # Opcodes:
+          #   $86 - zeropage   - 3 cycles
+          #   $8E - absolute   - 4 cycles
+          #   $96 - zeropage_y - 4 cycles
+          def stx(addr, _value)
+            write_byte(addr, @x)
+          end
+
+          # Store Y register in memory.
+          #
+          # Opcodes:
+          #   $84 - zeropage   - 3 cycles
+          #   $8C - absolute   - 4 cycles
+          #   $94 - zeropage_x - 4 cycles
+          def sty(addr, _value)
+            write_byte(addr, @y)
+          end
+
+          # Transfer accumulator to X register.
+          #
+          # Opcodes:
+          #   $AA - implied - 2 cycles
+          def tax(_addr, _value)
+            @x = a
+            update_number_flags(@x)
+          end
+
+          # Transfer accumulator to Y register.
+          #
+          # Opcodes:
+          #   $A8 - implied - 2 cycles
+          def tay(_addr, _value)
+            @y = a
+            update_number_flags(@y)
+          end
+
+          # Transfer stack pointer to X register.
+          #
+          # Opcodes:
+          #   $BA - implied - 2 cycles
+          def tsx(_addr, _value)
+            @x = stack_pointer
+            update_number_flags(@x)
+          end
+
+          # Transfer X register to accumulator.
+          #
+          # Opcodes:
+          #   $8A - implied - 2 cycles
+          def txa(_addr, _operand)
+            @a = x
+            update_number_flags(@a)
+          end
+
+          # Transfer X register to stack pointer.
+          #
+          # Opcodes:
+          #   $9A - implied - 2 cycles
+          def txs(_addr, _operand)
+            @stack_pointer = x
+          end
+
+          # Transfer Y register to accumulator.
+          #
+          # Opcodes:
+          #   $98 - implied - 2 cycles
+          def tya(_addr, _operand)
+            @a = y
+            update_number_flags(@a)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+require "badline/chips/cpu/instruction_set/arithmetic"
+require "badline/chips/cpu/instruction_set/bitwise"
+require "badline/chips/cpu/instruction_set/branch"
+require "badline/chips/cpu/instruction_set/inc_dec"
+require "badline/chips/cpu/instruction_set/flag"
+require "badline/chips/cpu/instruction_set/illegal"
+require "badline/chips/cpu/instruction_set/stack"
+require "badline/chips/cpu/instruction_set/transfer"
+
+module Badline
+  module Chips
+    class CPU
+      # http://www.6502.org/tutorials/6502opcodes.html
+      # http://www.e-tradition.net/bytes/6502/6502_instruction_set.html
+      module InstructionSet
+        include InstructionSet::Arithmetic
+        include InstructionSet::Bitwise
+        include InstructionSet::Branch
+        include InstructionSet::IncDec
+        include InstructionSet::Flag
+        include InstructionSet::Illegal
+        include InstructionSet::Stack
+        include InstructionSet::Transfer
+
+        # No operation. The illegal forms with an operand still read it, in
+        # the steps before this is called.
+        #
+        # Opcodes:
+        #   $EA                          - implied    - 2 cycles
+        #   $04, $44, $64                - zeropage   - 3 cycles  (illegal)
+        #   $14, $34, $54, $74, $D4, $F4 - zeropage_x - 4 cycles  (illegal)
+        #   $0C                          - absolute   - 4 cycles  (illegal)
+        #   $1C, $3C, $5C, $7C, $DC, $FC - absolute_x - 4+ cycles (illegal)
+        #   $1A, $3A, $5A, $7A, $DA, $FA - implied    - 2 cycles  (illegal)
+        def nop(_addr, _value); end
+
+        private
+
+        def update_number_flags(value)
+          status.zero = value.zero?
+          status.negative = value & 0x80 != 0
+          value
+        end
+
+        # Stores a read-modify-write result. For memory, the write happens in
+        # the steps that follow (see Operations#op_rmw_read).
+        def write_modified(addr, result)
+          if addr == :accumulator
+            @a = result
+          else
+            @rmw_result = result
+          end
+        end
+      end
+    end
+  end
+end