badline 0.10.1 → 0.11.1

data/lib/badline/drive1541/mechanism.rb

@@ -2,6 +2,7 @@
 
 require "badline/drive1541/rotation"
 require "badline/drive1541/mechanism_state"
+require "badline/drive1541/byte_ready"
 
 module Badline
   class Drive1541
@@ -26,7 +27,7 @@ module Badline
     # reads it, and it holds the bit counter at zero, so the first 0 bit
     # after it starts a byte. Every eighth bit after that is BYTE READY,
     # which pulls VIA 2's CA1 low until the next bit and reaches the CPU's
-    # SO pin (see Drive1541#byte_ready!).
+    # SO pin (see byte_ready!).
     #
     # CB2 low selects write mode, where SYNC detection and the flux are
     # off and the clock runs on at the selected rate. At each BYTE READY
@@ -64,9 +65,13 @@ module Badline
     # becomes track 1's, so the DOS's bump leaves the head on track 1 in
     # line with the phase it ends on, and its first step in reaches the
     # half track after it.
+    #
+    # The 1571's stepper is lined up so that phase 0 holds track 1, where
+    # its track 0 sensor looks for the head (Mechanism.new's +slip+).
     class Mechanism
       include Rotation
       include MechanismState
+      include ByteReady
 
       MOTOR = 0x04
       LED = 0x08
@@ -81,11 +86,15 @@ module Badline
 
       attr_reader :disk, :half_track, :zone
 
-      def initialize(drive)
-        @drive = drive
+      # +slip+ is the stepper's phase offset at power-on: 0, where each half
+      # track's phase is the low two bits of its number, or 2 for track 1
+      # on phase 0.
+      def initialize(slip: 0)
+        @via = nil
+        @so_pending = false
         @disk = nil
         @half_track = START_HALF_TRACK
-        @slip = 0
+        @slip = slip
         @motor = false
         @led = false
         @zone = 0
@@ -98,10 +107,30 @@ module Badline
         @bits = 0
         @sync = false
         @byte_ready = false
+        @byte_latched = false
         @writing = false
         @write_shift = 0
         @write_gate = false
         @protected = false
+        @side_base = 0
+        @cycle_ticks = CYCLE
+        load_track
+      end
+
+      # The drive's clock rate: the disk turns on by fewer ticks each
+      # cycle at 2 MHz.
+      def clock_hz=(clock_hz)
+        @cycle_ticks = CYCLE * Drive1541::CLOCK_HZ / clock_hz
+      end
+
+      # The head that reads, 0 or 1, on a drive with two (Disk::SIDE).
+      def side = @side_base.zero? ? 0 : 1
+
+      def side=(side)
+        side_base = side * Disk::SIDE
+        return if side_base == @side_base
+
+        @side_base = side_base
         load_track
       end
 
@@ -117,10 +146,10 @@ module Badline
       # LED, the zone and the clock's rate, the stepper, write mode and
       # where a write starts, and the track and cell under the head. The
       # rest moves only while the motor turns, or as a disk goes in (see
-      # Drive1541::Idle).
+      # Drive::Idle).
       def idle_state
-        [@motor, @led, @zone, @clock, @half_track, @slip, @disk, @track, @index, @mask, @cell_end, @time,
-         @writing, @write_index, @sync]
+        [@motor, @led, @zone, @clock, @half_track, @slip, @side_base, @disk, @track, @index, @mask, @cell_end,
+         @time, @writing, @write_index, @sync, @byte_latched]
       end
 
       # Puts a Disk in, or takes it out with nil, flushing the disk that
@@ -178,7 +207,7 @@ module Badline
       def read_bit(one)
         if @byte_ready
           @byte_ready = false
-          @drive.byte_ready_ended!
+          byte_ready_ended!
         end
         @shift = ((@shift << 1) & 0x3fe) | (one ? 1 : 0)
         if one
@@ -197,7 +226,7 @@ module Badline
       def write_bit(at)
         if @byte_ready
           @byte_ready = false
-          @drive.byte_ready_ended!
+          byte_ready_ended!
         end
         one = @write_shift.anybits?(0x80)
         @write_shift = (@write_shift << 1) & 0xff
@@ -227,10 +256,11 @@ module Badline
       # changed: a half track without data gets a blank track, and a track
       # written at another rate is laid out again at this one.
       def track_written(at)
-        track = @disk.writable_track(@half_track, @zone)
-        @disk.write(@half_track, track.relaid(@zone)) unless track.written_at?(@zone)
+        surface = self.surface
+        track = @disk.writable_track(surface, @zone)
+        @disk.write(surface, track.relaid(@zone)) unless track.written_at?(@zone)
         load_track(at)
-        @disk.written(@half_track)
+        @disk.written(surface)
         @track_written = true
       end
 
@@ -246,9 +276,9 @@ module Badline
         return unless @bits == 8
 
         @bits = 0
-        @write_shift = @writing ? @drive.via2.port_a_output : @shift & 0xff
+        @write_shift = @writing ? @via.port_a_output : @shift & 0xff
         @byte_ready = true
-        @drive.byte_ready!
+        byte_ready!
       end
 
       # The stepper's rotor turns with the head, a phase to each half
@@ -267,6 +297,10 @@ module Badline
         end
       end
 
+      # The half track under the head that reads, numbered on the disk
+      # (see Disk::SIDE).
+      def surface = @half_track + @side_base
+
       def seek(half_track)
         half_track = half_track.clamp(MIN_HALF_TRACK, Disk::MAX_HALF_TRACK)
         return if half_track == @half_track

data/lib/badline/drive1541/mechanism_state.rb

@@ -10,11 +10,10 @@ module Badline
       def save_state(out)
         out.boolean(!@disk.nil?)
         @disk&.save_state(out)
-        [@half_track, @slip, @zone, @clock, @time, @clock_at, @clocks, @shift, @ones, @bits, @write_shift,
+        [@half_track, @slip, @side_base, @zone, @clock, @time, @clock_at, @clocks, @shift, @ones, @bits, @write_shift,
          @index, @mask, @cell_end, @width, @next].each { |value| out.int(value) }
-        [@motor, @led, @sync, @byte_ready, @writing, @write_gate, @protected, @track_written].each do |flag|
-          out.boolean(flag)
-        end
+        [@motor, @led, @sync, @byte_ready, @byte_latched, @writing, @write_gate, @protected,
+         @track_written].each { |flag| out.boolean(flag) }
         out.optional_int(@write_index)
       end
 
@@ -36,6 +35,7 @@ module Badline
       def load_head(input)
         @half_track = input.int
         @slip = input.int
+        @side_base = input.int
         @zone = input.int
         @clock = input.int
         @time = input.int
@@ -57,6 +57,7 @@ module Badline
         @led = input.boolean?
         @sync = input.boolean?
         @byte_ready = input.boolean?
+        @byte_latched = input.boolean?
         @writing = input.boolean?
         @write_gate = input.boolean?
         @protected = input.boolean?

data/lib/badline/drive1541/rotation.rb

@@ -30,12 +30,12 @@ module Badline
       BLANK = Track.new(Array.new(Disk::TRACK_LENGTHS[0], 0).freeze, 0)
 
       # One drive cycle: nothing with the motor off, and otherwise the
-      # disk turns on by 16 ticks, through whatever cells and clocks fall
-      # in them.
+      # disk turns on by a cycle's ticks, 16 at 1 MHz and 8 at 2 MHz,
+      # through whatever cells and clocks fall in them.
       def cycle!
         return unless @motor
 
-        @time += CYCLE
+        @time += @cycle_ticks
         pass_time if @time >= @next
       end
 
@@ -95,7 +95,7 @@ module Badline
       # The track under the head and its layout, leaving the head's place
       # on it as it stands.
       def head_on_track
-        @track = @disk&.track(@half_track) || BLANK
+        @track = @disk&.track(surface) || BLANK
         @bytes = @track.bytes
         @widths = @track.widths
         @length = @track.length
@@ -105,7 +105,7 @@ module Badline
       # The track under the head, from the cell that's under it +time+
       # into the turn.
       def load_track(time = @time)
-        @track = @disk&.track(@half_track) || BLANK
+        @track = @disk&.track(surface) || BLANK
         @bytes = @track.bytes
         @widths = @track.widths
         @length = @track.length

data/lib/badline/drive1541/serial_port.rb

@@ -3,72 +3,16 @@
 module Badline
   class Drive1541
     # What VIA 1's ports read from outside the chip. Port B carries the
-    # serial bus inputs and the device number jumpers; port A goes to the
-    # unused parallel header and floats high.
-    #
-    # DATA IN (PB0), CLK IN (PB2) and ATN IN (PB7) come through inverters,
-    # so a released line reads 0 and a pulled one 1. The jumpers on PB5 and
-    # PB6 pull a line low when closed, and both closed make device 8.
-    #
-    # The drive sees the C64's side of the bus a host cycle late. The C64's
-    # CIA changes its pins at the end of the cycle that writes them, and
-    # the drive's VIA samples its own late in each of its cycles, so a
-    # drive cycle that runs alongside the write reads the lines from
-    # before it. The drive runs after the C64 in each host cycle (see
-    # Computer#cycle!), so the port reads the C64's lines as latch_host
-    # took them at the end of the last one. Fast loaders that time their
-    # transfer from an ATN edge, as VICE's drive tests do, depend on it.
+    # serial bus inputs and the device number jumpers (Drive::SerialLines);
+    # port A goes to the unused parallel header and floats high.
     class SerialPort
-      DATA_IN = 0x01
-      CLK_IN = 0x04
-      ATN_IN = 0x80
-      SERIAL_INPUTS = DATA_IN | CLK_IN | ATN_IN
-      JUMPERS = 0b0110_0000
-
-      attr_reader :bus
+      include Drive::SerialLines
 
       def initialize(device: 8, bus: IECBus.new)
-        @port_b = (0xff & ~(SERIAL_INPUTS | JUMPERS)) | (((device - 8) & 0x03) << 5)
-        @host = 0
-        self.bus = bus
-      end
-
-      def bus=(bus)
-        @bus = bus
-        latch_host
-      end
-
-      # Takes the C64's lines as the machine last pushed them into the bus,
-      # for the drive cycles of the next host cycle.
-      def latch_host
-        @host = @bus.host_lines
-      end
-
-      # The C64's lines as last latched. The jumpers and the bus are the
-      # drive's wiring.
-      def save_state(out)
-        out.int(@host)
+        init_serial_lines(device, bus)
       end
 
-      def load_state(input)
-        @host = input.int
-      end
-
-      # Whether the C64 has moved ATN since the last latch_host.
-      def atn_moved? = (@bus.host_lines ^ @host).anybits?(IECBus::HOST_ATN_OUT)
-
-      def atn_low? = @bus.atn_low?(@host)
-
       def read_a(_lines) = 0xff
-
-      def read_b(_lines)
-        low = @bus.low_lines(@host)
-        value = @port_b
-        value |= DATA_IN if low.anybits?(IECBus::DATA)
-        value |= CLK_IN if low.anybits?(IECBus::CLK)
-        value |= ATN_IN if low.anybits?(IECBus::ATN)
-        value
-      end
     end
   end
 end

data/lib/badline/drive1541.rb

@@ -1,5 +1,6 @@
 # frozen_string_literal: true
 
+require "badline/drive"
 require "badline/drive1541/bus"
 require "badline/drive1541/cpu"
 require "badline/drive1541/serial_port"
@@ -8,75 +9,20 @@ require "badline/drive1541/track"
 require "badline/drive1541/disk"
 require "badline/drive1541/mechanism"
 require "badline/drive1541/disk_via"
-require "badline/drive1541/sleep"
-require "badline/drive1541/idle"
-require "badline/drive1541/orbit"
 
 module Badline
   # The 1541 disk drive as a machine of its own: a 6502 running the DOS
-  # ROM at 1 MHz, with 2 KB of RAM and two VIAs on its bus. VIA 1 faces
-  # the serial bus and VIA 2 the disk mechanism.
-  #
-  # The drive runs on its own crystal, so it clocks against the host's
-  # clock through a fractional accumulator: each host cycle adds 1 MHz
-  # worth of phase, and every whole host period in it runs a drive cycle.
-  # Against the PAL C64's 985,248 Hz that's one drive cycle per host cycle
-  # and a second one about every 67. The host sets its clock on attaching
-  # the drive, and until then the drive runs one cycle per host cycle.
-  #
-  # VIA 2's port B runs the Mechanism, which reads a Disk put in with
-  # insert.
-  #
-  # While the DOS idles, host_cycle! skips the drive's cycles and catches
-  # up on them later, exactly (see Idle). The readers of the drive's parts
-  # catch up first, so they find the drive as running every cycle would
-  # have left it. Once the DOS's timer interrupts come round, the drive
-  # sleeps through them too (see Orbit).
+  # ROM at 1 MHz, with 2 KB of RAM and two VIAs on its bus. Drive::Core
+  # clocks it against the host and sleeps through the DOS's idle loop.
   class Drive1541
-    include Sleep
-    include Idle
-    include Orbit
+    include Drive::Core
 
     CLOCK_HZ = 1_000_000
 
-    attr_reader :device, :serial_bus
+    # Where the DOS 2.6 idle loop starts over (see Drive::Idle).
+    IDLE_LOOP = 0xebff
 
-    def cpu
-      settle!
-      @cpu
-    end
-
-    def bus
-      settle!
-      @bus
-    end
-
-    def via1
-      settle!
-      @via1
-    end
-
-    def via2
-      settle!
-      @via2
-    end
-
-    def mechanism
-      settle!
-      @mechanism
-    end
-
-    def cycles
-      settle!
-      @cycles
-    end
-
-    def ram = bus.ram
-
-    def host_clock_hz=(clock_hz)
-      settle!
-      @host_clock_hz = clock_hz
-    end
+    def model_name = "1541"
 
     # +rom+ covers $C000-$FFFF, and defaults to the DOS image in the ROM
     # path. +device+ is the number the jumpers on VIA 1's PB5 and PB6 set,
@@ -85,14 +31,15 @@ module Badline
       @device = device
       @serial_port = SerialPort.new(device:)
       @via1 = VIA.new(start: 0x1800, peripheral: @serial_port)
-      @mechanism = Mechanism.new(self)
+      @mechanism = Mechanism.new
       @via2 = DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
       @bus = Bus.new(rom: rom || ROM.load("dos1541.rom", 0xc000), via1: @via1, via2: @via2)
       @cpu = CPU.new(@bus, debug:)
+      @clock_hz = CLOCK_HZ
+      @idle_loop = IDLE_LOOP
       @host_clock_hz = host_clock_hz
       @phase = 0
       @cycles = 0
-      @so_pending = false
       @serial_bus = nil
       init_idle(debug)
       # CA1 powers up at the level of a released ATN, without an edge.
@@ -101,86 +48,6 @@ module Badline
       connect(IECBus.new)
     end
 
-    # Plugs the drive into a serial bus, leaving the one it was on. A drive
-    # starts out on a bus of its own, with nothing else on it.
-    def connect(serial_bus)
-      settle!
-      @serial_bus&.detach(self)
-      @serial_bus = serial_bus
-      @serial_port.bus = serial_bus
-      serial_bus.attach(self)
-      @via1.ca1 = @serial_port.atn_low?
-    end
-
-    # Puts a Disk in the drive (Disk.from_d64 makes one from an image).
-    # Nil takes the disk out.
-    def insert(disk)
-      settle!
-      @mechanism.insert(disk)
-    end
-
-    def disk = mechanism.disk
-
-    # Whether the LED is lit. Reading it leaves the drive asleep: the LED
-    # is the same at the end of every pass the drive sleeps through.
-    def led_on? = @mechanism.led_on?
-
-    # VIA 1's port B as it drives the serial bus. It holds still while the
-    # drive sleeps, so reading it leaves the drive asleep.
-    def serial_output = @via1.port_b_output
-
-    # Stores what the head wrote since the motor last stopped in the
-    # disk's image, as the motor stopping does.
-    def flush
-      settle!
-      @mechanism.flush
-    end
-
-    # The serial bus's RESET line reaches the CPU and both VIAs. RAM keeps
-    # its contents.
-    def reset!
-      settle!
-      @via1.reset!
-      @via2.reset!
-      @cpu.reset!
-    end
-
-    # Runs the drive cycles that fall in one host cycle: none, one or two.
-    # The host has run this cycle already, and the drive sees what it did
-    # from the next one on (see SerialPort). Asleep, the drive owes the
-    # cycles instead, until ATN moves or its counters are due (see Idle).
-    # It looks at ATN only after the machine pushed its lines into the bus
-    # (see host_written!).
-    def host_cycle!
-      if @asleep
-        return if (@slept += 1) != @wake_at && @host_still
-
-        return doze
-      end
-
-      phase = @phase + CLOCK_HZ
-      while phase >= @host_clock_hz
-        @asleep ? @owed += 1 : run_cycle
-        phase -= @host_clock_hz
-      end
-      @phase = phase
-      settle! if @serial_port.atn_moved?
-      @serial_port.latch_host
-      plan_wake if @asleep
-    end
-
-    # The machine pushed its lines into the bus, so ATN may have moved.
-    def host_written!
-      @host_still = false
-    end
-
-    # Runs one drive cycle, catching up first on any the drive owes (see
-    # step).
-    def cycle!
-      settle!
-      step
-    end
-
     # The drive's whole state: its clock phase, the CPU, RAM, both VIAs,
     # the serial port's latch of the C64's lines and the mechanism with its
     # disk. The drive settles first, so it is awake and not recording a
@@ -191,7 +58,7 @@ module Badline
     def save_state(out)
       settle!
       out.marker("DRIVE1541")
-      out.int(@phase).int(@cycles).boolean(@so_pending)
+      out.int(@phase).int(@cycles).boolean(@mechanism.so_pending)
       @serial_port.save_state(out)
       @via1.save_state(out)
       @via2.save_state(out)
@@ -205,7 +72,7 @@ module Badline
       input.marker("DRIVE1541")
       @phase = input.int
       @cycles = input.int
-      @so_pending = input.boolean?
+      @mechanism.so_pending = input.boolean?
       @serial_port.load_state(input)
       @via1.load_state(input)
       @via2.load_state(input)
@@ -215,33 +82,8 @@ module Badline
       forget_orbits
     end
 
-    def inspect
-      "#<#{self.class.name} cycles=#{cycles} cpu=(#{cpu.inspect})>"
-    end
-
-    # The read electronics signal a whole GCR byte. BYTE READY pulls VIA 2's
-    # CA1 low, a falling edge that sets its flag and, with latching on,
-    # latches port A. It reaches the CPU's SO pin while VIA 2's CA2 (SOE)
-    # is high, which lets the DOS spin on BVC for each byte. The CPU
-    # samples SO on the next cycle (see step).
-    def byte_ready!
-      @via2.ca1 = false
-      @so_pending = true if @via2.ca2_output
-    end
-
-    # BYTE READY lets go of CA1 with the next bit.
-    def byte_ready_ended!
-      @via2.ca1 = true
-    end
-
     private
 
-    # A drive cycle from host_cycle!, which may find the idle loop.
-    def run_cycle
-      step
-      idle_loop_reached if @cpu.program_counter == IDLE_LOOP && @idle_skip
-    end
-
     # One drive cycle. The VIAs clock ahead of the CPU, as the C64's chips
     # do, and either one pulls IRQ. Nothing drives NMI on the 1541. The CPU
     # runs whether or not the motor turns, since it answers ATN.
@@ -254,8 +96,7 @@ module Badline
     # high as the C64 asserts ATN, as the serial port sees it: from the
     # host cycle after the one that asserts it.
     def step
-      so = @so_pending
-      @so_pending = false
+      so = @mechanism.take_so
       @mechanism.cycle!
       @via1.ca1 = @serial_port.atn_low?
       @via1.cycle!

data/lib/badline/drive1571/bus.rb

@@ -0,0 +1,111 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1571
+    # The drive CPU's bus:
+    #
+    # $0000-$07FF - 2 KB of RAM
+    # $0800-$17FF - nothing: open bus
+    # $1800-$1BFF - VIA 1, its sixteen registers mirrored
+    # $1C00-$1FFF - VIA 2, its sixteen registers mirrored
+    # $2000-$3FFF - the WD1770, its four registers mirrored
+    # $4000-$7FFF - the CIA, its sixteen registers mirrored
+    # $8000-$FFFF - the DOS ROM
+    #
+    # Writes to the ROM and to open bus go nowhere, and a read from open
+    # bus finds the last byte on the data bus, as on the 1541. Any access
+    # to VIA 2 clears the BYTE READY latch VIA 1's PA7 reads (SerialPort).
+    #
+    # While Idle records a pass of the DOS's idle loop, the bus watches it,
+    # and while Idle looks for an orbit, it guards the drive (see
+    # Drive::Watch). Any access to the CIA or the WD1770 makes the pass
+    # volatile and taints the drive.
+    class Bus
+      include Addressable
+      include Drive::Watch
+
+      attr_reader :ram, :rom, :via1, :via2, :cia, :fdc, :data
+
+      def initialize(rom:, via1:, via2:, cia:, fdc:)
+        addressable_at(0, length: 2**16)
+        @ram = Memory.new([], length: 0x0800, start: 0)
+        @rom = rom
+        @via1 = via1
+        @via2 = via2
+        @cia = cia
+        @fdc = fdc
+        @mechanism = via2.mechanism
+        @data = 0
+        init_watch
+      end
+
+      # The last byte on the data bus and the RAM. What a watched stretch
+      # touched is Idle's, and a restored bus isn't watching.
+      def save_state(out)
+        out.int(@data)
+        @ram.save_state(out)
+      end
+
+      def load_state(input)
+        @data = input.int
+        @ram.load_state(input)
+        @watching = false
+      end
+
+      def peek(addr)
+        return @data = @rom.peek(addr) if addr >= 0x8000
+        return @data = chip_peek(addr) if addr >= 0x2000
+
+        watch_read(addr) if @watching
+        @data = if addr < 0x0800
+                  @ram.peek(addr)
+                elsif addr < 0x1800
+                  @data
+                elsif addr < 0x1c00
+                  @via1.peek(addr)
+                else
+                  @mechanism.release_byte_latch
+                  @via2.peek(addr)
+                end
+      end
+
+      def poke(addr, value)
+        @data = value
+        return if addr >= 0x8000
+        return chip_poke(addr, value) if addr >= 0x2000
+
+        low_poke(addr, value)
+      end
+
+      private
+
+      # A write below $2000: RAM or a VIA.
+      def low_poke(addr, value)
+        if addr < 0x0800
+          touch(addr) if @recording
+          @ram.poke(addr, value)
+        elsif addr >= 0x1c00
+          @mechanism.release_byte_latch
+          @via2.poke(addr, value)
+        elsif addr >= 0x1800
+          @via1.poke(addr, value)
+        end
+        watch_write(addr) if @watching
+      end
+
+      def chip_peek(addr)
+        watch_chip if @watching
+        addr >= 0x4000 ? @cia.peek(0x4000 | (addr & 0x0f)) : @fdc.peek(addr & 0x03)
+      end
+
+      def chip_poke(addr, value)
+        if addr >= 0x4000
+          @cia.poke(0x4000 | (addr & 0x0f), value)
+        else
+          @fdc.poke(addr & 0x03, value)
+        end
+        watch_chip if @watching
+      end
+    end
+  end
+end

data/lib/badline/drive1571/cpu.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1571
+    # The drive's 6502, on the drive's Bus.
+    class CPU
+      include Badline::CPU::Core
+      include Drive::IdleCPU
+    end
+  end
+end