badline 0.10.1 → 0.11.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/CHANGELOG.md +23 -0
- data/CLAUDE.md +25 -6
- data/CONTRIBUTING.md +8 -3
- data/README.md +63 -4
- data/doc/pinned-behaviour.md +75 -0
- data/doc/snapshots.md +15 -0
- data/lib/badline/address_bus/pla.rb +3 -16
- data/lib/badline/address_bus.rb +14 -0
- data/lib/badline/c128/banks.rb +35 -0
- data/lib/badline/c128/bus.rb +347 -0
- data/lib/badline/c128/bus_state.rb +53 -0
- data/lib/badline/c128/color_lines.rb +39 -0
- data/lib/badline/c128/cpu.rb +10 -0
- data/lib/badline/c128/drives.rb +95 -0
- data/lib/badline/c128/fast_serial.rb +62 -0
- data/lib/badline/c128/keys.rb +35 -0
- data/lib/badline/c128/mmu.rb +197 -0
- data/lib/badline/c128/mmu_pages.rb +105 -0
- data/lib/badline/c128/model.rb +39 -0
- data/lib/badline/c128/modes.rb +48 -0
- data/lib/badline/c128/saved_state.rb +121 -0
- data/lib/badline/c128/vdc/memory.rb +54 -0
- data/lib/badline/c128/vdc/painter.rb +143 -0
- data/lib/badline/c128/vdc/raster.rb +97 -0
- data/lib/badline/c128/vdc/window.rb +215 -0
- data/lib/badline/c128/vdc.rb +268 -0
- data/lib/badline/c128.rb +322 -0
- data/lib/badline/chrout_trap.rb +3 -0
- data/lib/badline/cia/fast_forward.rb +42 -0
- data/lib/badline/cia/serial.rb +12 -0
- data/lib/badline/cia/timer.rb +39 -0
- data/lib/badline/cia.rb +2 -0
- data/lib/badline/computer/attachments.rb +10 -13
- data/lib/badline/computer/kernal_traps.rb +29 -0
- data/lib/badline/computer.rb +5 -0
- data/lib/badline/drive/core.rb +172 -0
- data/lib/badline/{drive1541 → drive}/idle.rb +18 -19
- data/lib/badline/drive/idle_cpu.rb +28 -0
- data/lib/badline/{drive1541 → drive}/orbit.rb +2 -1
- data/lib/badline/drive/serial_lines.rb +73 -0
- data/lib/badline/{drive1541 → drive}/sleep.rb +4 -3
- data/lib/badline/drive/watch.rb +150 -0
- data/lib/badline/drive.rb +9 -0
- data/lib/badline/drive1541/bus.rb +5 -129
- data/lib/badline/drive1541/byte_ready.rb +48 -0
- data/lib/badline/drive1541/cpu.rb +1 -19
- data/lib/badline/drive1541/disk.rb +77 -20
- data/lib/badline/drive1541/disk_state.rb +7 -2
- data/lib/badline/drive1541/disk_via.rb +3 -0
- data/lib/badline/drive1541/mechanism.rb +48 -14
- data/lib/badline/drive1541/mechanism_state.rb +5 -4
- data/lib/badline/drive1541/rotation.rb +5 -5
- data/lib/badline/drive1541/serial_port.rb +4 -60
- data/lib/badline/drive1541.rb +13 -172
- data/lib/badline/drive1571/bus.rb +111 -0
- data/lib/badline/drive1571/cpu.rb +11 -0
- data/lib/badline/drive1571/serial_port.rb +37 -0
- data/lib/badline/drive1571/serial_via.rb +25 -0
- data/lib/badline/drive1571/wd1770.rb +34 -0
- data/lib/badline/drive1571.rb +225 -0
- data/lib/badline/frontend/app.rb +35 -22
- data/lib/badline/frontend/boot.rb +31 -1
- data/lib/badline/frontend/controls.rb +11 -0
- data/lib/badline/frontend/drive_led.rb +1 -1
- data/lib/badline/frontend/keys.rb +28 -1
- data/lib/badline/frontend/machine_window.rb +16 -13
- data/lib/badline/frontend/menu_media.rb +3 -3
- data/lib/badline/frontend/menu_pages.rb +8 -2
- data/lib/badline/frontend/menu_ports.rb +1 -1
- data/lib/badline/frontend/pause_menu.rb +1 -0
- data/lib/badline/frontend/screen.rb +33 -8
- data/lib/badline/frontend/screens.rb +90 -0
- data/lib/badline/frontend/timeline.rb +15 -4
- data/lib/badline/frontend.rb +1 -0
- data/lib/badline/iec_bus.rb +54 -4
- data/lib/badline/kernal_trap/file.rb +1 -1
- data/lib/badline/kernal_trap/layout.rb +58 -8
- data/lib/badline/kernal_trap/load.rb +1 -1
- data/lib/badline/kernal_trap/save.rb +1 -1
- data/lib/badline/kernal_trap/serial.rb +5 -0
- data/lib/badline/machine.rb +20 -9
- data/lib/badline/media/true_drive.rb +26 -23
- data/lib/badline/media.rb +8 -6
- data/lib/badline/options/event.rb +5 -1
- data/lib/badline/options/family.rb +52 -0
- data/lib/badline/options/help.rb +7 -2
- data/lib/badline/options/table.rb +8 -2
- data/lib/badline/options/validation.rb +14 -1
- data/lib/badline/options.rb +20 -19
- data/lib/badline/roms/README +36 -0
- data/lib/badline/roms/c128/basic.rom +0 -0
- data/lib/badline/roms/c128/character.rom +0 -0
- data/lib/badline/roms/c128/kernal.rom +0 -0
- data/lib/badline/roms/dos1571.rom +0 -0
- data/lib/badline/snapshot/container.rb +2 -0
- data/lib/badline/snapshot/image.rb +14 -0
- data/lib/badline/snapshot.rb +9 -2
- data/lib/badline/storage/d64_image.rb +3 -0
- data/lib/badline/storage/d71_image.rb +9 -4
- data/lib/badline/storage/g64_image.rb +7 -2
- data/lib/badline/time_of_day.rb +9 -0
- data/lib/badline/version.rb +1 -1
- data/lib/badline/via/fast_forward.rb +3 -3
- data/lib/badline/vic/display_state.rb +12 -0
- data/lib/badline/vic/registers.rb +3 -0
- data/lib/badline/vic.rb +108 -7
- data/lib/badline/vic20/attachments.rb +6 -0
- data/lib/badline/z80/arithmetic.rb +117 -0
- data/lib/badline/z80/bit_page.rb +55 -0
- data/lib/badline/z80/block_io.rb +58 -0
- data/lib/badline/z80/block_transfers.rb +59 -0
- data/lib/badline/z80/bus_cycles.rb +111 -0
- data/lib/badline/z80/core.rb +111 -0
- data/lib/badline/z80/exchanges.rb +50 -0
- data/lib/badline/z80/extended_page.rb +89 -0
- data/lib/badline/z80/flags.rb +37 -0
- data/lib/badline/z80/interrupt_acceptance.rb +46 -0
- data/lib/badline/z80/jumps.rb +82 -0
- data/lib/badline/z80/loads.rb +98 -0
- data/lib/badline/z80/main_page.rb +134 -0
- data/lib/badline/z80/registers.rb +120 -0
- data/lib/badline/z80/shifts.rb +64 -0
- data/lib/badline/z80.rb +11 -0
- data/lib/badline.rb +1 -0
- metadata +59 -4
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# frozen_string_literal: true
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module Badline
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module Drive
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# A drive bus's eye on what the CPU reaches, for Idle and Orbit. While
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# Idle records a pass of the DOS's idle loop, the bus watches it (see
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# watch!). While Idle looks for an orbit, the bus guards the drive
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# (see guard!). The bus calls watch_read and watch_write with the
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# address folded into $0000-$1FFF, RAM and the two VIAs at $1800 and
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# $1C00, while @watching.
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module Watch
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# VIA registers, as bits by offset, whose access makes a watched
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# stretch volatile: reads of either VIA's counters and shift register
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# and of VIA 1's port B, and writes to VIA 2's timers, shift register
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# and ACR. Any write to VIA 1 does too (watch_write).
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VOLATILE_VIA1_READS = 0x0731
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VOLATILE_VIA2_READS = 0x0730
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VOLATILE_VIA2_WRITES = 0x0ff0
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# The timer each VIA register reaches, by offset, as bits: 1 for
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# timer 1 and 2 for timer 2.
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TIMER_REGISTERS = [0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 0, 0, 0, 0, 0, 0].freeze
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# Whether a watched stretch did something that makes it unrepeatable.
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attr_reader :volatile
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# The RAM a watched stretch read or wrote, as each address's value
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# from before the first access.
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attr_reader :touched
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# Whether the drive did something since guard! that reached outside
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# it, or took something in from outside.
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attr_reader :tainted
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# The timers the drive read or wrote since guard!, as bits: VIA 1's
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# timer 1 and timer 2 in bits 0 and 1, and VIA 2's in bits 2 and 3.
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attr_reader :touched_timers
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# Starts watching: see volatile and touched. The bus stops watching
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# once the stretch turns volatile.
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def watch!
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@recording = true
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@volatile = false
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@touched = {}
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watching!
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end
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def unwatch!
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@recording = false
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watching!
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end
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# Starts guarding: see tainted and touched_timers. Reading VIA 1's
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# port B, which reads the serial bus, taints the drive, and so do
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# any write to VIA 1, whose port B drives the serial bus, a write to
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# VIA 2's shift register or ACR, and VIA 2 turning the motor on or
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# changing the LED. The bus stops guarding once the drive is tainted.
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def guard!
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@guarding = true
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@tainted = false
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@touched_timers = 0
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@led = @via2.port_b_output & Drive1541::Mechanism::LED
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watching!
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end
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private
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def init_watch
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@recording = @guarding = @watching = false
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@volatile = @tainted = false
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@touched = {}
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@touched_timers = 0
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@led = 0
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end
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def watching!
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@watching = @recording || @guarding
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end
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# An access to a chip beyond the VIAs, as the 1571's CIA and floppy
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# controller are: it makes the stretch volatile and taints the
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# drive.
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def watch_chip
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volatile! if @recording
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taint! if @guarding
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end
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def touch(addr)
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@touched[addr] = @ram.peek(addr) unless @touched.key?(addr)
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end
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def watch_read(addr)
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if addr < 0x0800
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touch(addr) if @recording
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elsif addr >= 0x1800
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via1 = addr < 0x1c00
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watch(via1 ? VOLATILE_VIA1_READS : VOLATILE_VIA2_READS, addr) if @recording
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guard_read(via1, addr & 0x0f) if @guarding
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end
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end
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def watch_write(addr)
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if addr >= 0x1c00
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watch_via2_write(addr) if @recording
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guard_via2_write(addr & 0x0f) if @guarding
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elsif addr >= 0x1800
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volatile! if @recording
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taint! if @guarding
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end
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end
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# Any write to VIA 1 makes the stretch volatile (watch_write), and so
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# does a write to VIA 2 that leaves the motor on.
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def watch_via2_write(addr)
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watch(VOLATILE_VIA2_WRITES, addr)
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volatile! if @recording && @via2.port_b_output.anybits?(Drive1541::Mechanism::MOTOR)
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end
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def watch(volatile, addr)
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volatile! if volatile.anybits?(1 << (addr & 0x0f))
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end
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def volatile!
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@volatile = true
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@recording = false
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watching!
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end
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def guard_read(via1, offset)
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return taint! if via1 && offset.zero?
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@touched_timers |= via1 ? TIMER_REGISTERS[offset] : TIMER_REGISTERS[offset] << 2
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end
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def guard_via2_write(offset)
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return taint! if offset.between?(0x0a, 0x0b)
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@touched_timers |= TIMER_REGISTERS[offset] << 2
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lines = @via2.port_b_output
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taint! if lines.anybits?(Drive1541::Mechanism::MOTOR) || (lines & Drive1541::Mechanism::LED) != @led
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end
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def taint!
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@tainted = true
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@guarding = false
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watching!
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end
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end
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end
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end
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# page is what its dummy read found. VICE-testprogs drive/openbus pins
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# both on a real 1541.
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#
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#
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# While Idle records a pass of the DOS's idle loop, the bus watches it,
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# and while Idle looks for an orbit, it guards the drive (see
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# Drive::Watch).
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class Bus
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include Addressable
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# VIA registers, as bits by offset, whose access makes a watched
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# stretch volatile: reads of either VIA's counters and shift register
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# and of VIA 1's port B, and writes to VIA 2's timers, shift register
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# and ACR. Any write to VIA 1 does too (watch_write).
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VOLATILE_VIA1_READS = 0x0731
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VOLATILE_VIA2_READS = 0x0730
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VOLATILE_VIA2_WRITES = 0x0ff0
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# The timer each VIA register reaches, by offset, as bits: 1 for
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# timer 1 and 2 for timer 2.
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TIMER_REGISTERS = [0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 0, 0, 0, 0, 0, 0].freeze
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include Drive::Watch
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attr_reader :ram, :rom, :via1, :via2, :data
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# Whether a watched stretch did something that makes it unrepeatable.
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attr_reader :volatile
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# The RAM a watched stretch read or wrote, as each address's value
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# from before the first access.
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attr_reader :touched
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# Whether the drive did something since guard! that reached outside
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# it, or took something in from outside.
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attr_reader :tainted
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# The timers the drive read or wrote since guard!, as bits: VIA 1's
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# timer 1 and timer 2 in bits 0 and 1, and VIA 2's in bits 2 and 3.
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attr_reader :touched_timers
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def initialize(rom:, via1:, via2:)
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addressable_at(0, length: 2**16)
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@ram = Memory.new([], length: 0x0800, start: 0)
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@via1 = via1
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@via2 = via2
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@data = 0
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@volatile = @tainted = false
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@touched = {}
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@touched_timers = 0
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@led = 0
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end
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# Starts watching: see volatile and touched. The bus stops watching
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# once the stretch turns volatile.
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def watch!
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@recording = true
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@volatile = false
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@touched = {}
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watching!
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end
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def unwatch!
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@recording = false
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watching!
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end
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# Starts guarding: see tainted and touched_timers. Reading VIA 1's
|
|
85
|
-
# port B, which reads the serial bus, taints the drive, and so do
|
|
86
|
-
# any write to VIA 1, whose port B drives the serial bus, a write to
|
|
87
|
-
# VIA 2's shift register or ACR, and VIA 2 turning the motor on or
|
|
88
|
-
# changing the LED. The bus stops guarding once the drive is tainted.
|
|
89
|
-
def guard!
|
|
90
|
-
@guarding = true
|
|
91
|
-
@tainted = false
|
|
92
|
-
@touched_timers = 0
|
|
93
|
-
@led = @via2.port_b_output & Mechanism::LED
|
|
94
|
-
watching!
|
|
37
|
+
init_watch
|
|
95
38
|
end
|
|
96
39
|
|
|
97
40
|
# The last byte on the data bus and the RAM. What a watched stretch
|
|
@@ -138,73 +81,6 @@ module Badline
|
|
|
138
81
|
end
|
|
139
82
|
watch_write(addr) if @watching
|
|
140
83
|
end
|
|
141
|
-
|
|
142
|
-
private
|
|
143
|
-
|
|
144
|
-
def watching!
|
|
145
|
-
@watching = @recording || @guarding
|
|
146
|
-
end
|
|
147
|
-
|
|
148
|
-
def touch(addr)
|
|
149
|
-
@touched[addr] = @ram.peek(addr) unless @touched.key?(addr)
|
|
150
|
-
end
|
|
151
|
-
|
|
152
|
-
def watch_read(addr)
|
|
153
|
-
if addr < 0x0800
|
|
154
|
-
touch(addr) if @recording
|
|
155
|
-
elsif addr >= 0x1800
|
|
156
|
-
via1 = addr < 0x1c00
|
|
157
|
-
watch(via1 ? VOLATILE_VIA1_READS : VOLATILE_VIA2_READS, addr) if @recording
|
|
158
|
-
guard_read(via1, addr & 0x0f) if @guarding
|
|
159
|
-
end
|
|
160
|
-
end
|
|
161
|
-
|
|
162
|
-
def watch_write(addr)
|
|
163
|
-
if addr >= 0x1c00
|
|
164
|
-
watch_via2_write(addr) if @recording
|
|
165
|
-
guard_via2_write(addr & 0x0f) if @guarding
|
|
166
|
-
elsif addr >= 0x1800
|
|
167
|
-
volatile! if @recording
|
|
168
|
-
taint! if @guarding
|
|
169
|
-
end
|
|
170
|
-
end
|
|
171
|
-
|
|
172
|
-
# Any write to VIA 1 makes the stretch volatile (watch_write), and so
|
|
173
|
-
# does a write to VIA 2 that leaves the motor on.
|
|
174
|
-
def watch_via2_write(addr)
|
|
175
|
-
watch(VOLATILE_VIA2_WRITES, addr)
|
|
176
|
-
volatile! if @recording && @via2.port_b_output.anybits?(Mechanism::MOTOR)
|
|
177
|
-
end
|
|
178
|
-
|
|
179
|
-
def watch(volatile, addr)
|
|
180
|
-
volatile! if volatile.anybits?(1 << (addr & 0x0f))
|
|
181
|
-
end
|
|
182
|
-
|
|
183
|
-
def volatile!
|
|
184
|
-
@volatile = true
|
|
185
|
-
@recording = false
|
|
186
|
-
watching!
|
|
187
|
-
end
|
|
188
|
-
|
|
189
|
-
def guard_read(via1, offset)
|
|
190
|
-
return taint! if via1 && offset.zero?
|
|
191
|
-
|
|
192
|
-
@touched_timers |= via1 ? TIMER_REGISTERS[offset] : TIMER_REGISTERS[offset] << 2
|
|
193
|
-
end
|
|
194
|
-
|
|
195
|
-
def guard_via2_write(offset)
|
|
196
|
-
return taint! if offset.between?(0x0a, 0x0b)
|
|
197
|
-
|
|
198
|
-
@touched_timers |= TIMER_REGISTERS[offset] << 2
|
|
199
|
-
lines = @via2.port_b_output
|
|
200
|
-
taint! if lines.anybits?(Mechanism::MOTOR) || (lines & Mechanism::LED) != @led
|
|
201
|
-
end
|
|
202
|
-
|
|
203
|
-
def taint!
|
|
204
|
-
@tainted = true
|
|
205
|
-
@guarding = false
|
|
206
|
-
watching!
|
|
207
|
-
end
|
|
208
84
|
end
|
|
209
85
|
end
|
|
210
86
|
end
|
|
@@ -0,0 +1,48 @@
|
|
|
1
|
+
# frozen_string_literal: true
|
|
2
|
+
|
|
3
|
+
module Badline
|
|
4
|
+
class Drive1541
|
|
5
|
+
# The Mechanism's BYTE READY line: to VIA 2's CA1, to the CPU's SO pin
|
|
6
|
+
# through SOE, and on the 1571 to a latch VIA 1's PA7 reads.
|
|
7
|
+
module ByteReady
|
|
8
|
+
# VIA 2, which DiskVIA plugs in.
|
|
9
|
+
attr_writer :via
|
|
10
|
+
|
|
11
|
+
# Whether BYTE READY reached SO for the CPU to sample on the drive's
|
|
12
|
+
# next cycle.
|
|
13
|
+
attr_accessor :so_pending
|
|
14
|
+
|
|
15
|
+
# Whether SO is pending, which the drive's cycle samples and clears.
|
|
16
|
+
def take_so
|
|
17
|
+
so = @so_pending
|
|
18
|
+
@so_pending = false
|
|
19
|
+
so
|
|
20
|
+
end
|
|
21
|
+
|
|
22
|
+
# The read electronics signal a whole GCR byte. BYTE READY pulls VIA
|
|
23
|
+
# 2's CA1 low, a falling edge that sets its flag and, with latching
|
|
24
|
+
# on, latches port A. It reaches the CPU's SO pin while VIA 2's CA2
|
|
25
|
+
# (SOE) is high, which lets the DOS spin on BVC for each byte. The CPU
|
|
26
|
+
# samples SO on the next cycle.
|
|
27
|
+
def byte_ready!
|
|
28
|
+
@byte_latched = true
|
|
29
|
+
@via.ca1 = false
|
|
30
|
+
@so_pending = true if @via.ca2_output
|
|
31
|
+
end
|
|
32
|
+
|
|
33
|
+
# BYTE READY lets go of CA1 with the next bit.
|
|
34
|
+
def byte_ready_ended!
|
|
35
|
+
@via.ca1 = true
|
|
36
|
+
end
|
|
37
|
+
|
|
38
|
+
# Whether BYTE READY has come since the CPU last read VIA 2, as the
|
|
39
|
+
# 1571 latches it for VIA 1's PA7.
|
|
40
|
+
def byte_latched? = @byte_latched
|
|
41
|
+
|
|
42
|
+
# A read of VIA 2 clears the 1571's BYTE READY latch.
|
|
43
|
+
def release_byte_latch
|
|
44
|
+
@byte_latched = false
|
|
45
|
+
end
|
|
46
|
+
end
|
|
47
|
+
end
|
|
48
|
+
end
|
|
@@ -5,25 +5,7 @@ module Badline
|
|
|
5
5
|
# The drive's 6502, on the drive's Bus.
|
|
6
6
|
class CPU
|
|
7
7
|
include Badline::CPU::Core
|
|
8
|
-
|
|
9
|
-
# Everything the CPU holds but its cycle and instruction counts: the
|
|
10
|
-
# registers, the interrupt lines and pipeline, and what the last
|
|
11
|
-
# instruction left in its working registers. Drive1541::Idle compares
|
|
12
|
-
# it at two instruction boundaries.
|
|
13
|
-
def idle_state
|
|
14
|
-
[@program_counter, @stack_pointer, @a, @x, @y, @status.value,
|
|
15
|
-
@irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll,
|
|
16
|
-
@boundary_irq, @boundary_nmi, @so_high, @interrupt, @brk, @pending_write, @stalled_at, @traps,
|
|
17
|
-
@operation, @optional_dummy, @boundary_crossed, @branch_taken,
|
|
18
|
-
@address, @pointer, @dummy_address, @value, @rmw_result]
|
|
19
|
-
end
|
|
20
|
-
|
|
21
|
-
# Counts +cycles+ cycles and +instructions+ instructions that ran
|
|
22
|
-
# without changing anything idle_state holds.
|
|
23
|
-
def fast_forward(cycles, instructions)
|
|
24
|
-
@cycles += cycles
|
|
25
|
-
@instructions += instructions
|
|
26
|
-
end
|
|
8
|
+
include Drive::IdleCPU
|
|
27
9
|
end
|
|
28
10
|
end
|
|
29
11
|
end
|
|
@@ -10,6 +10,11 @@ module Badline
|
|
|
10
10
|
# nothing between them. A .d64 image fills the whole tracks; a .g64
|
|
11
11
|
# can fill any of them, with tracks of any length.
|
|
12
12
|
#
|
|
13
|
+
# The disk has a second side, for the 1571's second head, its half
|
|
14
|
+
# tracks numbered from SIDE on. A .d71 fills both sides, its tracks
|
|
15
|
+
# 36-70 being tracks 1-35 of the second, and a .g71 holds 84 half
|
|
16
|
+
# tracks a side. A 1541 reads the first side only.
|
|
17
|
+
#
|
|
13
18
|
# The head writes into the tracks' bytes, and a write to a half track
|
|
14
19
|
# without data gives it a blank Track first. A disk made from an image
|
|
15
20
|
# remembers it: flush reads the sectors back off the tracks written
|
|
@@ -21,6 +26,15 @@ module Badline
|
|
|
21
26
|
|
|
22
27
|
MAX_HALF_TRACK = 84
|
|
23
28
|
|
|
29
|
+
# Where the second side's half tracks start: its track 1 is SIDE + 2.
|
|
30
|
+
SIDE = MAX_HALF_TRACK + 1
|
|
31
|
+
|
|
32
|
+
# The tracks a side of a .d71 holds.
|
|
33
|
+
D71_SIDE_TRACKS = 35
|
|
34
|
+
|
|
35
|
+
# The half track entries a side of a .g71 holds.
|
|
36
|
+
G71_SIDE_ENTRIES = 84
|
|
37
|
+
|
|
24
38
|
# GCR bytes around a track in each speed zone: 200 ms of rotation at
|
|
25
39
|
# 300 rpm, in bytes of 32, 30, 28 and 26 µs.
|
|
26
40
|
TRACK_LENGTHS = [6250, 6666, 7142, 7692].freeze
|
|
@@ -51,27 +65,63 @@ module Badline
|
|
|
51
65
|
# the 325-byte GCR data block. The gap after it takes up the rest.
|
|
52
66
|
SECTOR_LENGTH = SYNC_LENGTH + 10 + HEADER_GAP + SYNC_LENGTH + 325
|
|
53
67
|
|
|
54
|
-
# A disk from the image at +path+: a .g64 as its tracks are,
|
|
55
|
-
# anything else as a .d64,
|
|
56
|
-
# write-protected.
|
|
68
|
+
# A disk from the image at +path+: a .g64 or .g71 as its tracks are,
|
|
69
|
+
# a .d71 formatted on both sides, and anything else as a .d64,
|
|
70
|
+
# formatted. `read_only` opens the image write-protected.
|
|
57
71
|
def self.open(path, read_only: false)
|
|
58
72
|
return from_g64(Storage::G64Image.new(path, read_only:)).opened(path, read_only) if State.g64?(path)
|
|
73
|
+
return from_d64(Storage::D71Image.new(path, read_only:)).opened(path, read_only) if State.d71?(path)
|
|
59
74
|
|
|
60
75
|
from_d64(Storage::D64Image.new(path, read_only:)).opened(path, read_only)
|
|
61
76
|
end
|
|
62
77
|
|
|
63
|
-
# A disk from a G64 image, each half track as the image stores
|
|
64
|
-
# with its speed map. Flushing it writes the tracks back as they
|
|
78
|
+
# A disk from a G64 or G71 image, each half track as the image stores
|
|
79
|
+
# it, with its speed map. Flushing it writes the tracks back as they
|
|
80
|
+
# are.
|
|
65
81
|
def self.from_g64(image)
|
|
66
82
|
disk = new(image)
|
|
67
|
-
|
|
68
|
-
entry = half_track - Mechanism::MIN_HALF_TRACK
|
|
83
|
+
image.half_tracks.times do |entry|
|
|
69
84
|
track = image.track(entry)
|
|
70
|
-
disk.write(
|
|
85
|
+
disk.write(half_track_of(entry), Track.new(*track, image.speeds(entry))) if track
|
|
71
86
|
end
|
|
72
87
|
disk
|
|
73
88
|
end
|
|
74
89
|
|
|
90
|
+
# The half track a G64 or G71 table entry holds: entry 0 is track 1,
|
|
91
|
+
# and a .g71's entries from G71_SIDE_ENTRIES on are the second
|
|
92
|
+
# side's.
|
|
93
|
+
def self.half_track_of(entry)
|
|
94
|
+
side = entry / G71_SIDE_ENTRIES
|
|
95
|
+
(side * SIDE) + (entry % G71_SIDE_ENTRIES) + Mechanism::MIN_HALF_TRACK
|
|
96
|
+
end
|
|
97
|
+
|
|
98
|
+
# The table entry of a half track, or nil for one a G64 or G71 has
|
|
99
|
+
# no entry for.
|
|
100
|
+
def self.entry_of(half_track)
|
|
101
|
+
side = half_track / SIDE
|
|
102
|
+
entry = (half_track % SIDE) - Mechanism::MIN_HALF_TRACK
|
|
103
|
+
(side * G71_SIDE_ENTRIES) + entry if entry.between?(0, G71_SIDE_ENTRIES - 1)
|
|
104
|
+
end
|
|
105
|
+
|
|
106
|
+
# The half track an image's track number is on: a .d71's tracks past
|
|
107
|
+
# D71_SIDE_TRACKS are on the second side.
|
|
108
|
+
def self.d64_half_track(image, track)
|
|
109
|
+
return track * 2 unless image.sides == 2 && track > D71_SIDE_TRACKS
|
|
110
|
+
|
|
111
|
+
SIDE + ((track - D71_SIDE_TRACKS) * 2)
|
|
112
|
+
end
|
|
113
|
+
|
|
114
|
+
# The image's track number a half track holds, or nil for a half
|
|
115
|
+
# track or one past the image's last.
|
|
116
|
+
def self.d64_track(image, half_track)
|
|
117
|
+
side = half_track / SIDE
|
|
118
|
+
return unless (half_track % SIDE).even?
|
|
119
|
+
|
|
120
|
+
track = (half_track % SIDE) / 2
|
|
121
|
+
track += D71_SIDE_TRACKS if side == 1
|
|
122
|
+
track if track.positive? && track <= image.track_count && side < image.sides
|
|
123
|
+
end
|
|
124
|
+
|
|
75
125
|
# A disk formatted from a D64 image, each sector laid out as the DOS
|
|
76
126
|
# formats it, with the disk ID from the header block. A block the
|
|
77
127
|
# image's error table marks 20, 21, 22, 23, 27 or 29 is written the
|
|
@@ -81,7 +131,8 @@ module Badline
|
|
|
81
131
|
#
|
|
82
132
|
# Each track starts sector 0 at the angle the DOS's N: leaves it: track
|
|
83
133
|
# 1 at the index angle, and each track after it SKEWS[zone] of a turn
|
|
84
|
-
# round from the last.
|
|
134
|
+
# round from the last. A .d71's second side starts over at the index
|
|
135
|
+
# angle.
|
|
85
136
|
def self.from_d64(image)
|
|
86
137
|
track, sector = image.header_block
|
|
87
138
|
header = image.read_block(track, sector)
|
|
@@ -89,16 +140,18 @@ module Badline
|
|
|
89
140
|
disk = new(image)
|
|
90
141
|
angle = 0
|
|
91
142
|
(1..image.track_count).each do |track|
|
|
92
|
-
|
|
93
|
-
|
|
94
|
-
|
|
143
|
+
half_track = d64_half_track(image, track)
|
|
144
|
+
zone = zone((half_track % SIDE) / 2)
|
|
145
|
+
angle = half_track == SIDE + 2 ? 0 : (angle + SKEWS[zone]) % SKEW_TURN if track > 1
|
|
146
|
+
bytes = format_track(image, track, id, zone)
|
|
147
|
+
disk.write(half_track, Track.new(bytes.rotate(-(bytes.length * angle / SKEW_TURN)), zone))
|
|
95
148
|
end
|
|
96
149
|
disk
|
|
97
150
|
end
|
|
98
151
|
|
|
99
|
-
def self.format_track(image, track, id)
|
|
152
|
+
def self.format_track(image, track, id, zone = zone(track))
|
|
100
153
|
sectors = image.sectors_in(track)
|
|
101
|
-
length = TRACK_LENGTHS[zone
|
|
154
|
+
length = TRACK_LENGTHS[zone]
|
|
102
155
|
gap = (length - (sectors * SECTOR_LENGTH)) / sectors
|
|
103
156
|
bytes = []
|
|
104
157
|
sectors.times do |sector|
|
|
@@ -146,7 +199,7 @@ module Badline
|
|
|
146
199
|
|
|
147
200
|
def initialize(image = nil)
|
|
148
201
|
@image = image
|
|
149
|
-
@tracks = Array.new(
|
|
202
|
+
@tracks = Array.new(SIDE * 2)
|
|
150
203
|
@written = {}
|
|
151
204
|
@path = nil
|
|
152
205
|
@read_only = false
|
|
@@ -188,11 +241,14 @@ module Badline
|
|
|
188
241
|
def flush
|
|
189
242
|
return flush_tracks if @image.respond_to?(:store_tracks)
|
|
190
243
|
|
|
191
|
-
tracks = @written.keys.
|
|
244
|
+
tracks = @written.keys.filter_map do |half|
|
|
245
|
+
track = @image && Disk.d64_track(@image, half)
|
|
246
|
+
[half, track] if track
|
|
247
|
+
end
|
|
192
248
|
@written.clear
|
|
193
249
|
return if tracks.empty?
|
|
194
250
|
|
|
195
|
-
sectors = tracks.to_h { |half| [
|
|
251
|
+
sectors = tracks.to_h { |half, track| [track, SectorReader.read(@tracks[half].bytes, track)] }
|
|
196
252
|
id = disk_id(sectors)
|
|
197
253
|
warn_lost(sectors)
|
|
198
254
|
@image.store_blocks(sectors.flat_map do |track, found|
|
|
@@ -203,9 +259,10 @@ module Badline
|
|
|
203
259
|
private
|
|
204
260
|
|
|
205
261
|
def flush_tracks
|
|
206
|
-
tracks = @written.keys.sort.
|
|
207
|
-
|
|
208
|
-
|
|
262
|
+
tracks = @written.keys.sort.filter_map do |half|
|
|
263
|
+
entry = Disk.entry_of(half)
|
|
264
|
+
[entry, [@tracks[half].bytes, @tracks[half].zone]] if entry
|
|
265
|
+
end.to_h
|
|
209
266
|
@written.clear
|
|
210
267
|
@image.store_tracks(tracks) unless tracks.empty?
|
|
211
268
|
end
|
|
@@ -12,13 +12,18 @@ module Badline
|
|
|
12
12
|
# for a disk from Disk.open. Nil for a disk made another way.
|
|
13
13
|
attr_reader :path, :read_only
|
|
14
14
|
|
|
15
|
-
# A .g64 image by its name,
|
|
16
|
-
|
|
15
|
+
# A .g64 or .g71 image by its name, a .d71 by its name, and anything
|
|
16
|
+
# else a .d64.
|
|
17
|
+
def self.g64?(path) = %w[.g64 .g71].include?(File.extname(path).downcase)
|
|
18
|
+
|
|
19
|
+
def self.d71?(path) = File.extname(path).casecmp?(".d71")
|
|
17
20
|
|
|
18
21
|
# A disk for the image at the path, its tracks left for the state.
|
|
19
22
|
def self.reopen(path, read_only)
|
|
20
23
|
if g64?(path)
|
|
21
24
|
Disk.new(Storage::G64Image.new(path, read_only:)).opened(path, read_only)
|
|
25
|
+
elsif d71?(path)
|
|
26
|
+
Disk.new(Storage::D71Image.new(path, read_only:)).opened(path, read_only)
|
|
22
27
|
else
|
|
23
28
|
Disk.new(Storage::D64Image.new(path, read_only:)).opened(path, read_only)
|
|
24
29
|
end
|
|
@@ -7,8 +7,11 @@ module Badline
|
|
|
7
7
|
# hears both after every write and reset, since ORB, DDRB, the ACR and
|
|
8
8
|
# the PCR can all change them.
|
|
9
9
|
class DiskVIA < VIA
|
|
10
|
+
attr_reader :mechanism
|
|
11
|
+
|
|
10
12
|
def initialize(start:, mechanism:)
|
|
11
13
|
@mechanism = mechanism
|
|
14
|
+
mechanism.via = self
|
|
12
15
|
super(start:, peripheral: mechanism)
|
|
13
16
|
end
|
|
14
17
|
|