badline 0.10.1 → 0.11.1

data/lib/badline/z80/core.rb

@@ -0,0 +1,111 @@
+# frozen_string_literal: true
+
+require "badline/z80/flags"
+require "badline/z80/registers"
+require "badline/z80/bus_cycles"
+require "badline/z80/arithmetic"
+require "badline/z80/shifts"
+require "badline/z80/loads"
+require "badline/z80/exchanges"
+require "badline/z80/jumps"
+require "badline/z80/main_page"
+require "badline/z80/bit_page"
+require "badline/z80/extended_page"
+require "badline/z80/block_transfers"
+require "badline/z80/block_io"
+require "badline/z80/interrupt_acceptance"
+
+module Badline
+  class Z80
+    # The Z80 core, on whatever bus +bus+ is. The bus answers
+    # fetch(address) for an opcode fetch (M1), read(address) and
+    # write(address, value) for memory, input(port) and output(port, value)
+    # for I/O, and acknowledge for the byte a device puts on the data bus
+    # when the CPU takes a maskable interrupt.
+    #
+    # #step! runs one instruction, prefixes and all, or takes an interrupt,
+    # or idles one opcode fetch while halted. #cycles counts T-states, and
+    # each bus call happens while it holds the T-state its machine cycle
+    # starts on.
+    module Core
+      include Flags
+      include Registers
+      include BusCycles
+      include Arithmetic
+      include Shifts
+      include Loads
+      include Exchanges
+      include Jumps
+      include MainPage
+      include BitPage
+      include ExtendedPage
+      include BlockTransfers
+      include BlockIO
+      include InterruptAcceptance
+
+      attr_reader :bus, :cycles, :nmi
+      attr_accessor :int
+
+      def initialize(bus)
+        @bus = bus
+        @cycles = 0
+        @a = @f = 0xff
+        @b = @c = @d = @e = @h = @l = 0xff
+        @af_alt = @bc_alt = @de_alt = @hl_alt = 0xffff
+        @ix = @iy = @sp = 0xffff
+        @wz = @q = @last_q = 0
+        @prefix = 0
+        @int = @nmi = @nmi_pending = false
+        reset!
+      end
+
+      # The RESET line: the program counter, I, R and the interrupt mode go
+      # to 0, and interrupts are disabled.
+      def reset!
+        @pc = @i = @r = @im = 0
+        @iff1 = @iff2 = false
+        @halted = @after_ei = @after_ld_a_ir = false
+        @nmi_pending = false
+      end
+
+      # The NMI line. Asserting it latches an interrupt, taken after the
+      # current instruction, and holding it does nothing more.
+      def nmi=(asserted)
+        @nmi_pending = true if asserted && !@nmi
+        @nmi = asserted
+      end
+
+      # The WAIT line: a bus that holds it during an access lengthens that
+      # machine cycle by +states+ T-states.
+      def wait(states)
+        @cycles += states
+      end
+
+      def step!
+        if @nmi_pending
+          take_nmi
+        elsif @int && @iff1 && !@after_ei
+          take_int
+        else
+          @after_ei = @after_ld_a_ir = false
+          @last_q = @q
+          @q = 0
+          @prefix = 0
+          @halted ? idle_fetch : execute(fetch_opcode)
+        end
+        nil
+      end
+
+      def inspect
+        "Cycles: #{@cycles}, PC: #{hex(@pc)}, SP: #{hex(@sp)}, AF: #{hex(af)}, BC: #{hex(bc)}, " \
+          "DE: #{hex(de)}, HL: #{hex(hl)}, IX: #{hex(@ix)}, IY: #{hex(@iy)}"
+      end
+
+      private
+
+      def hex(value)
+        value.to_s(16).rjust(4, "0")
+      end
+    end
+  end
+end

data/lib/badline/z80/exchanges.rb

@@ -0,0 +1,50 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # EX AF,AF', EXX, EX DE,HL and EX (SP),HL. Only the last swaps IX or IY
+    # after a prefix.
+    module Exchanges
+      private
+
+      def exchange_alternates
+        bc_alt = @bc_alt
+        de_alt = @de_alt
+        hl_alt = @hl_alt
+        @bc_alt = bc
+        @de_alt = de
+        @hl_alt = hl
+        self.bc = bc_alt
+        self.de = de_alt
+        self.hl = hl_alt
+      end
+
+      def exchange_af
+        af_alt = @af_alt
+        @af_alt = af
+        self.af = af_alt
+      end
+
+      def exchange_de_hl
+        d = @d
+        e = @e
+        @d = @h
+        @e = @l
+        @h = d
+        @l = e
+      end
+
+      def exchange_stack_top
+        low = read_byte(@sp)
+        high = read_byte((@sp + 1) & 0xffff)
+        @cycles += 1
+        value = hl_or_index
+        write_byte((@sp + 1) & 0xffff, value >> 8)
+        write_byte(@sp, value & 0xff)
+        @cycles += 2
+        @wz = low | (high << 8)
+        self.hl_or_index = @wz
+      end
+    end
+  end
+end

data/lib/badline/z80/extended_page.rb

@@ -0,0 +1,89 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The interrupt mode each of ED 46, 4E, 56, 5E, 66, 6E, 76 and 7E sets.
+    # 4E and 6E set mode 0 on the NMOS Z80.
+    INTERRUPT_MODES = [0, 0, 1, 2, 0, 0, 1, 2].freeze
+
+    # The ED page: its second quarter, the block instructions, and 8
+    # T-states of nothing for the rest.
+    module ExtendedPage
+      private
+
+      def execute_extended(opcode)
+        case opcode >> 6
+        when 1 then extended_operation(opcode)
+        when 2 then block_operation(opcode) if (opcode & 0x24) == 0x20
+        end
+      end
+
+      def extended_operation(opcode)
+        row = (opcode >> 3) & 7
+        case opcode & 7
+        when 0 then input_register(row)
+        when 1 then output_register(row)
+        when 2 then add_pair_with_carry(row)
+        when 3 then row.nobits?(1) ? store_word(pair(row >> 1)) : set_pair(row >> 1, load_word)
+        when 4 then neg
+        when 5 then return_from_interrupt
+        when 6 then @im = INTERRUPT_MODES[row]
+        else special_register(row)
+        end
+      end
+
+      # IN r,(C), and IN F,(C) at index 6, which sets the flags alone.
+      def input_register(index)
+        port = bc
+        value = input(port)
+        @wz = (port + 1) & 0xffff
+        assign_flags((@f & CF) | SZ53P[value])
+        set_register(index, value) unless index == 6
+      end
+
+      # OUT (C),r, and at index 6 OUT (C),0.
+      def output_register(index)
+        port = bc
+        output(port, index == 6 ? 0 : register(index))
+        @wz = (port + 1) & 0xffff
+      end
+
+      def add_pair_with_carry(row)
+        row.nobits?(1) ? sbc16(pair(row >> 1)) : adc16(pair(row >> 1))
+        @cycles += 7
+      end
+
+      # RETN and RETI both restore IFF1 from IFF2.
+      def return_from_interrupt
+        @iff1 = @iff2
+        return_from_call
+      end
+
+      # LD I,A, LD R,A, LD A,I, LD A,R, RRD and RLD, and two that do
+      # nothing.
+      def special_register(row)
+        case row
+        when 0 then @i = load_ir(@a)
+        when 1 then @r = load_ir(@a)
+        when 2 then @a = load_a_from_ir(@i)
+        when 3 then @a = load_a_from_ir(@r)
+        when 4 then rotate_digits(false)
+        when 5 then rotate_digits(true)
+        end
+      end
+
+      def load_ir(value)
+        @cycles += 1
+        value
+      end
+
+      # P/V copies IFF2, and an interrupt taken next clears it again.
+      def load_a_from_ir(value)
+        @cycles += 1
+        assign_flags((@f & CF) | SZ53[value] | (@iff2 ? PF : 0))
+        @after_ld_a_ir = true
+        value
+      end
+    end
+  end
+end

data/lib/badline/z80/flags.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    CF = 0x01
+    NF = 0x02
+    PF = 0x04
+    XF = 0x08
+    HF = 0x10
+    YF = 0x20
+    ZF = 0x40
+    SF = 0x80
+
+    # Bits 5 and 3, which most instructions copy from a result.
+    XYF = YF | XF
+
+    # S, Z, Y and X as a result byte sets them.
+    SZ53 = Array.new(256) { |v| (v & (SF | XYF)) | (v.zero? ? ZF : 0) }.freeze
+
+    # P/V as parity: set when a byte has an even number of bits set.
+    PARITY = Array.new(256) { |v| (0x6996 >> ((v ^ (v >> 4)) & 0x0f)).nobits?(1) ? PF : 0 }.freeze
+
+    SZ53P = Array.new(256) { |v| SZ53[v] | PARITY[v] }.freeze
+
+    # The flags, which the core keeps in F as the chip does. Every
+    # instruction that sets them through the ALU also latches them in Q,
+    # which SCF and CCF read on the next instruction.
+    module Flags
+      private
+
+      def assign_flags(value)
+        @f = value
+        @q = value
+      end
+    end
+  end
+end

data/lib/badline/z80/interrupt_acceptance.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Taking NMI and INT between instructions. Either wakes a halted CPU,
+    # whose program counter already points past the HALT.
+    module InterruptAcceptance
+      private
+
+      # An opcode fetch whose byte is ignored, a T-state more, and a call
+      # to $0066. IFF2 keeps what IFF1 held, for RETN to restore.
+      def take_nmi
+        @nmi_pending = false
+        @halted = false
+        @iff1 = false
+        @bus.fetch(@pc)
+        refresh
+        @cycles += 5
+        push(@pc)
+        @pc = 0x66
+        @wz = 0x66
+      end
+
+      # The acknowledge cycle, an M1 with two wait states, reads a byte
+      # from the device. Mode 0 runs it as an opcode, which is a RST in
+      # practice, mode 1 calls $0038, and mode 2 calls through the vector
+      # at I and that byte.
+      def take_int
+        @halted = false
+        @f &= ~PF if @after_ld_a_ir
+        @iff1 = @iff2 = false
+        @after_ld_a_ir = false
+        @prefix = 0
+        data = @bus.acknowledge
+        refresh
+        @cycles += 6
+        return execute(data) if @im.zero?
+
+        @cycles += 1
+        push(@pc)
+        @pc = @im == 1 ? 0x38 : read_word((@i << 8) | data)
+        @wz = @pc
+      end
+    end
+  end
+end

data/lib/badline/z80/jumps.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Jumps, calls and returns. Each leaves its target in WZ, and JP cc and
+    # CALL cc do whether they jump or not.
+    module Jumps
+      private
+
+      # The conditions bits 5-3 pick: NZ Z NC C PO PE P M.
+      def condition?(index)
+        case index
+        when 0 then @f.nobits?(ZF)
+        when 1 then @f.anybits?(ZF)
+        when 2 then @f.nobits?(CF)
+        when 3 then @f.anybits?(CF)
+        when 4 then @f.nobits?(PF)
+        when 5 then @f.anybits?(PF)
+        when 6 then @f.nobits?(SF)
+        else @f.anybits?(SF)
+        end
+      end
+
+      # NOP, EX AF,AF', DJNZ, JR and JR cc.
+      def relative_jump(row)
+        case row
+        when 0 then nil
+        when 1 then exchange_af
+        when 2 then decrement_and_jump
+        when 3 then jump_relative(fetch_byte)
+        else
+          offset = fetch_byte
+          jump_relative(offset) if condition?(row - 4)
+        end
+      end
+
+      def decrement_and_jump
+        @cycles += 1
+        offset = fetch_byte
+        @b = (@b - 1) & 0xff
+        jump_relative(offset) unless @b.zero?
+      end
+
+      def jump_relative(offset)
+        @cycles += 5
+        @pc = (@pc + offset - (offset > 127 ? 256 : 0)) & 0xffff
+        @wz = @pc
+      end
+
+      def jump(taken)
+        @wz = fetch_word
+        @pc = @wz if taken
+      end
+
+      def call(taken)
+        @wz = fetch_word
+        return unless taken
+
+        @cycles += 1
+        push(@pc)
+        @pc = @wz
+      end
+
+      def conditional_return(index)
+        @cycles += 1
+        return_from_call if condition?(index)
+      end
+
+      def return_from_call
+        @pc = pop
+        @wz = @pc
+      end
+
+      def restart(address)
+        @cycles += 1
+        push(@pc)
+        @pc = address
+        @wz = address
+      end
+    end
+  end
+end

data/lib/badline/z80/loads.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # Loads, PUSH, and IN and OUT through a port A and n address. The loads
+    # through a pointer leave the address after it in WZ, or for a store of
+    # A, A and the low byte of that address.
+    module Loads
+      private
+
+      # LD r,r' with (HL) as index 6.
+      def load_register(target, source)
+        if source == 6
+          set_plain_register(target, read_byte(operand_address))
+        elsif target == 6
+          write_byte(operand_address, plain_register(source))
+        else
+          set_register(target, register(source))
+        end
+      end
+
+      # LD r,n, and LD (IX+d),n, which reads n while it adds d.
+      def load_immediate(index)
+        return set_register(index, fetch_byte) unless index == 6
+        return write_byte(hl, fetch_byte) if @prefix.zero?
+
+        displaced
+        value = fetch_byte
+        @cycles += 2
+        write_byte(@wz, value)
+      end
+
+      def indirect_load(row)
+        case row
+        when 0 then store_a(bc)
+        when 1 then load_a(bc)
+        when 2 then store_a(de)
+        when 3 then load_a(de)
+        when 4 then store_word(hl_or_index)
+        when 5 then self.hl_or_index = load_word
+        when 6 then store_a(fetch_word)
+        else load_a(fetch_word)
+        end
+      end
+
+      def load_a(address)
+        @a = read_byte(address)
+        @wz = (address + 1) & 0xffff
+      end
+
+      def store_a(address)
+        write_byte(address, @a)
+        @wz = (@a << 8) | ((address + 1) & 0xff)
+      end
+
+      def store_word(value)
+        address = fetch_word
+        write_word(address, value)
+        @wz = (address + 1) & 0xffff
+      end
+
+      def load_word
+        address = fetch_word
+        @wz = (address + 1) & 0xffff
+        read_word(address)
+      end
+
+      def push_pair(index)
+        @cycles += 1
+        push(stack_pair(index))
+      end
+
+      # RET, EXX, JP (HL) and LD SP,HL.
+      def stack_and_exchange(index)
+        case index
+        when 0 then return_from_call
+        when 1 then exchange_alternates
+        when 2 then @pc = hl_or_index
+        else
+          @cycles += 2
+          @sp = hl_or_index
+        end
+      end
+
+      def output_immediate
+        port = (@a << 8) | fetch_byte
+        output(port, @a)
+        @wz = (port & 0xff00) | ((port + 1) & 0xff)
+      end
+
+      def input_immediate
+        port = (@a << 8) | fetch_byte
+        @wz = (port + 1) & 0xffff
+        @a = input(port)
+      end
+    end
+  end
+end

data/lib/badline/z80/main_page.rb

@@ -0,0 +1,134 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The unprefixed opcodes, which DD and FD reuse with IX or IY for HL.
+    # An opcode splits into its quarter (bits 7-6), its row (5-3) and its
+    # column (2-0), and each quarter of the page is regular in rows and
+    # columns.
+    module MainPage
+      private
+
+      def execute(opcode)
+        case opcode >> 6
+        when 0 then execute_low(opcode)
+        when 1 then opcode == 0x76 ? @halted = true : load_register((opcode >> 3) & 7, opcode & 7)
+        when 2 then alu((opcode >> 3) & 7, operand(opcode & 7))
+        else execute_high(opcode)
+        end
+      end
+
+      def execute_low(opcode)
+        row = (opcode >> 3) & 7
+        case opcode & 7
+        when 0 then relative_jump(row)
+        when 1 then opcode.nobits?(8) ? set_pair(row >> 1, fetch_word) : add_pair(row >> 1)
+        when 2 then indirect_load(row)
+        when 3 then step_pair(row)
+        when 4 then modify(row, true)
+        when 5 then modify(row, false)
+        when 6 then load_immediate(row)
+        else accumulator_operation(row)
+        end
+      end
+
+      def execute_high(opcode)
+        row = (opcode >> 3) & 7
+        case opcode & 7
+        when 0 then conditional_return(row)
+        when 1 then opcode.nobits?(8) ? set_stack_pair(row >> 1, pop) : stack_and_exchange(row >> 1)
+        when 2 then jump(condition?(row))
+        when 3 then miscellaneous(row)
+        when 4 then call(condition?(row))
+        when 5 then opcode.nobits?(8) ? push_pair(row >> 1) : call_or_prefix(row >> 1)
+        when 6 then alu(row, fetch_byte)
+        else restart(row << 3)
+        end
+      end
+
+      # The operand of the 8-bit ALU opcodes: a register or (HL).
+      def operand(index)
+        index == 6 ? read_byte(operand_address) : register(index)
+      end
+
+      # INC and DEC on a register or (HL).
+      def modify(index, increase)
+        if index == 6
+          address = operand_address
+          value = read_byte(address)
+          @cycles += 1
+          write_byte(address, increase ? increment(value) : decrement(value))
+        else
+          set_register(index, increase ? increment(register(index)) : decrement(register(index)))
+        end
+      end
+
+      # INC and DEC on a pair, which touch no flags.
+      def step_pair(row)
+        @cycles += 2
+        index = row >> 1
+        set_pair(index, (pair(index) + (row.nobits?(1) ? 1 : -1)) & 0xffff)
+      end
+
+      def add_pair(index)
+        self.hl_or_index = add16(hl_or_index, pair(index))
+        @cycles += 7
+      end
+
+      def accumulator_operation(row)
+        case row
+        when 0, 1, 2, 3 then rotate_a(row)
+        when 4 then daa
+        when 5 then complement
+        when 6 then assign_flags((@f & (SF | ZF | PF)) | CF | (((@last_q ^ @f) | @a) & XYF))
+        else assign_flags((@f & (SF | ZF | PF)) | ((@f & CF) << 4) | ((@f & CF) ^ CF) | (((@last_q ^ @f) | @a) & XYF))
+        end
+      end
+
+      def complement
+        @a ^= 0xff
+        assign_flags((@f & (SF | ZF | PF | CF)) | HF | NF | (@a & XYF))
+      end
+
+      def miscellaneous(row)
+        case row
+        when 0 then jump(true)
+        when 1 then @prefix.zero? ? execute_bits(fetch_opcode) : execute_index_bits
+        when 2 then output_immediate
+        when 3 then input_immediate
+        when 4 then exchange_stack_top
+        when 5 then exchange_de_hl
+        when 6 then @iff1 = @iff2 = false
+        else enable_interrupts
+        end
+      end
+
+      def call_or_prefix(index)
+        case index
+        when 0 then call(true)
+        when 1 then index_prefix(1)
+        when 2 then extended_prefix
+        else index_prefix(2)
+        end
+      end
+
+      # DD and FD: the next opcode runs with IX or IY for HL. A prefix
+      # after a prefix replaces it.
+      def index_prefix(prefix)
+        @prefix = prefix
+        @last_q = 0
+        execute(fetch_opcode)
+      end
+
+      def extended_prefix
+        @prefix = 0
+        execute_extended(fetch_opcode)
+      end
+
+      def enable_interrupts
+        @iff1 = @iff2 = true
+        @after_ei = true
+      end
+    end
+  end
+end