badline 0.10.1 → 0.11.1

data/lib/badline/c128/mmu.rb

@@ -0,0 +1,197 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The 8722 MMU's registers, $D500-$D50B in C128 mode:
+    #
+    #   $D500 CR: I/O, the ROMs and the RAM bank the CPU sees
+    #   $D501-$D504 PCRA-PCRD: preset configurations
+    #   $D505 MCR: the CPU (bit 0, 1 for the 8502), FSDIR, GAME and EXROM
+    #         in, C64 mode (bit 6) and the 40/80 key
+    #   $D506 RCR: common RAM and the VIC's RAM bank
+    #   $D507-$D50A P0L, P0H, P1L, P1H: page 0 and page 1 relocation
+    #   $D50B VR: the version, 2 banks of version 0
+    #
+    # The rest of the page reads $FF. $FF00 is CR again, and a write to
+    # $FF01-$FF04, the LCRs, copies PCRA-PCRD into CR. Those five answer in
+    # every configuration, whatever CR maps there.
+    #
+    # A write to P0H or P1H waits until the matching P0L or P1L write
+    # takes it.
+    #
+    # On the C128 the Z80 runs first and hands the bus to the 8502. Here the
+    # 8502 runs from reset, with MCR as the Z80 leaves it. A machine built
+    # for C64 mode resets into C64 mode, the state the C128 KERNAL leaves
+    # when C= is held at power-on. In C64 mode the MMU answers nowhere, but
+    # the CPU's RAM bank, common RAM and the VIC's bank it holds stay in
+    # force.
+    class MMU
+      CR = 0
+      MCR = 5
+      RCR = 6
+      P0L = 7
+      P0H = 8
+      P1L = 9
+      P1H = 10
+      VR = 11
+
+      MCR_8502 = 0x01
+      MCR_FSDIR = 0x08
+      MCR_C64_MODE = 0x40
+      VERSION = 0x20
+
+      # MCR's bits that read back what was written: the CPU, FSDIR and C64
+      # mode. Bits 1 and 2 have no pins and read 1.
+      MCR_WRITABLE = 0x49
+      MCR_UNUSED = 0x06
+      MCR_GAME = 0x10
+      MCR_EXROM = 0x20
+      MCR_DISPLAY_KEY = 0x80
+
+      # The common RAM sizes RCR bits 0-1 pick, in pages.
+      COMMON_PAGES = [4, 16, 32, 64].freeze
+
+      # The registers, CR first.
+      attr_reader :registers
+
+      # Whether the 40/80 DISPLAY key is locked down, which MCR bit 7 reads
+      # as 0 in C128 mode.
+      attr_accessor :display_key
+
+      # The cartridge's GAME and EXROM lines, which MCR bits 4 and 5 read.
+      attr_writer :game, :exrom
+
+      # +mode+ is the mode a reset leaves, :c128 or :c64.
+      def initialize(mode = :c64)
+        @reset_mode = mode
+        @registers = Array.new(12, 0)
+        @display_key = false
+        @game = 1
+        @exrom = 1
+        @on_change = nil
+        @on_fast_serial_change = nil
+        reset!
+      end
+
+      # Calls the block whenever the mapping the registers ask for changes.
+      def on_change(&block)
+        @on_change = block
+      end
+
+      # Calls the block whenever FSDIR turns the fast serial buffers round.
+      def on_fast_serial_change(&block)
+        @on_fast_serial_change = block
+      end
+
+      def reset!
+        fast_serial_out = fast_serial_out?
+        @registers.fill(0)
+        @registers[MCR] = @reset_mode == :c64 ? MCR_C64_MODE | MCR_8502 : MCR_8502
+        @registers[P1L] = 0x01
+        @registers[VR] = VERSION
+        @p0h_latch = 0
+        @p1h_latch = 0
+        @on_change&.call
+        @on_fast_serial_change&.call if fast_serial_out
+      end
+
+      def c64_mode? = @registers[MCR].anybits?(MCR_C64_MODE)
+
+      # Whether MCR bit 3, FSDIR, turns the fast serial buffers outwards, so
+      # CIA 1's CNT and SP drive SRQ and DATA.
+      def fast_serial_out? = @registers[MCR].anybits?(MCR_FSDIR)
+
+      # :c64 or :c128, the mode MCR bit 6 selects.
+      def mode = c64_mode? ? :c64 : :c128
+
+      # The 64K bank the VIC sees, RCR bit 6. Bit 7 picks banks a 256K
+      # machine has.
+      def vic_bank = (@registers[RCR] >> 6) & 0x01
+
+      # The RAM bank the CPU sees, CR bit 6.
+      def cpu_bank = (@registers[CR] >> 6) & 0x01
+
+      def cr = @registers[CR]
+
+      # The pages from $0000 up that common RAM keeps in bank 0, or 0.
+      def common_low_pages = @registers[RCR].anybits?(0x04) ? common_pages : 0
+
+      # The first page of the common RAM below $FFFF, or 256 for none.
+      def common_high_start = @registers[RCR].anybits?(0x08) ? 256 - common_pages : 256
+
+      # The page and the bank page 0 moves to.
+      def p0_page = @registers[P0L]
+      def p0_bank = @registers[P0H] & 0x01
+
+      # The page and the bank page 1 moves to.
+      def p1_page = @registers[P1L]
+      def p1_bank = @registers[P1H] & 0x01
+
+      # The registers at $D500-$D5FF.
+      def peek(addr)
+        offset = addr & 0xff
+        case offset
+        when MCR then mcr
+        when P0H, P1H then 0xf0 | @registers[offset]
+        when 0..VR then @registers[offset]
+        else 0xff
+        end
+      end
+
+      def poke(addr, value)
+        offset = addr & 0xff
+        case offset
+        when P0H then @p0h_latch = value & 0x0f
+        when P1H then @p1h_latch = value & 0x0f
+        when P0L then relocate(P0L, P0H, @p0h_latch, value)
+        when P1L then relocate(P1L, P1H, @p1h_latch, value)
+        when CR..RCR then write(offset, value)
+        end
+      end
+
+      # The registers and the P0H and P1H writes waiting for P0L and P1L.
+      # The bus maps the restored registers once its own state is back.
+      def save_state(out)
+        out.ints(@registers).int(@p0h_latch).int(@p1h_latch)
+      end
+
+      def load_state(input)
+        input.ints_into(@registers)
+        @p0h_latch = input.int
+        @p1h_latch = input.int
+      end
+
+      # CR and the LCRs at $FF00-$FF04: an LCR reads its PCR.
+      def peek_configuration(addr) = @registers[addr & 0x07]
+
+      def poke_configuration(addr, value)
+        offset = addr & 0x07
+        write(CR, offset.zero? ? value : @registers[offset])
+      end
+
+      private
+
+      def common_pages = COMMON_PAGES[@registers[RCR] & 0x03]
+
+      def mcr
+        value = (@registers[MCR] & MCR_WRITABLE) | MCR_UNUSED
+        value |= MCR_GAME if @game == 1
+        value |= MCR_EXROM if @exrom == 1
+        value |= MCR_DISPLAY_KEY unless @display_key
+        value
+      end
+
+      def relocate(low, high, latch, value)
+        @registers[high] = latch
+        write(low, value)
+      end
+
+      def write(offset, value)
+        fast_serial_out = fast_serial_out?
+        @registers[offset] = value
+        @on_change&.call
+        @on_fast_serial_change&.call if fast_serial_out? != fast_serial_out
+      end
+    end
+  end
+end

data/lib/badline/c128/mmu_pages.rb

@@ -0,0 +1,105 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    class Bus
+      # What the MMU maps. For the CPU: the RAM bank, common RAM and the
+      # pages page 0 and page 1 move to in both modes, and CR's ROMs and I/O
+      # in C128 mode. C64 mode lays the PLA's ROMs and I/O over the same RAM
+      # (AddressBus::PLA).
+      module MMUPages
+        private
+
+        # CR's ROMs and I/O over the RAM, with the configuration registers on
+        # top at $FF00.
+        def map_c128_pages
+          cr = @mmu.cr
+          map_ram_pages
+          @read_pages.fill(@basic_low_rom, 0x40, 0x40) if cr.nobits?(0x02)
+          map_rom_block((cr >> 2) & 0x03, 0x80)
+          map_rom_block((cr >> 4) & 0x03, 0xc0)
+          map_io_pages if cr.nobits?(0x01)
+          @configuration_reads.below = @read_pages[0xff]
+          @configuration_writes.below = @write_pages[0xff]
+          @read_pages[0xff] = @configuration_reads
+          @write_pages[0xff] = @configuration_writes
+        end
+
+        # A 16K block's two CR bits pick the system ROM, the internal or the
+        # external function ROM, neither of which is fitted, or RAM.
+        def map_rom_block(select, first_page)
+          case select
+          when 0 then map_system_rom(first_page)
+          when 1, 2 then @read_pages.fill(@open_bus, first_page, 0x40)
+          end
+        end
+
+        # BASIC's high half at $8000, or the screen editor, the character ROM
+        # and the KERNAL at $C000.
+        def map_system_rom(first_page)
+          if first_page == 0x80
+            @read_pages.fill(@basic_high_rom, 0x80, 0x40)
+          else
+            @read_pages.fill(@editor_rom, 0xc0, 0x10)
+            @read_pages.fill(@c128_character_rom, 0xd0, 0x10)
+            @read_pages.fill(@c128_kernal_rom, 0xe0, 0x20)
+          end
+        end
+
+        # The bank CR picks, with common RAM in bank 0, then the pages page 0
+        # and page 1 move to.
+        def map_ram_pages
+          @io_mapped = false
+          bank_ram = @mmu.cpu_bank.zero? ? @ram : @bank1
+          @read_pages.fill(bank_ram)
+          @write_pages.fill(bank_ram)
+          map_common_ram
+          relocate_pages
+        end
+
+        def map_common_ram
+          low = @mmu.common_low_pages
+          high = @mmu.common_high_start
+          @read_pages.fill(@ram, 0, low)
+          @write_pages.fill(@ram, 0, low)
+          @read_pages.fill(@ram, high, 256 - high)
+          @write_pages.fill(@ram, high, 256 - high)
+        end
+
+        # In C128 mode page 0 and page 1 go to the pages P0 and P1 name, in
+        # bank 0 if common RAM holds them. In both modes, the page each moved
+        # to reaches back to page 0 or page 1, in the bank it named, if the
+        # CPU sees that bank there. Page 1's takes the page they both name.
+        # C64 mode moves neither page 0 nor page 1 forward, so either can be
+        # the page that reaches back.
+        def relocate_pages
+          mmu = @mmu
+          forward = !mmu.c64_mode?
+          if forward
+            map_relocated(0, @relocated[0], bank_of(0, mmu.p0_bank), mmu.p0_page)
+            map_relocated(1, @relocated[1], bank_of(1, mmu.p1_bank), mmu.p1_page)
+          end
+          reach_back(@relocated[2], mmu.p0_page, mmu.p0_bank, 0, forward)
+          reach_back(@relocated[3], mmu.p1_page, mmu.p1_bank, 1, forward)
+        end
+
+        def reach_back(window, page, bank, home, forward)
+          return if forward && page < 2
+          return unless bank_of(page, @mmu.cpu_bank) == bank
+
+          map_relocated(page, window, bank, home)
+        end
+
+        def map_relocated(page, window, bank, target)
+          window.base = (bank << 16) | (target << 8)
+          @read_pages[page] = @write_pages[page] = window
+        end
+
+        # The bank +page+ reaches when the CPU or a pointer asks for +bank+.
+        def bank_of(page, bank)
+          page < @mmu.common_low_pages || page >= @mmu.common_high_start ? 0 : bank
+        end
+      end
+    end
+  end
+end

data/lib/badline/c128/model.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The C128s badline builds by name: the chips each board has, and its
+    # video standard. The plastic C128D is a "c128" board with a 1571 built
+    # in. A VDC on either board can have 16K or 64K of RAM.
+    module Model
+      Profile = Data.define(:name, :vic_model, :cia_model, :sid_model, :region, :vdc_model, :vdc_ram_kb)
+
+      # The C128 and the plastic C128D, PAL: the 8566 VIC-IIe, 6526 CIAs,
+      # the 6581 SID and the 8563 VDC with 16K.
+      C128 = Profile.new(name: "c128", vic_model: :mos8566, cia_model: :mos6526, sid_model: :mos6581,
+                         region: Region::PAL, vdc_model: :mos8563, vdc_ram_kb: 16)
+
+      # The NTSC C128, with the 8564.
+      C128_NTSC = Profile.new(name: "c128ntsc", vic_model: :mos8564, cia_model: :mos6526, sid_model: :mos6581,
+                              region: Region::NTSC, vdc_model: :mos8563, vdc_ram_kb: 16)
+
+      # The metal C128DCR, PAL: 6526A CIAs, the 8580 SID and the 8568 VDC
+      # with 64K.
+      DCR = Profile.new(name: "c128dcr", vic_model: :mos8566, cia_model: :mos6526a, sid_model: :mos8580,
+                        region: Region::PAL, vdc_model: :mos8568, vdc_ram_kb: 64)
+
+      # The NTSC C128DCR, with the 8564.
+      DCR_NTSC = Profile.new(name: "c128dcrntsc", vic_model: :mos8564, cia_model: :mos6526a, sid_model: :mos8580,
+                             region: Region::NTSC, vdc_model: :mos8568, vdc_ram_kb: 64)
+
+      ALL = [C128, C128_NTSC, DCR, DCR_NTSC].freeze
+
+      def self.named(name)
+        model = ALL.find { |candidate| candidate.name == name }
+        raise ArgumentError, "no C128 model named #{name}" if model.nil?
+
+        model
+      end
+    end
+  end
+end

data/lib/badline/c128/modes.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # Following the MMU between C128 and C64 mode: the KERNAL traps go to
+    # the KERNAL the machine runs, C= held from power-on starts it in C64
+    # mode through the C128 KERNAL, and #active_screen tells a front end
+    # which screen the mode's editor prints to.
+    module Modes
+      # Holds C= down from power-on until the C128 KERNAL has taken the
+      # machine to C64 mode, as a user does to start a C128 in C64 mode.
+      # #on_init's handlers then wait for the C64 KERNAL's boot.
+      def hold_commodore_key
+        keyboard.press(:cbm)
+        @holding_commodore = true
+      end
+
+      # The screen the machine prints to: in C128 mode the screen editor's,
+      # :vdc while bit 7 of its 40/80 flag at $D7 is set, as GRAPHIC 5,
+      # ESC X and a reset with 40/80 DISPLAY down leave it, or :vic. C64
+      # mode has the VIC-IIe's alone.
+      def active_screen = mode == :c128 && ram.peek(0xd7).anybits?(0x80) ? :vdc : :vic
+
+      private
+
+      # The KERNAL the traps stand in for: the C128's in C128 mode, the C64's
+      # in C64 mode.
+      def trap_layout = mode == :c128 ? KernalTrap::C128_LAYOUT : KernalTrap::C64_LAYOUT
+
+      # The machine went to C64 mode or came back: the traps move to the
+      # KERNAL it now runs. C= held from power-on lets go, and #on_init's
+      # handlers wait for the C64 KERNAL to boot.
+      def mode_changed
+        layout = trap_layout
+        @capture_output&.layout = layout
+        if @drive
+          remove_kernal_traps
+          install_kernal_traps(layout)
+        end
+        return unless @holding_commodore && mode == :c64
+
+        keyboard.release(:cbm)
+        @holding_commodore = false
+        @init_threshold = @cycles + Computer::INIT_THRESHOLD if @cycles < @init_threshold
+      end
+    end
+  end
+end

data/lib/badline/c128/saved_state.rb

@@ -0,0 +1,121 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    MARKER = "C128"
+
+    # The model, the SID and the mode it resets into of the machine a State
+    # from #snapshot was taken of, the arguments C128.new takes.
+    def self.setup(state)
+      input = Snapshot::StateReader.new(state)
+      input.marker(MARKER)
+      input.check_stamp
+      SavedState.read_setup(input)
+    end
+
+    # A new machine, built as the one a State from #snapshot was taken of,
+    # at that state.
+    def self.restored(state)
+      setup = setup(state)
+      new(model: setup[0], sid_model: setup[1], mode: setup[2]).apply_state(state)
+    end
+
+    # The whole machine's state for a snapshot, as Computer's: the
+    # machine's own latches, FAST and TEST as they last took hold, the bus with its RAM, the MMU, the chips and
+    # the VDC, the CPU, the cartridge, the disk device 8 serves through the
+    # traps and a true 1541. The serial lines go back into the bus from the
+    # restored CIA 2. What the host holds stays out: the keyboard, the
+    # joysticks, CAPS LOCK and 40/80 DISPLAY, the traps and callbacks, and
+    # which chip renders.
+    module SavedState
+      SID_MODELS = %i[mos6581 mos8580].freeze
+      MODES = %i[c64 c128].freeze
+
+      # The model's name, the SID's model and the mode.
+      def self.read_setup(input)
+        name = input.string
+        known = Model::ALL.any? { |model| model.name == name }
+        raise Snapshot::FormatError, "the state names a C128 model badline doesn't know" unless known
+
+        sid_model = SID_MODELS.fetch(input.int)
+        [name, sid_model, MODES.fetch(input.int)]
+      rescue IndexError
+        raise Snapshot::FormatError, "the state names a SID or a mode badline doesn't know"
+      end
+
+      # How many more on_init handlers the machine a State was taken of had
+      # yet to run than this one has. Nil until the machine is restored.
+      attr_reader :init_handlers_lost
+
+      def snapshot
+        out = Snapshot::StateWriter.new
+        save_state(out)
+        out.state
+      end
+
+      # Takes the machine back to a State from #snapshot, trying it on a new
+      # machine first, so one that fails leaves this machine as it was.
+      # Raises Snapshot::FormatError for a state of another model or SID.
+      def restore(state)
+        check_setup(C128.setup(state))
+        C128.restored(state)
+        apply_state(state)
+      end
+
+      # Puts a State into the machine without trying it on a new one first.
+      def apply_state(state)
+        input = Snapshot::StateReader.new(state)
+        load_state(input)
+        raise Snapshot::FormatError, "the state goes on past the machine" unless input.finished?
+
+        self
+      end
+
+      def save_state(out)
+        out.marker(MARKER).stamp
+        out.string(@model.name).int(SID_MODELS.index(@sid.model)).int(@c64_built ? 0 : 1)
+        out.int(@cycles).int(@clock_bits).boolean(@nmi_asserted).boolean(@cartridge_nmi).boolean(@restore_pulse)
+        out.boolean(!@pending_keys.nil?)
+        out.ints(@pending_keys) if @pending_keys
+        out.int(@cycles <= init_threshold ? @init_handlers.length : 0)
+        save_cartridge(out)
+        @bus.save_state(out)
+        @cpu.save_state(out)
+        save_trap_drive(out)
+        save_serial_bus(out)
+      end
+
+      def load_state(input)
+        input.marker(MARKER)
+        input.check_stamp
+        check_setup(SavedState.read_setup(input))
+        @cycles = input.int
+        @clock_bits = input.int
+        @nmi_asserted = input.boolean?
+        @cartridge_nmi = input.boolean?
+        @restore_pulse = input.boolean?
+        @pending_keys = nil
+        @pending_keys = input.ints if input.boolean?
+        @init_handlers_lost = [input.int - @init_handlers.length, 0].max
+        load_cartridge(input)
+        @bus.load_state(input)
+        push_serial_lines
+        @cpu.load_state(input)
+        load_trap_drive(input)
+        load_serial_bus(input)
+        push_fast_serial
+      end
+
+      private
+
+      def check_setup(setup)
+        ours = [@model.name, @sid.model, @c64_built ? :c64 : :c128]
+        return if setup == ours
+
+        raise Snapshot::FormatError, "the state is of a #{setup.join(' with a ')}, not a #{ours.join(' with a ')}"
+      end
+    end
+
+    include SavedState
+  end
+end

data/lib/badline/c128/vdc/memory.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    class VDC
+      # The VDC's own DRAM: 16K of two 4416s (16K by 4) or 64K of 4164s or
+      # 4464s, behind the 16-bit addresses the VDC computes.
+      #
+      # The VDC drives an address onto the DRAM's pins as a row and a
+      # column, and R28 bit 4 picks the order (Programmer's Reference Guide,
+      # R28): set, for 64K parts, the row is A0-A7 and the column A8-A15;
+      # clear, for 4416s, the column pins carry A8, A8, A9-A13 and A15, and
+      # A14 goes nowhere. A 4416 has only six column lines and ignores the
+      # first and the last column pin. That gives the four layouts
+      # VDC/vdcdump's patterns.txt records from real machines: a 16K VDC in
+      # 64K mode sees A9-A14, so pages p, p ^ 1 and p ^ $80 are one page,
+      # and a 64K VDC in 16K mode sees page p at page
+      # (p & $80) | (p & $3E) << 1 | (p & 1) * 3.
+      class Memory
+        attr_reader :ram
+
+        def initialize(ram_kb)
+          @ram = Array.new(ram_kb * 1024, 0)
+          @layouts = [false, true].map { |mode64| Array.new(256) { |page| page_base(page, mode64) }.freeze }
+          @pages = @layouts[0]
+        end
+
+        # Selects 64K mode, R28 bit 4, or 16K mode.
+        def mode64=(on)
+          @pages = @layouts[on ? 1 : 0]
+        end
+
+        def fetch(addr) = @ram[@pages[(addr >> 8) & 0xff] | (addr & 0xff)]
+
+        def store(addr, value)
+          @ram[@pages[(addr >> 8) & 0xff] | (addr & 0xff)] = value
+        end
+
+        def clear!
+          @ram.fill(0)
+        end
+
+        private
+
+        def page_base(page, mode64)
+          pins = mode64 ? page : (page & 0x80) | ((page & 0x3e) << 1) | ((page & 1) * 3)
+          return pins << 8 if @ram.length == 0x10000
+
+          ((pins >> 1) & 0x3f) << 8
+        end
+      end
+    end
+  end
+end