badline 0.10.1 → 0.11.1

data/lib/badline/c128/vdc.rb

@@ -0,0 +1,268 @@
+# frozen_string_literal: true
+
+require "badline/c128/vdc/memory"
+require "badline/c128/vdc/window"
+require "badline/c128/vdc/painter"
+require "badline/c128/vdc/raster"
+
+module Badline
+  class C128
+    # The 8563 or 8568 VDC: the address register at $D600 and the data
+    # register at $D601, mirrored through $D6FF, in front of 37 internal
+    # registers (38 on the 8568), the VDC's own RAM (Memory) and its 80
+    # column RGBI display (Raster, Painter).
+    #
+    # A write to $D600 selects a register, and a read there gives the
+    # status: bit 7 ready for the next access, bit 5 in the vertical blank
+    # (outside the displayed rows), and bits 0-2 the version. $D601 reads
+    # and writes the selected register. A register past the last reads $FF.
+    # The light pen is left out.
+    #
+    # R18 and R19 hold the update address, high byte first, and a write to
+    # either reads the RAM there into R31. A read of R31 gives that byte,
+    # moves the address on and reads the next. A write of R31 stores the
+    # byte, moves the address on and reads the next. A write of R30 then
+    # repeats the last byte written over R30 more bytes (256 for 0), or with
+    # R24 bit 7 copies that many from R32/R33 on, and leaves the update
+    # address, and R32/R33 for a copy, after the last byte.
+    #
+    # The VDC runs on its own 16 MHz dot clock, a character clock every
+    # character width of dots (R22, doubled by R25 bit 4). The status reads
+    # not ready for ACCESS_CLOCKS character clocks after an access through
+    # R31 or a write of R18 or R19, and for one clock per byte a block write
+    # fills or two per byte it copies.
+    class VDC
+      include Addressable
+
+      STATUS_READY = 0x80
+      STATUS_VBLANK = 0x20
+      UPDATE_HIGH = 18
+      UPDATE_LOW = 19
+      WORD_COUNT = 30
+      DATA = 31
+      SOURCE_HIGH = 32
+      SOURCE_LOW = 33
+      DOT_CLOCK_HZ = 16_000_000
+
+      # Character clocks the status reads busy after an access through R31
+      # or a write of R18 or R19, fitted to the timings a flat C128 gave
+      # VDC/vdctiming (TimingResultsFlatC128.jpg).
+      ACCESS_CLOCKS = 30
+
+      # The version in the status bits: 1 for the 8563 R8 and R9, and 2 for
+      # the 8568.
+      VERSIONS = { mos8563: 1, mos8568: 2 }.freeze
+
+      # The 16 RGBI colours, red, green, blue and intensity from bit 3 down,
+      # as the Programmer's Reference Guide names them: 1100 is dark yellow.
+      PALETTE = Array.new(16) do |rgbi|
+        intensity = rgbi.anybits?(1) ? 0x55 : 0
+        red = (rgbi.anybits?(8) ? 0xaa : 0) + intensity
+        green = (rgbi.anybits?(4) ? 0xaa : 0) + intensity
+        blue = (rgbi.anybits?(2) ? 0xaa : 0) + intensity
+        (red << 16) | (green << 8) | blue
+      end.freeze
+
+      attr_reader :model, :registers
+
+      # Whether lines paint into the display as the raster passes them.
+      attr_reader :render
+
+      # +ram_kb+ is 16 or 64, and +clock_hz+ the CPU's clock the VDC is
+      # clocked against.
+      def initialize(model: :mos8563, ram_kb: 16, clock_hz: Region::PAL.clock_hz)
+        addressable_at(0xd600, length: 0x100)
+        @model = model
+        @version = VERSIONS.fetch(model)
+        @clock_hz = clock_hz
+        @registers = Array.new(model == :mos8568 ? 38 : 37, 0)
+        @memory = Memory.new(ram_kb)
+        @painter = Painter.new(@registers, @memory)
+        @raster = Raster.new(@registers, @painter)
+        @render = false
+        power_on!
+      end
+
+      # The dots a character takes, R22 bits 4-7 plus one, or R22 bits 4-7
+      # doubled in double-width mode.
+      def self.char_dots(registers)
+        width = registers[22] >> 4
+        registers[25].anybits?(0x10) ? [width, 1].max * 2 : width + 1
+      end
+
+      # The registers clear, the RAM clears and the raster starts a frame.
+      def power_on!
+        @registers.fill(0)
+        @memory.clear!
+        @memory.mode64 = false
+        @selected = 0
+        @read_latch = 0
+        @write_data = 0
+        @busy_until = 0
+        @phase = 0
+        @raster.reset!
+        @line_units = @raster.line_dots * @clock_hz
+        @painter.clear!
+      end
+
+      def ram = @memory.ram
+
+      def render=(on)
+        @render = on
+        @painter.clear!
+      end
+
+      # Everything the VDC holds but its display, which it paints again
+      # while it renders: the registers, the RAM, the data port and the
+      # raster. Whether it renders is the host's.
+      def save_state(out)
+        out.marker("VDC")
+        out.ints(@registers).blob(@memory.ram)
+        out.int(@selected).int(@read_latch).int(@write_data).int(@busy_until).int(@phase).int(@line_units)
+        @raster.save_state(out)
+        @painter.save_state(out)
+      end
+
+      def load_state(input)
+        input.marker("VDC")
+        input.ints_into(@registers)
+        input.blob_into(@memory.ram)
+        @memory.mode64 = @registers[28].anybits?(0x10)
+        @selected = input.int
+        @read_latch = input.int
+        @write_data = input.int
+        @busy_until = input.int
+        @phase = input.int
+        @line_units = input.int
+        @raster.load_state(input)
+        @painter.load_state(input)
+      end
+
+      # The frames the raster has finished, which the blinking counts.
+      def frame = @raster.frame
+
+      def display = @painter.display
+
+      def width = @painter.width
+
+      def height = @painter.height
+
+      def dirty_lines = @painter.dirty_lines
+
+      def clear_dirty_lines! = @painter.clear_dirty_lines!
+
+      def palette = PALETTE
+
+      # The [left, top, width, height] of the display a monitor shows.
+      def crop = @painter.crop(@raster.line_dots, @raster.frame_lines, @raster.sync_lines)
+
+      # The update address R18 and R19 hold.
+      def update_address = (@registers[UPDATE_HIGH] << 8) | @registers[UPDATE_LOW]
+
+      # Whether an access or a block operation is still under way.
+      def busy? = @phase < @busy_until
+
+      # One CPU cycle: the dot clock runs on, and a line ends once it has
+      # run a line's dots. The line's phase counts dots times the CPU's
+      # clock, DOT_CLOCK_HZ a cycle.
+      def cycle!
+        @phase += DOT_CLOCK_HZ
+        end_line if @phase >= @line_units
+      end
+
+      def peek(addr)
+        return status if offset_of(addr).even?
+        return read_ram if @selected == DATA
+
+        @selected < @registers.length ? @registers[@selected] : 0xff
+      end
+
+      def poke(addr, value)
+        return @selected = value & 0x3f if offset_of(addr).even?
+        return if @selected >= @registers.length
+
+        write_register(@selected, value)
+      end
+
+      private
+
+      def status
+        value = @version
+        value |= STATUS_READY unless busy?
+        value |= STATUS_VBLANK if @raster.vertical_blank?
+        value
+      end
+
+      def end_line
+        @phase -= @line_units
+        @busy_until -= @line_units
+        @raster.end_line(@render)
+        @line_units = @raster.line_dots * @clock_hz
+      end
+
+      def write_register(number, value)
+        @registers[number] = value
+        case number
+        when DATA then write_ram(value)
+        when WORD_COUNT then block(value.zero? ? 256 : value)
+        when UPDATE_HIGH, UPDATE_LOW then read_ahead
+        when 28 then @memory.mode64 = value.anybits?(0x10)
+        end
+      end
+
+      def read_ram
+        value = @read_latch
+        advance(1)
+        read_ahead
+        value
+      end
+
+      def write_ram(value)
+        @memory.store(update_address, value)
+        @write_data = value
+        advance(1)
+        read_ahead
+      end
+
+      def read_ahead
+        @read_latch = @memory.fetch(update_address)
+        busy(ACCESS_CLOCKS)
+      end
+
+      def block(count)
+        copy = @registers[24].anybits?(0x80)
+        copy ? copy_block(count) : fill_block(count)
+        @read_latch = @memory.fetch(update_address)
+        busy(copy ? count * 2 : count)
+      end
+
+      def fill_block(count)
+        address = update_address
+        count.times { |i| @memory.store(address + i, @write_data) }
+        advance(count)
+      end
+
+      def copy_block(count)
+        destination = update_address
+        source = (@registers[SOURCE_HIGH] << 8) | @registers[SOURCE_LOW]
+        count.times { |i| @memory.store(destination + i, @memory.fetch(source + i)) }
+        advance(count)
+        source = (source + count) & 0xffff
+        @registers[SOURCE_HIGH] = source >> 8
+        @registers[SOURCE_LOW] = source & 0xff
+      end
+
+      def advance(count)
+        address = (update_address + count) & 0xffff
+        @registers[UPDATE_HIGH] = address >> 8
+        @registers[UPDATE_LOW] = address & 0xff
+      end
+
+      # Holds the status busy for `clocks` character clocks after whatever
+      # is already under way.
+      def busy(clocks)
+        @busy_until = [@busy_until, @phase].max + (clocks * VDC.char_dots(@registers) * @clock_hz)
+      end
+    end
+  end
+end

data/lib/badline/c128.rb

@@ -0,0 +1,322 @@
+# frozen_string_literal: true
+
+require "badline/c128/model"
+require "badline/c128/mmu"
+require "badline/c128/vdc"
+require "badline/c128/mmu_pages"
+require "badline/c128/color_lines"
+require "badline/c128/banks"
+require "badline/c128/bus_state"
+require "badline/c128/bus"
+require "badline/c128/cpu"
+require "badline/c128/saved_state"
+require "badline/c128/keys"
+require "badline/c128/modes"
+require "badline/c128/drives"
+require "badline/c128/fast_serial"
+require "badline/drive1571"
+
+module Badline
+  # The Commodore 128: the 8502 on the VIC-IIe's clock, two CIAs, the SID,
+  # the VDC and its 80 column display, and 128K of RAM, which the 8722 MMU
+  # maps (C128::Bus).
+  #
+  # Built for C128 mode, it runs BASIC 7.0 and the C128 KERNAL from reset.
+  # The C128's Z80 runs first and hands the bus to the 8502, but here the
+  # 8502 starts at its reset vector, with the MMU as the Z80 leaves it.
+  # The KERNAL goes to C64 mode as on the C128, with C= held at reset, a
+  # C64 cartridge or GO64.
+  #
+  # Built for C64 mode, the default, it powers on in C64 mode, the state
+  # the C128 KERNAL reaches when C= is held at power-on, and a reset comes
+  # back there. It runs the C64's BASIC and KERNAL, so the C64's KERNAL
+  # traps, the keyboard buffer and CHROUT capture work unchanged.
+  #
+  # Where a C64 program sees it differ from a C64C: the 8502's P6 senses CAPS
+  # LOCK, $D02F drives the extra keyboard rows, $D030's FAST bit runs the
+  # CPU at 2 MHz and its TEST bit races the raster counter, the SID has no
+  # mirrors, and $D500-$D7FF holds the hidden MMU, the VDC and open bus.
+  class C128
+    include IntegerHelper
+    include KeyboardBuffer
+    include Computer::Attachments
+    include Computer::KernalTraps
+    include Keys
+    include Modes
+    include Drives
+    include FastSerial
+
+    # The C64's 8x8 matrix and the three rows K0-K2 select, in port B
+    # column order.
+    KEYBOARD_MATRIX = (Keyboard::C64_MATRIX + [
+      %i[help keypad8 keypad5 tab keypad2 keypad4 keypad7 keypad1],
+      %i[esc keypad_plus keypad_minus line_feed keypad_enter keypad6 keypad9 keypad3],
+      %i[alt keypad0 keypad_period crsr_up crsr_down crsr_left crsr_right no_scroll]
+    ]).freeze
+
+    # The cycle at which #on_init's handlers run, once the KERNAL of the
+    # mode the machine is built for has booted: the C64's as on a C64, or
+    # BASIC 7.0's, which is READY by then.
+    C128_INIT_THRESHOLD = 2_000_000
+
+    # The C128 KERNAL's keyboard buffer and its count.
+    C128_KEYBOARD_BUFFER = 0x034a
+    C128_KEYBOARD_COUNT = 0xd0
+
+    attr_reader :cpu, :cycles, :drive1541, :model, :init_threshold
+
+    # The path of the disk or directory device 8 serves through the traps
+    # (Computer::Attachments), or an empty one.
+    def mounted_path = @drive.nil? ? "" : @drive.path
+
+    def family = :c128
+
+    def address_bus = @bus
+
+    def region = @bus.region
+
+    def vic = @bus.vic
+
+    def cia1 = @bus.cia1
+
+    def cia2 = @bus.cia2
+
+    def sid = @bus.sid
+
+    def vdc = @bus.vdc
+
+    def mmu = @bus.mmu
+
+    def ram = @bus.ram
+
+    def keyboard = @bus.keyboard
+
+    def joystick1 = @bus.joystick1
+
+    def joystick2 = @bus.joystick2
+
+    def control_ports = @bus.control_ports
+
+    def datasette = @bus.datasette
+
+    # :c64 or :c128, the mode the MMU is in.
+    def mode = @bus.mmu.mode
+
+    def install_debug_register(&) = @bus.install_debug_register(&)
+
+    # +model+ names one of Model::ALL, and +sid_model+, when not nil, the
+    # SID in place of the model's. +mode+, :c64 or :c128, is the mode it
+    # powers on and resets into.
+    def initialize(model: "c128", sid_model: nil, mode: :c64, debug: false)
+      raise ArgumentError, "no C128 mode named #{mode}" unless %i[c64 c128].include?(mode)
+
+      @model = Model.named(model)
+      @c64_built = mode == :c64
+      @init_threshold = @c64_built ? Computer::INIT_THRESHOLD : C128_INIT_THRESHOLD
+      @holding_commodore = false
+      @bus = Bus.new(@model, sid_model: sid_model || @model.sid_model, mode:)
+      @cpu = CPU.new(@bus, debug:)
+      @vic = @bus.vic
+      @vic.open_bus = -> { @bus.ram.peek(@cpu.program_counter) }
+      @cia1 = @bus.cia1
+      @cia2 = @bus.cia2
+      @sid = @bus.sid
+      @vdc = @bus.vdc
+      @datasette = @bus.datasette
+      @cycles = 0
+      @clock_bits = 0
+      @nmi_asserted = false
+      @cartridge_nmi = false
+      @restore_pulse = false
+      @init_handlers = []
+      @pending_keys = nil
+      @capture_output = nil
+      init_drives
+      enter_c64_mode if @c64_built
+      @bus.on_mode_change { mode_changed }
+    end
+
+    # The chips clock ahead of the CPU, as on the C64. $D030's FAST and
+    # TEST bits take hold a cycle after the write that sets them: in FAST
+    # mode the CPU runs in both halves of the cycle (#clock_fast), and the
+    # TEST bit steps the raster counter in every cycle.
+    def cycle!
+      handle_init if @cycles == @init_threshold
+      feed_keyboard if @pending_keys
+
+      clock_bits = @clock_bits
+      @clock_bits = @vic.clock_bits
+      @vic.test_step! if clock_bits >= 0x02
+
+      @vic.cycle!
+      @cia1.cycle!
+      @cia2.cycle!
+      @sid.cycle!
+      @datasette.cycle!
+      @vdc.cycle!
+
+      @cpu.irq = @cia1.interrupted? || @vic.interrupted?
+
+      drive_nmi
+      clock_bits.odd? ? clock_fast : clock_cpu
+      clock_serial_bus
+
+      @cycles += 1
+    end
+
+    # Runs `count` cycles, one #cycle! after another.
+    def run_cycles(count)
+      i = 0
+      while i < count
+        cycle!
+        i += 1
+      end
+    end
+
+    # Runs cycles until the block returns true or the cycle count passes
+    # `limit`, checking before each cycle.
+    def run_until(limit)
+      cycle! until yield || @cycles > limit
+    end
+
+    def on_init(&block)
+      if @cycles < init_threshold
+        @init_handlers << block
+      else
+        block.call
+      end
+    end
+
+    # The clock, the raster and the crop of the VIC-IIe's region.
+    def timing
+      region = @bus.region
+      Timing.new(clock_hz: region.clock_hz, cycles_per_line: region.cycles_per_line,
+                 lines_per_frame: region.lines_per_frame, crop: region.crop, pixel_width: 1)
+    end
+
+    # The chip whose #display a front end shows: the VIC-IIe, or with
+    # :vdc the VDC, whose display paints only while its #render is on.
+    def video(chip = :vic) = chip == :vdc ? @vdc : @vic
+
+    # Renders the VDC's display, and not the VIC-IIe's, while a front end
+    # shows it, or with false the other way round.
+    def vdc_shown=(shown)
+      @vdc.render = shown
+      @vic.render = !shown
+    end
+
+    # The chip a front end records the machine's sound from.
+    def sound_source = @sid
+
+    def load_prg(data)
+      uint16(data[0], data[1]).tap do |load_addr|
+        ram.write(load_addr, data[2..])
+      end
+    end
+
+    # A cartridge goes in with the power off.
+    def attach_cartridge(cartridge)
+      connect_cartridge(cartridge)
+      power_cycle!
+    end
+
+    # RAM, the VIC and the VDC start from their power-on state, and the RES
+    # line resets everything else.
+    def power_cycle!
+      @vic.power_on!
+      @vdc.power_on!
+      @bus.power_on!
+      reset!
+      enter_c64_mode if @c64_built
+    end
+
+    # The RES line reaches the CPU and its port, the MMU, both CIAs, the
+    # SID, the cartridge port and, through the serial bus, the drives.
+    def reset!
+      @bus.reset!
+      @cia1.reset!
+      @cia2.reset!
+      @sid.reset!
+      @bus.cartridge&.reset
+      @drive&.reset!
+      @drive1541&.reset!
+      @drive1571&.reset!
+      @nmi_asserted = false
+      @cpu.reset!
+    end
+
+    # CHROUT is at $FFD2 in both KERNALs, and the trap follows the mode.
+    def capture_output
+      @capture_output ||= ChroutTrap.new(cpu:, bus: @bus, layout: trap_layout).tap do |trap|
+        cpu.install_trap(ChroutTrap::ADDRESS) { trap.call }
+      end
+    end
+
+    def inspect
+      "#<#{self.class.name} cycles=#{@cycles} cpu=(#{@cpu.inspect})>"
+    end
+
+    private
+
+    # The C128 KERNAL leaves $D02F at $FF, every extra keyboard row
+    # deselected, before it jumps to the C64's reset.
+    def enter_c64_mode
+      @vic.poke(0xd02f, 0xff)
+      @bus.control_ports.extra_rows = 0xff
+    end
+
+    # The NMI line is wired-OR between CIA 2, the cartridge and RESTORE,
+    # and the CPU takes an interrupt on its falling edge.
+    def drive_nmi
+      nmi = @cia2.interrupted? || @cartridge_nmi || @restore_pulse
+      @restore_pulse = false
+      @cpu.nmi = true if nmi && !@nmi_asserted
+      @nmi_asserted = nmi
+    end
+
+    # BA halts the CPU on a read cycle.
+    def clock_cpu
+      @cpu.pending_write? || !@vic.ba_low? ? @cpu.cycle! : @cpu.stall!
+    end
+
+    # The 8502 at 2 MHz takes both halves of the cycle, and BA no longer
+    # halts it. It leaves phi1 to the VIC in the refresh cycles, and an
+    # access to I/O, whose chips run at 1 MHz, waits for phi2. The VIC's
+    # fetches in the cycle see the bytes on the bus. In a phi1 the CPU
+    # spends waiting that is the byte it writes, or the last byte the bus
+    # held.
+    def clock_fast
+      phi1 = 0xff
+      unless @vic.refresh_cycle?
+        held = @bus.data
+        write = @cpu.pending_write?
+        @cpu.cycle!
+        if @bus.io_access?
+          data = @bus.data
+          return @vic.take_cpu_bus(write ? data : held, data, @bus.vic_access?)
+        end
+
+        phi1 = @bus.data
+      end
+      @cpu.cycle!
+      @vic.take_cpu_bus(phi1, @bus.data, @bus.vic_access?)
+    end
+
+    def handle_init
+      @init_handlers.each(&:call)
+    end
+
+    # The keyboard buffer of the KERNAL the machine runs: the C64's, or in
+    # C128 mode BASIC 7.0's.
+    def feed_keyboard
+      c64 = mode == :c64
+      count = c64 ? KeyboardBuffer::COUNT : C128_KEYBOARD_COUNT
+      return unless ram.peek(count).zero?
+
+      chunk = @pending_keys.shift(KeyboardBuffer::CAPACITY)
+      ram.write(c64 ? KeyboardBuffer::ADDRESS : C128_KEYBOARD_BUFFER, chunk)
+      ram.poke(count, chunk.length)
+      @pending_keys = nil if @pending_keys.empty?
+    end
+  end
+end

data/lib/badline/chrout_trap.rb

@@ -10,6 +10,9 @@ module Badline
 
     attr_reader :output
 
+    # The KERNAL layout whose mapping the trap checks.
+    attr_writer :layout
+
     def initialize(cpu:, bus:, layout:)
       @cpu = cpu
       @bus = bus

data/lib/badline/cia/fast_forward.rb

@@ -0,0 +1,42 @@
+# frozen_string_literal: true
+
+module Badline
+  class CIA
+    # Running a CIA a stretch of cycles at once, for Drive::Idle.
+    module FastForward
+      # Whether fast_forward can run the CIA: timer B stopped with nothing
+      # in its pipeline, no interrupt or acknowledge on its way, CNT where it
+      # was, the TOD clock stopped, and timer A either stopped, or free
+      # running (Timer#free_running?) with its interrupt masked and the
+      # serial port an idle input. Drive::Idle sleeps the 1571's CIA through
+      # such cycles, which its DOS leaves timer A running in.
+      def quiet?
+        return false unless @tb.idle? && @icr.quiet && @tod.quiet? && cnt_steady?
+
+        @ta.idle? ? @serial.idle : timer_a_free_running?
+      end
+
+      # Runs +cycles+ cycles at once while quiet?, as cycle! would: timer A's
+      # underflows flag in the ICR, and reach the serial port's underflow
+      # line.
+      def fast_forward(cycles)
+        @tod.fast_forward(cycles)
+        return if @ta.idle?
+
+        @icr.flag(:timer_a) if @ta.fast_forward(cycles).positive?
+        @serial.follow_underflow(@ta.underflowed)
+      end
+
+      private
+
+      # Timer A free running with its interrupt masked, and the serial port
+      # an idle input it only clocks.
+      def timer_a_free_running?
+        @ta.free_running? && !@control_a.serial_mode? && @icr.mask.value.nobits?(0x01) && @serial.drained?
+      end
+
+      # Whether CNT holds the level the last cycle sampled.
+      def cnt_steady? = @serial.cnt == @cnt_high && !@cnt_rise
+    end
+  end
+end

data/lib/badline/cia/serial.rb

@@ -79,6 +79,18 @@ module Badline
         @control.serial_mode?
       end
 
+      # Whether nothing is counting down or in the delay lines, so only
+      # timer A's underflows reach the register.
+      def drained? = idle?
+
+      # Takes timer A's underflow line as cycle! would have left it, with
+      # +underflowed+ its level on the last cycle, for a CIA run without
+      # the register in use (CIA#fast_forward).
+      def follow_underflow(underflowed)
+        @underflow_high = underflowed
+        @idle = !underflowed
+      end
+
       def cnt_in=(level)
         @cnt_in = level
         @cnt = level unless output?