badline 0.10.1 → 0.11.1

data/lib/badline/vic/display_state.rb

@@ -68,6 +68,12 @@ module Badline
       # True once AEC has followed BA down and the VIC owns the bus.
       def bus_taken?(column) = @ba ? column >= @ba + BA_DELAY : false
 
+      # The CPU kept the bus through the cycle before +column+, so on a bad
+      # line AEC falls BA_DELAY cycles after it at the earliest.
+      def keep_bus(column)
+        @ba &&= column
+      end
+
       def fetching?(column)
         @matched && column >= FETCH_FIRST && column <= DMA_LAST
       end
@@ -98,6 +104,12 @@ module Badline
 
       def new_line(line)
         @ba = nil
+        raster_step(line)
+      end
+
+      # The raster counter moved on to +line+, at the line's start or, under
+      # the VIC-IIe's TEST bit, within it.
+      def raster_step(line)
         @line_bits = line & 0b111
         @den_line = line == FIRST_LINE
         @in_window = line.between?(FIRST_LINE, LAST_LINE)

data/lib/badline/vic/registers.rb

@@ -150,6 +150,9 @@ module Badline
       def fast? = @iie && @bytes[0x30].anybits?(0x01)
       def test? = @iie && @bytes[0x30].anybits?(0x02)
 
+      # FAST and TEST as bits 0 and 1.
+      def clock_bits = @iie ? @bytes[0x30] & 0x03 : 0
+
       def raster_target = uint16(@bytes[0x12], (@bytes[0x11] & 0x80) >> 7)
 
       def latch_irq!(bit)

data/lib/badline/vic.rb

@@ -42,6 +42,11 @@ module Badline
     # GREEN_PALETTE on a monochrome monitor.
     attr_accessor :palette
 
+    # The line of #display the beam draws, which is the raster line unless
+    # the VIC-IIe's TEST bit has moved the raster counter on since the
+    # last vertical sync (#test_step!).
+    attr_reader :output_line
+
     # The parts a VICE snapshot reads and sets.
     attr_reader :registers, :display_state, :sequencer, :sprites, :character_buffer, :color_buffer,
                 :fetch_d011
@@ -86,6 +91,11 @@ module Badline
     HOOK_DISPLAY = 16
     HOOK_LAST = 32
 
+    # The vertical sync starts this many lines into the vertical blank,
+    # and lasts VSYNC_LINES.
+    VSYNC_DELAY = 3
+    VSYNC_LINES = 3
+
     # On the 6569 the DMA compares fall in columns 53 and 54 and the
     # display compare in column 57. A region whose sprite fetches run later
     # moves them with the fetches (Region::Profile#sprite_cycle).
@@ -125,6 +135,7 @@ module Badline
       @height = region.lines_per_frame
       @last_column = @columns_per_line - 1
       @last_line = @height - 1
+      @vsync_line = region.vblank[0] + VSYNC_DELAY
       layout_columns
       @blank_columns = Array.new(@columns_per_line) { |column| Region.blanked?(column, region.hblank) }.freeze
       @blank_lines = Array.new(@height) { |line| Region.blanked?(line, region.vblank) }.freeze
@@ -153,6 +164,7 @@ module Badline
 
       @column = 0
       @rasterline = 0
+      @output_line = 0
 
       @character_buffer = Array.new(40, 0)
       @color_buffer = Array.new(40, 0)
@@ -169,11 +181,13 @@ module Badline
       @lp_triggered = false
       @lp_low = false
       @raster_match = false
+      @test_wrap = false
     end
 
     # Everything the VIC holds between cycles: the beam, the fetch and
     # g-access pipeline, the light pen and raster latches, the finished
-    # lines, the registers and the display, sequencer and sprite logic.
+    # lines, on the VIC-IIe the display line and the TEST bit's wrap, the
+    # registers and the display, sequencer and sprite logic.
     # Whether it renders is the host's, and every line comes back dirty so
     # a front end repaints.
     def save_state(out)
@@ -184,6 +198,7 @@ module Badline
       out.int(@vic_bank.lines)
       out.blob(@character_buffer).blob(@color_buffer).booleans(@sprite_ba)
       @lines.each { |line| out.blob(line) }
+      out.int(@output_line).boolean(@test_wrap) if @iie
       @registers.save_state(out)
       @display_state.save_state(out)
       @sequencer.save_state(out)
@@ -195,6 +210,7 @@ module Badline
       load_beam(input)
       load_buffers(input)
       load_lines(input)
+      load_test_state(input) if @iie
       @registers.load_state(input)
       @display_state.load_state(input)
       @sequencer.load_state(input)
@@ -218,6 +234,7 @@ module Badline
       if @column == @columns_per_line
         finish_line!
         @column = 0
+        step_output_line
         @rasterline = @rasterline == @last_line ? 0 : @rasterline + 1
         check_raster_irq!(@rasterline.zero? ? @last_line : @rasterline)
       end
@@ -255,6 +272,57 @@ module Badline
     def fast? = @registers.fast?
     def test? = @registers.test?
 
+    # $D030's FAST and TEST bits as bits 0 and 1, which the C128 reads once
+    # a cycle.
+    def clock_bits = @registers.clock_bits
+
+    # Whether the cycle just run was one of the five refresh cycles, Bauer's
+    # 11-15, whose phi1 half the VIC keeps in the VIC-IIe's FAST mode.
+    # @column has already advanced, so it is the Bauer cycle less one.
+    def refresh_cycle? = @column.between?(10, 14)
+
+    # In the VIC-IIe's FAST mode the 8502 drives the bus in both halves of
+    # the cycle, and the VIC's accesses in the cycle just run latched what
+    # it put there. The g-access, or the idle access, took the byte of
+    # phi1. A c-access took the byte of phi2 as one made before AEC does
+    # (#fetch_character_data!): $ff for the video matrix, unless the CPU
+    # was reading or writing the VIC's own registers, and the byte's low
+    # nibble for colour. AEC can't follow BA down while the CPU runs at
+    # 2 MHz, so on a bad line it falls three cycles after FAST mode ends.
+    def take_cpu_bus(phi1, phi2, register_access)
+      slot = @g_tick
+      @g_data[slot] = phi1 unless @g_kind[slot] == G_BLANK
+      display_state = @display_state
+      display_state.keep_bus(@column)
+      return unless display_state.fetching?(@column.zero? ? @last_column : @column - 1)
+
+      vmli = display_state.vmli
+      @character_buffer[vmli] = register_access ? phi2 : 0xff
+      @color_buffer[vmli] = phi2 & 0x0f
+    end
+
+    # The VIC-IIe's TEST bit clocks the raster counter in every cycle, and
+    # the C128 calls this ahead of each cycle the bit is set in. The line's
+    # last cycle, whose own step it falls in with, adds nothing more. The
+    # counter takes two steps from the frame's last line to line 0, as line
+    # 0 reads the last line for its first cycle.
+    def test_step!
+      return if @column == @last_column
+
+      if @rasterline == @last_line
+        @test_wrap = !@test_wrap
+        return if @test_wrap
+
+        @rasterline = 0
+        @display_state.new_frame
+      else
+        @test_wrap = false
+        @rasterline += 1
+      end
+      @display_state.raster_step(@rasterline)
+      check_raster_irq!
+    end
+
     def peek(addr)
       i = offset_of(addr) % (2**6)
       case i
@@ -363,7 +431,7 @@ module Badline
 
     # Puts the beam at the start of `line`.
     def restore_line(line)
-      @rasterline = line
+      @rasterline = @output_line = line
       @column = 0
     end
 
@@ -400,7 +468,7 @@ module Badline
 
     def load_beam(input)
       @column = input.int
-      @rasterline = input.int
+      @rasterline = @output_line = input.int
       @cycles = input.int
       @pending_write = input.boolean?
       @g_tick = input.int
@@ -421,6 +489,13 @@ module Badline
       input.booleans_into(@sprite_ba)
     end
 
+    # The VIC-IIe's display line and TEST wrap, which only its TEST bit
+    # moves off the raster line.
+    def load_test_state(input)
+      @output_line = input.int
+      @test_wrap = input.boolean?
+    end
+
     # The display is the finished lines one after another.
     def load_lines(input)
       @lines.each_with_index do |line, number|
@@ -663,7 +738,7 @@ module Badline
     # or not there is a line to draw — then composite the active sprites
     # over the finished background and copy the line into the frame display.
     def finish_line!
-      return @sprites.finish_line(nil, @sequencer.fg) if vblank? || !@render
+      return finish_blank_line if vblank? || !@render
 
       composite = @sprites.active?
       @sequencer.apply_color_patches
@@ -672,12 +747,38 @@ module Badline
       @sequencer.apply_border if composite
 
       colors = @sequencer.colors
-      line = @lines[@rasterline]
+      output_line = @output_line
+      line = @lines[output_line]
       return if line == colors
 
       line[0, @width] = colors
-      @display[@rasterline * @width, @width] = colors
-      @dirty_lines[@rasterline] = true
+      @display[output_line * @width, @width] = colors
+      @dirty_lines[output_line] = true
+    end
+
+    # A blanked line paints nothing, and is never shown unless the TEST
+    # bit has moved the beam off the raster line, where it shows black.
+    def finish_blank_line
+      @sprites.finish_line(nil, @sequencer.fg)
+      return if @output_line == @rasterline || !@render
+
+      line = @output_line
+      @lines[line].fill(0)
+      @display.fill(0, line * @width, @width)
+      @dirty_lines[line] = true
+    end
+
+    # The display line the beam draws next follows the one before it, and
+    # a line that ends in the vertical sync puts it back on the raster
+    # line. Only the VIC-IIe's TEST bit moves the raster counter on between
+    # the two, so the lines it skips shift the picture up until the next
+    # sync.
+    def step_output_line
+      @output_line = if @rasterline.between?(@vsync_line, @vsync_line + VSYNC_LINES - 1)
+                       @rasterline + 1
+                     else
+                       @output_line == @last_line ? 0 : @output_line + 1
+                     end
     end
 
     def video_matrix(index)

data/lib/badline/vic20/attachments.rb

@@ -75,6 +75,12 @@ module Badline
         @serial_trap&.device = serial_trap_device
       end
 
+      # The true drive on the serial bus: the Drive1541, or nil.
+      def true_drive = @drive1541
+
+      # Plugs a Drive1541 in as device 8, and returns it.
+      def plug_true_drive = Drive1541.new.tap { |drive| attach_drive1541(drive) }
+
       # Unplugs the Drive1541, leaving the serial bus with nothing on it.
       def detach_drive1541
         return unless @drive1541

data/lib/badline/z80/arithmetic.rb

@@ -0,0 +1,117 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The ALU's 8- and 16-bit arithmetic. Bits 5 and 3 of F come from the
+    # result, except for CP, which takes them from the operand, and the
+    # 16-bit operations, which take them from the high byte.
+    module Arithmetic
+      private
+
+      # The eight operations an opcode's bits 5-3 pick: ADD ADC SUB SBC AND
+      # XOR OR CP.
+      def alu(operation, value)
+        case operation
+        when 0 then add_a(value, 0)
+        when 1 then add_a(value, @f & CF)
+        when 2 then @a = subtract(value, 0)
+        when 3 then @a = subtract(value, @f & CF)
+        when 4 then logic(@a & value, HF)
+        when 5 then logic(@a ^ value, 0)
+        when 6 then logic(@a | value, 0)
+        else compare(value)
+        end
+      end
+
+      def add_a(value, carry)
+        result = @a + value + carry
+        assign_flags(SZ53[result & 0xff] | (result >> 8) | ((@a ^ value ^ result) & HF) |
+                  (((@a ^ value ^ 0x80) & (@a ^ result) & 0x80) >> 5))
+        @a = result & 0xff
+      end
+
+      def subtract(value, carry)
+        result = @a - value - carry
+        assign_flags(SZ53[result & 0xff] | NF | ((result >> 8) & CF) | ((@a ^ value ^ result) & HF) |
+                  (((@a ^ value) & (@a ^ result) & 0x80) >> 5))
+        result & 0xff
+      end
+
+      def compare(value)
+        subtract(value, 0)
+        assign_flags((@f & ~XYF) | (value & XYF))
+      end
+
+      def logic(result, half)
+        @a = result
+        assign_flags(SZ53P[result] | half)
+      end
+
+      def increment(value)
+        result = (value + 1) & 0xff
+        assign_flags((@f & CF) | SZ53[result] | (result == 0x80 ? PF : 0) | (result.nobits?(0x0f) ? HF : 0))
+        result
+      end
+
+      def decrement(value)
+        result = (value - 1) & 0xff
+        assign_flags((@f & CF) | NF | SZ53[result] | (result == 0x7f ? PF : 0) | (value.nobits?(0x0f) ? HF : 0))
+        result
+      end
+
+      def add16(left, right)
+        result = left + right
+        @wz = (left + 1) & 0xffff
+        assign_flags((@f & (SF | ZF | PF)) | ((result >> 8) & XYF) | (((left ^ right ^ result) >> 8) & HF) |
+                  (result >> 16))
+        result & 0xffff
+      end
+
+      def adc16(right)
+        left = hl
+        result = left + right + (@f & CF)
+        @wz = (left + 1) & 0xffff
+        self.hl = result & 0xffff
+        assign_flags(word_flags(result) | (((left ^ right ^ result) >> 8) & HF) |
+                  (((left ^ right ^ 0x8000) & (left ^ result) & 0x8000) >> 13))
+      end
+
+      def sbc16(right)
+        left = hl
+        result = left - right - (@f & CF)
+        @wz = (left + 1) & 0xffff
+        self.hl = result & 0xffff
+        assign_flags(word_flags(result) | NF | (((left ^ right ^ result) >> 8) & HF) |
+                  (((left ^ right) & (left ^ result) & 0x8000) >> 13))
+      end
+
+      def word_flags(result)
+        ((result >> 8) & (SF | XYF)) | (result.nobits?(0xffff) ? ZF : 0) | ((result >> 16) & CF)
+      end
+
+      def daa
+        low = @a & 0x0f
+        carry = @f.anybits?(CF) || @a > 0x99 ? CF : 0
+        correction = (carry.zero? ? 0 : 0x60) | (@f.anybits?(HF) || low > 9 ? 0x06 : 0)
+        subtracting = @f.anybits?(NF)
+        half = daa_half(low, subtracting)
+        @a = (subtracting ? @a - correction : @a + correction) & 0xff
+        assign_flags(SZ53P[@a] | (@f & NF) | carry | half)
+      end
+
+      def daa_half(low, subtracting)
+        if subtracting
+          @f.anybits?(HF) && low < 6 ? HF : 0
+        else
+          low > 9 ? HF : 0
+        end
+      end
+
+      def neg
+        value = @a
+        @a = 0
+        @a = subtract(value, 0)
+      end
+    end
+  end
+end

data/lib/badline/z80/bit_page.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The CB page: rotates and shifts (quarter 0), BIT (1), RES (2) and SET
+    # (3) of the bit the row names, on the column's register or (HL). After
+    # DD or FD the operand is always (IX+d): the displacement comes before
+    # the opcode, and an opcode that names a register other than (HL) also
+    # copies the result into it.
+    module BitPage
+      private
+
+      def execute_bits(opcode)
+        operation = opcode >> 6
+        number = (opcode >> 3) & 7
+        index = opcode & 7
+        return bits_in_memory(operation, number, hl) if index == 6
+
+        value = register(index)
+        if operation == 1
+          bit(number, value, value)
+        else
+          set_register(index, bit_result(operation, number, value))
+        end
+      end
+
+      def execute_index_bits
+        displaced
+        opcode = fetch_byte
+        @cycles += 2
+        result = bits_in_memory(opcode >> 6, (opcode >> 3) & 7, @wz)
+        index = opcode & 7
+        set_plain_register(index, result) unless index == 6 || (opcode >> 6) == 1
+      end
+
+      def bits_in_memory(operation, number, address)
+        value = read_byte(address)
+        @cycles += 1
+        return bit(number, value, @wz >> 8) if operation == 1
+
+        result = bit_result(operation, number, value)
+        write_byte(address, result)
+        result
+      end
+
+      def bit_result(operation, number, value)
+        case operation
+        when 0 then shift(number, value)
+        when 2 then value & ~(1 << number) & 0xff
+        else value | (1 << number)
+        end
+      end
+    end
+  end
+end

data/lib/badline/z80/block_io.rb

@@ -0,0 +1,58 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # INI, IND, OUTI, OUTD and their repeating forms. B counts the bytes
+    # and sets S, Z, 5 and 3. The byte's bit 7 sets N, and adding it to C
+    # plus or minus one for INI and IND, or to L for OUTI and OUTD, sets H
+    # and C on a carry out and P/V from the parity of its low 3 bits
+    # exclusive-ored with B.
+    module BlockIO
+      private
+
+      def block_input(step, repeat)
+        @cycles += 1
+        port = bc
+        value = input(port)
+        @wz = (port + step) & 0xffff
+        @b = (@b - 1) & 0xff
+        write_byte(hl, value)
+        self.hl = (hl + step) & 0xffff
+        block_io_flags(value, value + ((@c + step) & 0xff), repeat)
+      end
+
+      def block_output(step, repeat)
+        @cycles += 1
+        value = read_byte(hl)
+        @b = (@b - 1) & 0xff
+        output(bc, value)
+        self.hl = (hl + step) & 0xffff
+        @wz = (bc + step) & 0xffff
+        block_io_flags(value, value + @l, repeat)
+      end
+
+      def block_io_flags(value, sum, repeat)
+        carry = sum > 0xff ? HF | CF : 0
+        assign_flags(SZ53[@b] | ((value >> 6) & NF) | carry | PARITY[(sum & 7) ^ @b])
+        return unless repeat && !@b.zero?
+
+        repeat_block
+        repeat_io_flags(value, carry)
+      end
+
+      def repeat_io_flags(value, carry)
+        flags = @f & ~HF
+        if carry.zero?
+          flags ^= PARITY[@b & 7] ^ PF
+        elsif value.anybits?(0x80)
+          flags ^= PARITY[(@b - 1) & 7] ^ PF
+          flags |= HF if @b.nobits?(0x0f)
+        else
+          flags ^= PARITY[(@b + 1) & 7] ^ PF
+          flags |= HF if @b.allbits?(0x0f)
+        end
+        assign_flags(flags)
+      end
+    end
+  end
+end

data/lib/badline/z80/block_transfers.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # LDI, LDD, CPI, CPD and their repeating forms. A repeating form that
+    # goes round again winds the program counter back to its ED and spends
+    # 5 T-states more, and bits 5 and 3 then come from the program
+    # counter's high byte.
+    module BlockTransfers
+      private
+
+      # ED A0-BB: the column picks LD, CP, IN or OUT, bit 3 counts down, and
+      # bit 4 repeats.
+      def block_operation(opcode)
+        step = opcode.nobits?(0x08) ? 1 : -1
+        repeat = opcode.anybits?(0x10)
+        case opcode & 3
+        when 0 then block_load(step, repeat)
+        when 1 then block_compare(step, repeat)
+        when 2 then block_input(step, repeat)
+        else block_output(step, repeat)
+        end
+      end
+
+      def block_load(step, repeat)
+        value = read_byte(hl)
+        write_byte(de, value)
+        @cycles += 2
+        self.hl = (hl + step) & 0xffff
+        self.de = (de + step) & 0xffff
+        self.bc = (bc - 1) & 0xffff
+        sum = value + @a
+        assign_flags((@f & (SF | ZF | CF)) | (sum & XF) | ((sum & 0x02) << 4) | (bc.zero? ? 0 : PF))
+        repeat_block if repeat && !bc.zero?
+      end
+
+      def block_compare(step, repeat)
+        value = read_byte(hl)
+        @cycles += 5
+        result = (@a - value) & 0xff
+        half = (@a ^ value ^ result) & HF
+        adjusted = result - (half >> 4)
+        self.hl = (hl + step) & 0xffff
+        self.bc = (bc - 1) & 0xffff
+        @wz = (@wz + step) & 0xffff
+        assign_flags((@f & CF) | NF | half | (SZ53[result] & (SF | ZF)) | (adjusted & XF) | ((adjusted & 0x02) << 4) |
+                  (bc.zero? ? 0 : PF))
+        repeat_block if repeat && !bc.zero? && !result.zero?
+      end
+
+      def repeat_block
+        @cycles += 5
+        @pc = (@pc - 2) & 0xffff
+        @wz = (@pc + 1) & 0xffff
+        assign_flags((@f & ~XYF) | ((@pc >> 8) & XYF))
+      end
+    end
+  end
+end

data/lib/badline/z80/bus_cycles.rb

@@ -0,0 +1,111 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The machine cycles that reach the bus. An opcode fetch (M1) takes 4
+    # T-states and refreshes a row of DRAM, which counts up the low 7 bits
+    # of R. A memory read or write takes 3, and an I/O read or write 4,
+    # one of them the wait state the Z80 inserts itself. Each calls the bus
+    # on its first T-state, and T-states the CPU spends inside lengthen
+    # the machine cycle before them.
+    module BusCycles
+      private
+
+      def fetch_opcode
+        opcode = @bus.fetch(@pc)
+        @pc = (@pc + 1) & 0xffff
+        refresh
+        @cycles += 4
+        opcode
+      end
+
+      # A halted CPU fetches from the address after HALT, again and again,
+      # and leaves the program counter there.
+      def idle_fetch
+        @bus.fetch(@pc)
+        refresh
+        @cycles += 4
+      end
+
+      def refresh
+        @r = (@r & 0x80) | ((@r + 1) & 0x7f)
+      end
+
+      def read_byte(address)
+        value = @bus.read(address)
+        @cycles += 3
+        value
+      end
+
+      def write_byte(address, value)
+        @bus.write(address, value)
+        @cycles += 3
+      end
+
+      def read_word(address)
+        low = read_byte(address)
+        low | (read_byte((address + 1) & 0xffff) << 8)
+      end
+
+      def write_word(address, value)
+        write_byte(address, value & 0xff)
+        write_byte((address + 1) & 0xffff, value >> 8)
+      end
+
+      def input(port)
+        value = @bus.input(port)
+        @cycles += 4
+        value
+      end
+
+      def output(port, value)
+        @bus.output(port, value)
+        @cycles += 4
+      end
+
+      # The byte after the opcode.
+      def fetch_byte
+        value = read_byte(@pc)
+        @pc = (@pc + 1) & 0xffff
+        value
+      end
+
+      def fetch_word
+        low = fetch_byte
+        low | (fetch_byte << 8)
+      end
+
+      def push(value)
+        @sp = (@sp - 1) & 0xffff
+        write_byte(@sp, value >> 8)
+        @sp = (@sp - 1) & 0xffff
+        write_byte(@sp, value & 0xff)
+      end
+
+      def pop
+        low = read_byte(@sp)
+        high = read_byte((@sp + 1) & 0xffff)
+        @sp = (@sp + 2) & 0xffff
+        low | (high << 8)
+      end
+
+      # The address of an (HL) operand, or of (IX+d), whose displacement is
+      # read from after the opcode and added in 5 T-states inside.
+      def operand_address
+        return hl if @prefix.zero?
+
+        displaced
+        @cycles += 5
+        @wz
+      end
+
+      # Reads the displacement of an (IX+d) or (IY+d) operand and leaves
+      # the address in WZ.
+      def displaced
+        offset = fetch_byte
+        offset -= 256 if offset > 127
+        @wz = (index_register + offset) & 0xffff
+      end
+    end
+  end
+end