axi_tdl 0.0.12 → 0.1.3

data/lib/public_atom_module/pipe_reg.v

@@ -0,0 +1,93 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/7/9 9:20:55
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module pipe_reg #(
+	parameter		DSIZE	= 8
+)(
+	input				clock			,
+	input				rst_n           ,
+	input				wr_en           ,
+	input [DSIZE-1:0]	indata          ,
+	input				low_empty       ,
+	output				valid           ,
+	output				curr_empty      ,
+	output				sum_empty       ,
+	output[DSIZE-1:0]	outdata         ,
+	output				high_reload 
+);
+
+/*
+table  
+higher_vld(wr_en)   curr_valid  low_empty :  next_valid   next_data  curr_empty sum_empty
+     1                  1           1     :      1           U           0        curr_empty | low_empty  
+     1                  1           0     :      1           K           0        curr_empty | low_empty
+     1                  0           1     :      1           U           0        curr_empty | low_empty
+     1                  0           0     :      1           U           0        curr_empty | low_empty
+     0                  1           1     :      0           C           1        curr_empty | low_empty
+     0                  1           0     :      1           K           0        curr_empty | low_empty
+     0                  0           1     :      0           C           1        curr_empty | low_empty
+     0                  0           0     :      0           C           1        curr_empty | low_empty
+*/
+
+reg					data_vld;
+reg[DSIZE-1:0]		data_reg;  
+reg					reload_reg;
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_vld	<= 1'b0;
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111,
+		3'b110,
+		3'b101,
+		3'b100,
+		3'b010:	data_vld	<= 1'b1;
+		default:data_vld	<= 1'b0;
+		endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	reload_reg	<= 1'b0;
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111:	reload_reg	<= 1'b1;
+		3'b110:	reload_reg	<= 1'b0;
+		3'b101:	reload_reg	<= 1'b1;
+		3'b100:	reload_reg	<= 1'b1;
+		3'b011:	reload_reg	<= 1'b1;
+		3'b010: reload_reg	<= 1'b0;
+		3'b001:	reload_reg	<= 1'b1;
+		3'b000:	reload_reg	<= 1'b1;
+		default:reload_reg	<= 1'b0;
+		endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_reg	<= {DSIZE{1'b0}};
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111:	data_reg	<= indata;
+		3'b110:	data_reg	<= data_reg;
+		3'b101:	data_reg	<= indata;
+		3'b100:	data_reg	<= indata;
+		3'b011:	data_reg	<= {DSIZE{1'b0}};
+		3'b010: data_reg	<= data_reg;
+		3'b001:	data_reg	<= {DSIZE{1'b0}};
+		3'b000:	data_reg	<= {DSIZE{1'b0}};
+		default:data_reg	<= {DSIZE{1'b0}};
+		endcase
+
+assign	curr_empty	= !data_vld;
+assign	outdata		= data_reg;
+assign	valid		= data_vld;
+assign	sum_empty	= curr_empty | low_empty;
+assign	high_reload	= reload_reg;
+
+endmodule
+	

data/lib/public_atom_module/pipe_reg_2write_ports.v

@@ -0,0 +1,84 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/7/9 9:20:55
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module pipe_reg_2write_port #(
+	parameter		DSIZE	= 8
+)(
+	input				clock			,
+	input				rst_n           ,
+	input				wr_en0          ,
+	input [DSIZE-1:0]	indata0         ,
+	input				wr_en1          ,
+	input [DSIZE-1:0]	indata1         ,
+	input				low_empty       ,
+	output				valid           ,
+	output				curr_empty      ,
+	output				sum_empty       ,
+	output[DSIZE-1:0]	outdata          
+);
+
+wire[DSIZE-1:0]		indata;
+wire				wr_en;
+
+assign indata	= wr_en0? indata0 : (wr_en1? indata0 :{DSIZE{1'b0}});
+assign wr_en	= wr_en0 | wr_en1;
+
+/*
+table  
+higher_vld(wr_en)   curr_valid  low_empty :  next_valid   next_data  curr_empty sum_empty
+     1                  1           1     :      1           U           0        curr_empty | low_empty  
+     1                  1           0     :      1           K           0        curr_empty | low_empty
+     1                  0           1     :      1           U           0        curr_empty | low_empty
+     1                  0           0     :      1           U           0        curr_empty | low_empty
+     0                  1           1     :      0           C           1        curr_empty | low_empty
+     0                  1           0     :      1           K           0        curr_empty | low_empty
+     0                  0           1     :      0           C           1        curr_empty | low_empty
+     0                  0           0     :      0           C           1        curr_empty | low_empty
+*/
+
+reg					data_vld;
+reg[DSIZE-1:0]		data_reg;
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_vld	<= 1'b0;
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111,
+		3'b110,
+		3'b101,
+		3'b100,
+		3'b010:	data_vld	<= 1'b1;
+		default:data_vld	<= 1'b0;
+		endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_reg	<= {DSIZE{1'b0}};
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111:	data_reg	<= indata;
+		3'b110:	data_reg	<= data_reg;
+		3'b101:	data_reg	<= indata;
+		3'b100:	data_reg	<= indata;
+		3'b011:	data_reg	<= {DSIZE{1'b0}};
+		3'b010: data_reg	<= data_reg;
+		3'b001:	data_reg	<= {DSIZE{1'b0}};
+		3'b000:	data_reg	<= {DSIZE{1'b0}};
+		default:data_reg	<= {DSIZE{1'b0}};
+		endcase
+
+
+assign	curr_empty	= !data_vld;
+assign	outdata		= data_reg;
+assign	valid		= data_vld;
+assign	sum_empty	= curr_empty | low_empty;
+
+endmodule
+	

data/lib/public_atom_module/sim/clock_rst_verb.sv

@@ -0,0 +1,54 @@
+/**********************************************
+______________________________________________
+_______  ___   ___          ___   __   _    _
+_______ |     |   | |\  /| |___  |  \  |   /_\
+_______ |___  |___| | \/ | |___  |__/  |  /   \
+_______________________________________________
+descript:
+author : Young
+Version: VERB.0.0
+	create a module for it
+creaded: 2015/10/16 10:50:52
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* data_inf = "true" *)
+module clock_rst_verb #(
+	parameter bit		ACTIVE			= 1,
+	parameter longint	PERIOD_CNT		= 0,
+	parameter			RST_HOLD		= 5,
+	parameter real		FreqM			= 100
+)(
+	output			clock,
+	output			rst_x
+);
+
+bit clk_pause = 1;
+bit	clock_reg;
+bit	rst_reg;
+
+longint ccnt = 0;
+
+initial begin
+	clk_pause	= 1;
+	clock_reg	= 0;
+	rst_reg		= ACTIVE;
+	#(1000/FreqM*2);
+	clk_pause	= 0;
+	repeat(RST_HOLD)
+		@(posedge clock_reg);
+	rst_reg		= ~rst_reg;
+end
+
+always #(1000/FreqM/2) begin
+	if(clk_pause == 0 && (PERIOD_CNT==0 || ccnt < PERIOD_CNT))
+		clock_reg	= ~clock_reg;
+end
+
+always@(posedge clock)
+	ccnt	<= ccnt + 1;
+
+assign	clock	= clock_reg;
+assign	rst_x	= rst_reg;
+
+endmodule

data/lib/public_atom_module/sim/latency_long_tb.sv

@@ -0,0 +1,49 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/12/1 14:28:31
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_long_tb;
+
+bit		clock = 0;
+bit		rst_n = 0;
+
+always #5 clock	= ~clock;
+
+initial begin
+	repeat(10)	@(posedge clock);
+	rst_n	= 1;
+end
+
+bit		d;
+
+initial begin
+	d = 0   ;
+	wait(rst_n);
+	repeat(20) @(posedge clock);
+	d = 1;
+	repeat(1) @(posedge clock);
+	d = 0;
+end
+
+latency_long #(
+	.LAT		(5		)
+)latency_long_inst(
+	.clock 		(clock		),
+	.rst_n	    (rst_n      ),
+	.d          (d          ),
+	.q          (           )
+);
+
+
+endmodule
+
+
+
+

data/lib/public_atom_module/sim/latency_long_tb.sv.bak

@@ -0,0 +1,49 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/12/1 14:28:31
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_long_tb;
+
+bit		clock = 0;
+bit		rst_n = 0;
+
+always #5 clock	= ~clock;
+
+initial begin
+	repeat(10)	@(posedge clock);
+	rst_n	= 1;
+end
+
+bit		d;
+
+initial begin
+	d = 0   ;
+	wait(rst_n);
+	repeat(20) @(posedge clock);
+	d = 1;
+	repeat(10) @(posedge clock);
+	d = 0;
+end
+
+latency_long #(
+	.LAT		(5		)
+)latency_long_inst(
+	.clock 		(clock		),
+	.rst_n	    (rst_n      ),
+	.d          (d          ),
+	.q          (           )
+);
+
+
+endmodule
+
+
+
+

data/lib/tdl/Logic/logic_edge.rb

@@ -1,7 +1,7 @@
 
 
 class Logic     ## EDGE METHOD
-    def raising(cnt:1,clock:nil,reset:nil)
+    def raising(cnt:1,clock:nil,reset: 1.b1 )
 
         # if cnt==1 && clock == nil && reset==nil && @raising_record
         #     return @raising_record

data/lib/tdl/auto_script/autogensdl.rb

@@ -232,10 +232,21 @@ class AutoGenSdl
     end
 
     def gen_file
-        @autof = File.open(@autof_name,"w") do |f|
-            f.puts gen_head
-            f.puts gen_content
-            # f.puts "sm.origin_sv = true"
+        unless File.exist?(@autof_name) 
+            @autof = File.open(@autof_name,"w") do |f|
+                f.print gen_head
+                f.print gen_content
+                # f.puts "sm.origin_sv = true"
+            end
+        else 
+            _old_str  = File.open(@autof_name).read
+            _new_str = gen_head+gen_content
+            if _old_str != _new_str
+                @autof = File.open(@autof_name,"w") do |f|
+                    f.print _new_str
+                    # f.puts "sm.origin_sv = true"
+                end
+            end
         end
     end
 
@@ -255,7 +266,7 @@ self.path = File.expand_path(__FILE__)
     end
 
     def gen_content
-        (@param_port_inst+@signals_ports_inst+@inf_ports_inst + ["end"]).join("\n")
+        (@param_port_inst+@signals_ports_inst+@inf_ports_inst + ["end\n\n"]).join("\n")
     end
 
 

data/lib/tdl/axi4/axi4_interconnect_verb.rb

@@ -66,7 +66,34 @@ class Axi4
             # next unless e.is_a? Axi4
             if e.is_a? Axi4
                 e.band_params_from(self)
-                @interconnect_up_streams << e
+                
+                ## e is a Vector 
+                if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
+                    # require_hdl 'axi4_direct_B1.sv'
+                    require_hdl 'axi4_direct_verc.sv'
+
+                    e.dimension[0].times do |xi|
+                        _ne = e.copy(name: "#{e.inst_name}_toM_#{xi}")
+                        # _ne << e[xi]
+                        # belong_to_module.Instance('axi4_direct_B1',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
+                        #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                        #     h.slaver_inf        e[xi]
+                        #     h.master_inf        _ne
+                        # end
+
+                        belong_to_module.Instance('axi4_direct_verc',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
+                            h.param.MODE            "#{_ne.mode}_to_#{_ne.mode}"    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                            h.param.SLAVER_MODE     _ne.mode    #    //
+                            h.param.MASTER_MODE     _ne.mode    #    //
+                            h.slaver_inf        e[xi]
+                            h.master_inf        _ne
+                        end
+                
+                        @interconnect_up_streams << _ne 
+                    end    
+                else
+                    @interconnect_up_streams << e
+                end
             else
                 raise TdlError.new("When use `<<` for axi4's M2S ,argvs must be axi4 too.\nOtherwise use `naxi4_mix_interconnect_M2S` directly")
             end
@@ -218,16 +245,27 @@ class Axi4
                 else
                     mode_str = "ONLY_READ_to_BOTH"
                 end
-                # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
-                    # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                    h.slaver        lo
-                    h.master        "#{sub_name}[#{index}]".to_nq
+                # require_hdl 'axi4_direct_B1.sv'
+                # # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
+                # belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
+                #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                #     h.slaver_inf        lo
+                #     h.master_inf        "#{sub_name}[#{index}]".to_nq
+                # end
+
+                require_hdl 'axi4_direct_verc.sv'
+                belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
+                    h.param.MODE            mode_str    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                    h.param.SLAVER_MODE     (wr_lg ? "ONLY_WRITE" : "ONLY_READ")    #    //
+                    h.param.MASTER_MODE     "BOTH"    #    //
+                    h.slaver_inf        lo
+                    h.master_inf        "#{sub_name}[#{index}]".to_nq
                 end
 
             else
                 los = short_only.pop
                 @_long_slim_to_wide.delete los
+                require_hdl 'axi4_combin_wr_rd_batch.sv'
                 if wr_lg
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:lo,rd_slaver:los,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
                     belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
@@ -250,10 +288,11 @@ class Axi4
         @_long_slim_to_wide.each do |e|
             mode_str = e.mode + "_to_BOTH"
             # Axi4.axi4_direct_a1(mode:mode_str,slaver:e,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
+            require_hdl 'axi4_direct_B1.sv'
             belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_inst_long_to_wide_#{sub_name}") do |h|
                 # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                h.slaver        e
-                h.master        "#{sub_name}[#{index}]".to_nq
+                h.slaver_inf        e
+                h.master_inf        "#{sub_name}[#{index}]".to_nq
             end
             index = index + 1
         end
@@ -309,8 +348,8 @@ class Axi4
 "\naxi4_direct_B1 /* #(
     .MODE       (\"#{_str}\")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )*/ iterconnect_direct_A1_#{name}_instMM(
-/* axi_inf.slaver */  .slaver   (sub_axi_#{name}_inf[0]),
-/* axi_inf.master */  .master   (#{name})
+/* axi_inf.slaver */  .slaver_inf   (sub_axi_#{name}_inf[0]),
+/* axi_inf.master */  .master_inf   (#{name})
 );\n"
         end