axi_tdl 0.0.12 → 0.1.3

data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb

@@ -1,5 +1,6 @@
 # require_relative "../prj_lib"
-require_hdl File.join(__dir__,"../AXI_stream/axis_length_split_with_addr.sv")
+require_hdl "axis_length_split_with_addr.sv"
+require_hdl 'axi_stream_wide_fifo.sv'
 new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
 new_m.target_class = AxiStream
 

data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -56,7 +56,7 @@ logic stream_en;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1842 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1342 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
@@ -93,13 +93,13 @@ independent_clock_fifo #(
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
 /* output                        */.stream_en     (stream_en           ),
 /* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1842 )
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1342 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R1910_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R1842 ),
+)vcs_axi4_comptable_axi_wr_aux_R700_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R1342 ),
 /* output */.to     (axi_wr              )
 );
 axis_valve_with_pipe #(
@@ -111,30 +111,30 @@ axis_valve_with_pipe #(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-always_ff@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
+always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
     if(~axis_in.aresetn)begin
-         id <= 0;
+        id <= 0;
     end
     else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
-         id <= ( id+1);
+        id <= (id+1);
     end
     else begin
-         id <= id;
+        id <= id;
     end
 end
 
-assign  addr_s = addr_cur;
-assign  len_s = split_out.axis_tcnt;
-assign  id_add_len_in.axis_tvalid = ~fifo_empty;
-assign  id_add_len_in.axis_tdata = fifo_rdata;
-assign  id_add_len_in.axis_tlast = "1'b1";
-assign  fifo_rd_en = id_add_len_in.axis_tready;
+assign addr_s = addr_cur;
+assign len_s = split_out.axis_tcnt;
+assign id_add_len_in.axis_tvalid = ~fifo_empty;
+assign id_add_len_in.axis_tdata = fifo_rdata;
+assign id_add_len_in.axis_tlast = "1'b1";
+assign fifo_rd_en = id_add_len_in.axis_tready;
 
-assign  axi_wr.axi_wdata = pipe_axis.axis_tdata;
-assign  axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
-assign  axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
-assign  axi_wr.axi_wlast = pipe_axis.axis_tlast;
-assign  pipe_axis.axis_tready = axi_wr.axi_wready;
-assign  axi_wr.axi_bready = 1'b1;
+assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
+assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
+assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
+assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
+assign pipe_axis.axis_tready = axi_wr.axi_wready;
+assign axi_wr.axi_bready = 1'b1;
 
 endmodule

data/lib/axi/AXI_stream/axi_stream_split_channel.rb

@@ -20,7 +20,13 @@ TdlBuild.axi_stream_split_channel(__dir__) do
             new_last    <= 1.b0
         end
         ELSE do 
-            new_last    <= (origin_inf.axis_tcnt == (split_len - 2)).and(origin_inf.vld_rdy)
+            IF origin_inf.vld_rdy do 
+                new_last    <= (origin_inf.axis_tcnt == (split_len - 2))
+            end
+            ELSE do 
+                new_last    <= new_last
+            end
+            # new_last    <= (origin_inf.axis_tcnt == (split_len - 2)).and(origin_inf.vld_rdy)
 
             IF origin_inf.vld_rdy_last do 
                 addr    <= 1.b0 

data/lib/axi/AXI_stream/axi_stream_split_channel.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-04-03 12:04:15 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -55,22 +55,22 @@ axis_direct  axis_direct_end_inf_inst0 (
 );
 //-------- CLOCKs Total 3 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_8,cc_same_8;
-integer cc_afreq_8,cc_bfreq_8;
-ClockSameDomain CheckPClock_inst_8(
-/*  input         */      .aclk     (origin_inf.aclk        ),
-/*  input         */      .bclk     (first_inf.aclk         ),
-/*  output logic  */      .done     (cc_done_8),
-/*  output logic  */      .same     (cc_same_8),
-/*  output integer */     .aFreqK   (cc_afreq_8),
-/*  output integer */     .bFreqK   (cc_bfreq_8)
+logic cc_done_0,cc_same_0;
+integer cc_afreq_0,cc_bfreq_0;
+ClockSameDomain CheckPClock_inst_0(
+/*  input         */      .aclk     (origin_inf.aclk),
+/*  input         */      .bclk     (first_inf.aclk),
+/*  output logic  */      .done     (cc_done_0),
+/*  output logic  */      .same     (cc_same_0),
+/*  output integer */     .aFreqK   (cc_afreq_0),
+/*  output integer */     .bFreqK   (cc_bfreq_0)
 );
 
 initial begin
-    wait(cc_done_8);
-    assert(cc_same_8)
+    wait(cc_done_0);
+    assert(cc_same_0)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_0, 1000000.0/cc_bfreq_0);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -80,22 +80,22 @@ end
 //---<< CheckClock >>----------------
 
 //--->> CheckClock <<----------------
-logic cc_done_9,cc_same_9;
-integer cc_afreq_9,cc_bfreq_9;
-ClockSameDomain CheckPClock_inst_9(
-/*  input         */      .aclk     (origin_inf.aclk        ),
-/*  input         */      .bclk     (end_inf.aclk           ),
-/*  output logic  */      .done     (cc_done_9),
-/*  output logic  */      .same     (cc_same_9),
-/*  output integer */     .aFreqK   (cc_afreq_9),
-/*  output integer */     .bFreqK   (cc_bfreq_9)
+logic cc_done_1,cc_same_1;
+integer cc_afreq_1,cc_bfreq_1;
+ClockSameDomain CheckPClock_inst_1(
+/*  input         */      .aclk     (origin_inf.aclk),
+/*  input         */      .bclk     (end_inf.aclk),
+/*  output logic  */      .done     (cc_done_1),
+/*  output logic  */      .same     (cc_same_1),
+/*  output integer */     .aFreqK   (cc_afreq_1),
+/*  output integer */     .bFreqK   (cc_bfreq_1)
 );
 
 initial begin
-    wait(cc_done_9);
-    assert(cc_same_9)
+    wait(cc_done_1);
+    assert(cc_same_1)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_1, 1000000.0/cc_bfreq_1);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -105,34 +105,39 @@ end
 //---<< CheckClock >>----------------
 
 //======== CLOCKs Total 3 ======================
-assign  clock = origin_inf.aclk;
-assign  rst_n = origin_inf.aresetn;
+assign clock = origin_inf.aclk;
+assign rst_n = origin_inf.aresetn;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         addr <= 1'b0;
-         new_last <= 1'b0;
+        addr <= 1'b0;
+        new_last <= 1'b0;
     end
     else begin
-         new_last <= ( origin_inf.axis_tcnt==( split_len-2)&& origin_inf.axis_tvalid && origin_inf.axis_tready);
+        if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
+            new_last <= origin_inf.axis_tcnt==(split_len-2);
+        end
+        else begin
+            new_last <= new_last;
+        end
         if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
-             addr <= 1'b0;
+            addr <= 1'b0;
         end
-        else if( origin_inf.axis_tcnt==( split_len-1)&& origin_inf.axis_tvalid && origin_inf.axis_tready)begin
-             addr <= 1'b1;
+        else if(origin_inf.axis_tcnt==(split_len-1)&&origin_inf.axis_tvalid && origin_inf.axis_tready)begin
+            addr <= 1'b1;
         end
         else begin
-             addr <= addr;
+            addr <= addr;
         end
     end
 end
 
-assign  origin_inf_add_last.axis_tdata = origin_inf.axis_tdata;
-assign  origin_inf_add_last.axis_tvalid = origin_inf.axis_tvalid;
-assign  origin_inf_add_last.axis_tuser = origin_inf.axis_tuser;
-assign  origin_inf_add_last.axis_tkeep = origin_inf.axis_tkeep;
-assign  origin_inf_add_last.axis_tlast = ( origin_inf.axis_tlast|new_last);
-assign  origin_inf.axis_tready = origin_inf_add_last.axis_tready;
+assign origin_inf_add_last.axis_tdata = origin_inf.axis_tdata;
+assign origin_inf_add_last.axis_tvalid = origin_inf.axis_tvalid;
+assign origin_inf_add_last.axis_tuser = origin_inf.axis_tuser;
+assign origin_inf_add_last.axis_tkeep = origin_inf.axis_tkeep;
+assign origin_inf_add_last.axis_tlast = origin_inf.axis_tlast|new_last;
+assign origin_inf.axis_tready = origin_inf_add_last.axis_tready;
 
 
 axis_direct  axis_direct_first_inf_instMM (

data/lib/axi/AXI_stream/axis_head_cut_verb.sv

@@ -34,11 +34,15 @@ always_ff@(posedge axis_in.aclk, negedge axis_in.aresetn)
         if(axis_in.axis_tvalid && axis_in.axis_tready)begin 
             if(axis_in.axis_tlast)
                     ex_viliad   <= 1'b0;
+            else if(length == 16'd0)
+                    ex_viliad   <= 1'b1;
             else if(axis_in.axis_tcnt >= length - 1'b1)
                     ex_viliad   <= 1'b1;
             else    ex_viliad   <= ex_viliad;
-        end else begin 
-            ex_viliad   <= ex_viliad;
+        end else begin
+            if(axis_in.axis_tcnt == '0 && length == 16'd0)
+                    ex_viliad   <= 1'b1;
+            else    ex_viliad   <= ex_viliad;
         end
     end
 

data/lib/axi/AXI_stream/axis_head_cut_verc.sv

@@ -5,14 +5,14 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
 
 module axis_head_cut_verc #(
     parameter  BYTE_BITS = 8,
-    parameter  DX        =  origin_inf.DSIZE/BYTE_BITS
+    parameter  DX        = (origin_inf.DSIZE / BYTE_BITS)
 )(
     input [9:0]             bytes,
     axi_stream_inf.slaver   origin_inf,
@@ -45,7 +45,7 @@ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin
 axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR671 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR774 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_pipe_sync_seam #(
@@ -122,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
 axis_head_cut_verb last_cut_inst(
 /* input                 */.length   (16'd1               ),
 /* axi_stream_inf.slaver */.axis_in  (origin_inf_ss_E0_CH ),
-/* axi_stream_inf.master */.axis_out (out_inf_branchR671  )
+/* axi_stream_inf.master */.axis_out (out_inf_branchR774  )
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
@@ -136,7 +136,7 @@ axis_direct  axis_direct_out_inf_inst0 (
 );
 
 axis_direct  axis_direct_out_inf_inst1 (
-/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR671),
+/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR774),
 /*  axi_stream_inf.master*/ .master (sub_out_inf[1])
 );
 
@@ -154,57 +154,57 @@ axis_direct  axis_direct_origin_inf_cut_mix_inst1 (
 /*  axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[1])
 );
 initial begin
-    assert( DX<17)else begin
-         $error("param.DX<%0d> !< 17",DX);
-         $stop;
+    assert(DX<17)else begin
+        $error("param.DX<%0d> !< 17",DX);
+        $stop;
     end
 end
 
-assign  clock = origin_inf.aclk;
-assign  rst_n = origin_inf.aresetn;
+assign clock = origin_inf.aclk;
+assign rst_n = origin_inf.aresetn;
 
 always_comb begin 
-     bytes_x_tmp = '0;
+    bytes_x_tmp = '0;
     for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
-        if( bytes<DX*(10-gvar_cc_1))begin
-             bytes_x_tmp = ( ( 10-1)-gvar_cc_1);
+        if(bytes<DX*(10-gvar_cc_1))begin
+            bytes_x_tmp = (10-1)-gvar_cc_1;
         end
     end
 end
 
-assign  origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
-assign  {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
-assign  bytes_x_sub_nDx_tmp = ( bytes_Q-( bytes_x*DX));
-assign  origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
-assign  {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
-assign  origin_sync_info[2] = {10'd0,route_addr_tmp};
-assign  route_addr = origin_sync_info_out[2][1:0];
+assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
+assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
+assign bytes_x_sub_nDx_tmp = bytes_Q-(bytes_x*DX);
+assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
+assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
+assign origin_sync_info[2] = {10'd0,route_addr_tmp};
+assign route_addr = origin_sync_info_out[2][1:0];
 
 always_comb begin 
-    if( bytes_QQ=='0)begin
-         route_addr_tmp = 2'd0;
+    if(bytes_QQ=='0)begin
+        route_addr_tmp = 2'd0;
     end
-    else if( bytes_x_Q=='0)begin
-         route_addr_tmp = 2'd2;
+    else if(bytes_x_Q=='0)begin
+        route_addr_tmp = 2'd2;
     end
-    else if( bytes_x_sub_nDx=='0)begin
-         route_addr_tmp = 2'd1;
+    else if(bytes_x_sub_nDx=='0)begin
+        route_addr_tmp = 2'd1;
     end
     else begin
-         route_addr_tmp = 2'd1;
+        route_addr_tmp = 2'd1;
     end
 end
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         fifo_wr_en <= 1'b0;
+        fifo_wr_en <= 1'b0;
     end
     else begin
-         fifo_wr_en <= ( origin_inf.axis_tcnt=='0&& origin_inf.axis_tvalid && origin_inf.axis_tready);
+        fifo_wr_en <= (origin_inf.axis_tcnt=='0&&origin_inf.axis_tvalid && origin_inf.axis_tready);
     end
 end
 
-assign  shift_sel_pre = ( DX-bytes_x_sub_nDx);
+assign shift_sel_pre = DX-bytes_x_sub_nDx;
 
 
 //----->> fifo_wr_en LAST DELAY <<------------------

data/lib/axi/AXI_stream/axis_insert_copy.rb

@@ -1,4 +1,4 @@
-
+require_hdl 'axis_connect_pipe.sv'
 
 TdlBuild.axis_insert_copy(__dir__) do 
     input[16]               - 'insert_seed'     ## 0 need first
@@ -37,15 +37,29 @@ TdlBuild.axis_insert_copy(__dir__) do
                 IF in_inf.vld_rdy_last do 
                     insert_tri  <= 1.b1 
                 end
-                ELSIF in_inf.vld_rdy do 
-                    insert_tri  <= (in_inf_valve.axis_tcnt >= insert_len - 1.b1 )
+                ELSIF in_inf_valve.vld_rdy do 
+                    insert_tri  <= (in_inf_valve.axis_tcnt < insert_len - 1.b1 )
+                end
+                ELSIF (in_inf_valve.axis_tcnt == 0.A).and( "~(#{in_inf.vld_rdy})".to_nq ) do 
+                    insert_tri  <= 1.b1 
                 end
                 ELSE do 
                     insert_tri  <= insert_tri
                 end
             end
             ELSE do 
-                insert_tri <= (in_inf_valve.axis_tcnt >= insert_seed - 1.b1 ).and(in_inf_valve.vld_rdy).and(in_inf_valve.axis_tcnt < insert_seed + insert_len - 1.b1).and( ~in_inf.axis_tlast)
+                IF in_inf_valve.vld_rdy do 
+                    IF (in_inf_valve.axis_tcnt >= insert_seed - 1.b1 ).and(in_inf_valve.axis_tcnt < insert_seed + insert_len - 1.b1).and( ~in_inf.axis_tlast) do 
+                        insert_tri  <= 1.b1 
+                    end
+                    ELSE do 
+                        insert_tri  <= 1.b0 
+                    end
+                end
+                ELSE do 
+                    insert_tri  <= insert_tri
+                end
+                # insert_tri <= (in_inf_valve.axis_tcnt >= insert_seed - 1.b1 ).and(in_inf_valve.vld_rdy).and(in_inf_valve.axis_tcnt < insert_seed + insert_len - 1.b1).and( ~in_inf.axis_tlast)
             end
         end
     end

data/lib/axi/AXI_stream/axis_insert_copy.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -31,34 +31,47 @@ axis_connect_pipe axis_connect_pipe_inst(
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
-assign  clock = in_inf.aclk;
-assign  rst_n = in_inf.aresetn;
+assign clock = in_inf.aclk;
+assign rst_n = in_inf.aresetn;
 
-assign  in_inf_valve.axis_tdata = in_inf.axis_tdata;
-assign  in_inf_valve.axis_tvalid = ( in_inf.axis_tvalid|insert_tri);
-assign  in_inf_valve.axis_tuser = in_inf.axis_tuser;
-assign  in_inf_valve.axis_tkeep = in_inf.axis_tkeep;
-assign  in_inf.axis_tready = ( in_inf_valve.axis_tready&~insert_tri);
-assign  in_inf_valve.axis_tlast = ( in_inf.axis_tlast&~insert_tri);
+assign in_inf_valve.axis_tdata = in_inf.axis_tdata;
+assign in_inf_valve.axis_tvalid = in_inf.axis_tvalid|insert_tri;
+assign in_inf_valve.axis_tuser = in_inf.axis_tuser;
+assign in_inf_valve.axis_tkeep = in_inf.axis_tkeep;
+assign in_inf.axis_tready = in_inf_valve.axis_tready&~insert_tri;
+assign in_inf_valve.axis_tlast = in_inf.axis_tlast&~insert_tri;
 
 always_ff@(posedge clock,negedge rst_n) begin 
     if(~rst_n)begin
-         insert_tri <= 1'b0;
+        insert_tri <= 1'b0;
     end
     else begin
-        if( insert_seed=='0)begin
+        if(insert_seed=='0)begin
             if(in_inf.axis_tvalid && in_inf.axis_tready && in_inf.axis_tlast)begin
-                 insert_tri <= 1'b1;
+                insert_tri <= 1'b1;
             end
-            else if(in_inf.axis_tvalid && in_inf.axis_tready)begin
-                 insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_len-1'b1));
+            else if(in_inf_valve.axis_tvalid && in_inf_valve.axis_tready)begin
+                insert_tri <= (in_inf_valve.axis_tcnt<(insert_len-1'b1));
+            end
+            else if(in_inf_valve.axis_tcnt=='0&&~(in_inf.axis_tvalid && in_inf.axis_tready))begin
+                insert_tri <= 1'b1;
             end
             else begin
-                 insert_tri <= insert_tri;
+                insert_tri <= insert_tri;
             end
         end
         else begin
-             insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( ( insert_seed+insert_len)-1'b1))&& ~in_inf.axis_tlast);
+            if(in_inf_valve.axis_tvalid && in_inf_valve.axis_tready)begin
+                if(in_inf_valve.axis_tcnt>=(insert_seed-1'b1) &&(in_inf_valve.axis_tcnt<((insert_seed+insert_len)-1'b1))&&~in_inf.axis_tlast)begin
+                    insert_tri <= 1'b1;
+                end
+                else begin
+                    insert_tri <= 1'b0;
+                end
+            end
+            else begin
+                insert_tri <= insert_tri;
+            end
         end
     end
 end